tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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ARM: tegra: Add OPP tables and power domains to Tegra30 device-trees

Add OPP tables and power domains to all peripheral devices which
support power management on Tegra30 SoC.

Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30
Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

authored by

Dmitry Osipenko and committed by
Thierry Reding 73e2b72a 83b7f0b8

+1395 -3
+1
arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi
··· 968 968 nvidia,core-pwr-off-time = <0>; 969 969 nvidia,core-power-req-active-high; 970 970 nvidia,sys-clock-req-active-high; 971 + core-supply = <&vdd_core>; 971 972 }; 972 973 973 974 ahub@70080000 {
+1
arch/arm/boot/dts/tegra30-beaver.dts
··· 1916 1916 nvidia,core-pwr-off-time = <0>; 1917 1917 nvidia,core-power-req-active-high; 1918 1918 nvidia,sys-clock-req-active-high; 1919 + core-supply = <&core_vdd_reg>; 1919 1920 }; 1920 1921 1921 1922 ahub@70080000 {
+1
arch/arm/boot/dts/tegra30-cardhu.dtsi
··· 393 393 nvidia,core-pwr-off-time = <0>; 394 394 nvidia,core-power-req-active-high; 395 395 nvidia,sys-clock-req-active-high; 396 + core-supply = <&vdd_core>; 396 397 }; 397 398 398 399 ahub@70080000 {
+14 -3
arch/arm/boot/dts/tegra30-colibri.dtsi
··· 767 767 768 768 vddctrl_reg: vddctrl { 769 769 regulator-name = "+V1.0_VDD_CPU"; 770 - regulator-min-microvolt = <1150000>; 771 - regulator-max-microvolt = <1150000>; 770 + regulator-min-microvolt = <800000>; 771 + regulator-max-microvolt = <1250000>; 772 + regulator-coupled-with = <&vdd_core>; 773 + regulator-coupled-max-spread = <300000>; 774 + regulator-max-step-microvolt = <100000>; 772 775 regulator-always-on; 776 + 777 + nvidia,tegra-cpu-regulator; 773 778 }; 774 779 775 780 reg_1v8_vio: vio { ··· 897 892 }; 898 893 899 894 /* SW: +V1.2_VDD_CORE */ 900 - regulator@60 { 895 + vdd_core: regulator@60 { 901 896 compatible = "ti,tps62362"; 902 897 reg = <0x60>; 903 898 904 899 regulator-name = "tps62362-vout"; 905 900 regulator-min-microvolt = <900000>; 906 901 regulator-max-microvolt = <1400000>; 902 + regulator-coupled-with = <&vddctrl_reg>; 903 + regulator-coupled-max-spread = <300000>; 904 + regulator-max-step-microvolt = <100000>; 907 905 regulator-boot-on; 908 906 regulator-always-on; 907 + 908 + nvidia,tegra-core-regulator; 909 909 }; 910 910 }; 911 911 ··· 923 913 nvidia,core-pwr-off-time = <0>; 924 914 nvidia,core-power-req-active-high; 925 915 nvidia,sys-clock-req-active-high; 916 + core-supply = <&vdd_core>; 926 917 927 918 /* Set DEV_OFF bit in DCDC control register of TPS65911 PMIC */ 928 919 i2c-thermtrip {
+1
arch/arm/boot/dts/tegra30-ouya.dts
··· 2195 2195 nvidia,core-pwr-off-time = <458>; 2196 2196 nvidia,core-power-req-active-high; 2197 2197 nvidia,sys-clock-req-active-high; 2198 + core-supply = <&vdd_core>; 2198 2199 }; 2199 2200 2200 2201 memory-controller@7000f000 {
+1224
arch/arm/boot/dts/tegra30-peripherals-opp.dtsi
··· 1 1 // SPDX-License-Identifier: GPL-2.0 2 2 3 3 / { 4 + core_opp_table: opp-table-core { 5 + compatible = "operating-points-v2"; 6 + opp-shared; 7 + 8 + core_opp_950: opp-950000 { 9 + opp-microvolt = <950000 950000 1350000>; 10 + opp-level = <950000>; 11 + }; 12 + 13 + core_opp_1000: opp-1000000 { 14 + opp-microvolt = <1000000 1000000 1350000>; 15 + opp-level = <1000000>; 16 + }; 17 + 18 + core_opp_1050: opp-1050000 { 19 + opp-microvolt = <1050000 1050000 1350000>; 20 + opp-level = <1050000>; 21 + }; 22 + 23 + core_opp_1100: opp-1100000 { 24 + opp-microvolt = <1100000 1100000 1350000>; 25 + opp-level = <1100000>; 26 + }; 27 + 28 + core_opp_1150: opp-1150000 { 29 + opp-microvolt = <1150000 1150000 1350000>; 30 + opp-level = <1150000>; 31 + }; 32 + 33 + core_opp_1200: opp-1200000 { 34 + opp-microvolt = <1200000 1200000 1350000>; 35 + opp-level = <1200000>; 36 + }; 37 + 38 + core_opp_1250: opp-1250000 { 39 + opp-microvolt = <1250000 1250000 1350000>; 40 + opp-level = <1250000>; 41 + }; 42 + 43 + core_opp_1300: opp-1300000 { 44 + opp-microvolt = <1300000 1300000 1350000>; 45 + opp-level = <1300000>; 46 + }; 47 + 48 + core_opp_1350: opp-1350000 { 49 + opp-microvolt = <1350000 1350000 1350000>; 50 + opp-level = <1350000>; 51 + }; 52 + }; 53 + 4 54 emc_icc_dvfs_opp_table: opp-table-emc { 5 55 compatible = "operating-points-v2"; 6 56 ··· 58 8 opp-microvolt = <950000 950000 1350000>; 59 9 opp-hz = /bits/ 64 <12750000>; 60 10 opp-supported-hw = <0x0006>; 11 + required-opps = <&core_opp_950>; 61 12 }; 62 13 63 14 opp-12750000-1000 { 64 15 opp-microvolt = <1000000 1000000 1350000>; 65 16 opp-hz = /bits/ 64 <12750000>; 66 17 opp-supported-hw = <0x0001>; 18 + required-opps = <&core_opp_1000>; 67 19 }; 68 20 69 21 opp-12750000-1250 { 70 22 opp-microvolt = <1250000 1250000 1350000>; 71 23 opp-hz = /bits/ 64 <12750000>; 72 24 opp-supported-hw = <0x0008>; 25 + required-opps = <&core_opp_1250>; 73 26 }; 74 27 75 28 opp-25500000-950 { 76 29 opp-microvolt = <950000 950000 1350000>; 77 30 opp-hz = /bits/ 64 <25500000>; 78 31 opp-supported-hw = <0x0006>; 32 + required-opps = <&core_opp_950>; 79 33 }; 80 34 81 35 opp-25500000-1000 { 82 36 opp-microvolt = <1000000 1000000 1350000>; 83 37 opp-hz = /bits/ 64 <25500000>; 84 38 opp-supported-hw = <0x0001>; 39 + required-opps = <&core_opp_1000>; 85 40 }; 86 41 87 42 opp-25500000-1250 { 88 43 opp-microvolt = <1250000 1250000 1350000>; 89 44 opp-hz = /bits/ 64 <25500000>; 90 45 opp-supported-hw = <0x0008>; 46 + required-opps = <&core_opp_1250>; 91 47 }; 92 48 93 49 opp-27000000-950 { 94 50 opp-microvolt = <950000 950000 1350000>; 95 51 opp-hz = /bits/ 64 <27000000>; 96 52 opp-supported-hw = <0x0006>; 53 + required-opps = <&core_opp_950>; 97 54 }; 98 55 99 56 opp-27000000-1000 { 100 57 opp-microvolt = <1000000 1000000 1350000>; 101 58 opp-hz = /bits/ 64 <27000000>; 102 59 opp-supported-hw = <0x0001>; 60 + required-opps = <&core_opp_1000>; 103 61 }; 104 62 105 63 opp-27000000-1250 { 106 64 opp-microvolt = <1250000 1250000 1350000>; 107 65 opp-hz = /bits/ 64 <27000000>; 108 66 opp-supported-hw = <0x0008>; 67 + required-opps = <&core_opp_1250>; 109 68 }; 110 69 111 70 opp-51000000-950 { 112 71 opp-microvolt = <950000 950000 1350000>; 113 72 opp-hz = /bits/ 64 <51000000>; 114 73 opp-supported-hw = <0x0006>; 74 + required-opps = <&core_opp_950>; 115 75 }; 116 76 117 77 opp-51000000-1000 { 118 78 opp-microvolt = <1000000 1000000 1350000>; 119 79 opp-hz = /bits/ 64 <51000000>; 120 80 opp-supported-hw = <0x0001>; 81 + required-opps = <&core_opp_1000>; 121 82 }; 122 83 123 84 opp-51000000-1250 { 124 85 opp-microvolt = <1250000 1250000 1350000>; 125 86 opp-hz = /bits/ 64 <51000000>; 126 87 opp-supported-hw = <0x0008>; 88 + required-opps = <&core_opp_1250>; 127 89 }; 128 90 129 91 opp-54000000-950 { 130 92 opp-microvolt = <950000 950000 1350000>; 131 93 opp-hz = /bits/ 64 <54000000>; 132 94 opp-supported-hw = <0x0006>; 95 + required-opps = <&core_opp_950>; 133 96 }; 134 97 135 98 opp-54000000-1000 { 136 99 opp-microvolt = <1000000 1000000 1350000>; 137 100 opp-hz = /bits/ 64 <54000000>; 138 101 opp-supported-hw = <0x0001>; 102 + required-opps = <&core_opp_1000>; 139 103 }; 140 104 141 105 opp-54000000-1250 { 142 106 opp-microvolt = <1250000 1250000 1350000>; 143 107 opp-hz = /bits/ 64 <54000000>; 144 108 opp-supported-hw = <0x0008>; 109 + required-opps = <&core_opp_1250>; 145 110 }; 146 111 147 112 opp-102000000-950 { 148 113 opp-microvolt = <950000 950000 1350000>; 149 114 opp-hz = /bits/ 64 <102000000>; 150 115 opp-supported-hw = <0x0006>; 116 + required-opps = <&core_opp_950>; 151 117 }; 152 118 153 119 opp-102000000-1000 { 154 120 opp-microvolt = <1000000 1000000 1350000>; 155 121 opp-hz = /bits/ 64 <102000000>; 156 122 opp-supported-hw = <0x0001>; 123 + required-opps = <&core_opp_1000>; 157 124 }; 158 125 159 126 opp-102000000-1250 { 160 127 opp-microvolt = <1250000 1250000 1350000>; 161 128 opp-hz = /bits/ 64 <102000000>; 162 129 opp-supported-hw = <0x0008>; 130 + required-opps = <&core_opp_1250>; 163 131 }; 164 132 165 133 opp-108000000-1000 { 166 134 opp-microvolt = <1000000 1000000 1350000>; 167 135 opp-hz = /bits/ 64 <108000000>; 168 136 opp-supported-hw = <0x0007>; 137 + required-opps = <&core_opp_1000>; 169 138 }; 170 139 171 140 opp-108000000-1250 { 172 141 opp-microvolt = <1250000 1250000 1350000>; 173 142 opp-hz = /bits/ 64 <108000000>; 174 143 opp-supported-hw = <0x0008>; 144 + required-opps = <&core_opp_1250>; 175 145 }; 176 146 177 147 opp-204000000-1000 { 178 148 opp-microvolt = <1000000 1000000 1350000>; 179 149 opp-hz = /bits/ 64 <204000000>; 180 150 opp-supported-hw = <0x0007>; 151 + required-opps = <&core_opp_1000>; 181 152 opp-suspend; 182 153 }; 183 154 ··· 206 135 opp-microvolt = <1250000 1250000 1350000>; 207 136 opp-hz = /bits/ 64 <204000000>; 208 137 opp-supported-hw = <0x0008>; 138 + required-opps = <&core_opp_1250>; 209 139 opp-suspend; 210 140 }; 211 141 ··· 214 142 opp-microvolt = <1000000 1000000 1350000>; 215 143 opp-hz = /bits/ 64 <333500000>; 216 144 opp-supported-hw = <0x0006>; 145 + required-opps = <&core_opp_1000>; 217 146 }; 218 147 219 148 opp-333500000-1200 { 220 149 opp-microvolt = <1200000 1200000 1350000>; 221 150 opp-hz = /bits/ 64 <333500000>; 222 151 opp-supported-hw = <0x0001>; 152 + required-opps = <&core_opp_1200>; 223 153 }; 224 154 225 155 opp-333500000-1250 { 226 156 opp-microvolt = <1250000 1250000 1350000>; 227 157 opp-hz = /bits/ 64 <333500000>; 228 158 opp-supported-hw = <0x0008>; 159 + required-opps = <&core_opp_1250>; 229 160 }; 230 161 231 162 opp-375000000-1000 { 232 163 opp-microvolt = <1000000 1000000 1350000>; 233 164 opp-hz = /bits/ 64 <375000000>; 234 165 opp-supported-hw = <0x0006>; 166 + required-opps = <&core_opp_1000>; 235 167 }; 236 168 237 169 opp-375000000-1200 { 238 170 opp-microvolt = <1200000 1200000 1350000>; 239 171 opp-hz = /bits/ 64 <375000000>; 240 172 opp-supported-hw = <0x0001>; 173 + required-opps = <&core_opp_1200>; 241 174 }; 242 175 243 176 opp-375000000-1250 { 244 177 opp-microvolt = <1250000 1250000 1350000>; 245 178 opp-hz = /bits/ 64 <375000000>; 246 179 opp-supported-hw = <0x0008>; 180 + required-opps = <&core_opp_1250>; 247 181 }; 248 182 249 183 opp-400000000-1000 { 250 184 opp-microvolt = <1000000 1000000 1350000>; 251 185 opp-hz = /bits/ 64 <400000000>; 252 186 opp-supported-hw = <0x0006>; 187 + required-opps = <&core_opp_1000>; 253 188 }; 254 189 255 190 opp-400000000-1200 { 256 191 opp-microvolt = <1200000 1200000 1350000>; 257 192 opp-hz = /bits/ 64 <400000000>; 258 193 opp-supported-hw = <0x0001>; 194 + required-opps = <&core_opp_1200>; 259 195 }; 260 196 261 197 opp-400000000-1250 { 262 198 opp-microvolt = <1250000 1250000 1350000>; 263 199 opp-hz = /bits/ 64 <400000000>; 264 200 opp-supported-hw = <0x0008>; 201 + required-opps = <&core_opp_1250>; 265 202 }; 266 203 267 204 opp-416000000-1200 { 268 205 opp-microvolt = <1200000 1200000 1350000>; 269 206 opp-hz = /bits/ 64 <416000000>; 270 207 opp-supported-hw = <0x0007>; 208 + required-opps = <&core_opp_1200>; 271 209 }; 272 210 273 211 opp-416000000-1250 { 274 212 opp-microvolt = <1250000 1250000 1350000>; 275 213 opp-hz = /bits/ 64 <416000000>; 276 214 opp-supported-hw = <0x0008>; 215 + required-opps = <&core_opp_1250>; 277 216 }; 278 217 279 218 opp-450000000-1200 { 280 219 opp-microvolt = <1200000 1200000 1350000>; 281 220 opp-hz = /bits/ 64 <450000000>; 282 221 opp-supported-hw = <0x0007>; 222 + required-opps = <&core_opp_1200>; 283 223 }; 284 224 285 225 opp-450000000-1250 { 286 226 opp-microvolt = <1250000 1250000 1350000>; 287 227 opp-hz = /bits/ 64 <450000000>; 288 228 opp-supported-hw = <0x0008>; 229 + required-opps = <&core_opp_1250>; 289 230 }; 290 231 291 232 opp-500000000-1200 { 292 233 opp-microvolt = <1200000 1200000 1350000>; 293 234 opp-hz = /bits/ 64 <500000000>; 294 235 opp-supported-hw = <0x0007>; 236 + required-opps = <&core_opp_1200>; 295 237 }; 296 238 297 239 opp-500000000-1250 { 298 240 opp-microvolt = <1250000 1250000 1350000>; 299 241 opp-hz = /bits/ 64 <500000000>; 300 242 opp-supported-hw = <0x0008>; 243 + required-opps = <&core_opp_1250>; 301 244 }; 302 245 303 246 opp-533000000-1200 { 304 247 opp-microvolt = <1200000 1200000 1350000>; 305 248 opp-hz = /bits/ 64 <533000000>; 306 249 opp-supported-hw = <0x0007>; 250 + required-opps = <&core_opp_1200>; 307 251 }; 308 252 309 253 opp-533000000-1250 { 310 254 opp-microvolt = <1250000 1250000 1350000>; 311 255 opp-hz = /bits/ 64 <533000000>; 312 256 opp-supported-hw = <0x0008>; 257 + required-opps = <&core_opp_1250>; 313 258 }; 314 259 315 260 opp-625000000-1200 { 316 261 opp-microvolt = <1200000 1200000 1350000>; 317 262 opp-hz = /bits/ 64 <625000000>; 318 263 opp-supported-hw = <0x0006>; 264 + required-opps = <&core_opp_1200>; 319 265 }; 320 266 321 267 opp-625000000-1250 { 322 268 opp-microvolt = <1250000 1250000 1350000>; 323 269 opp-hz = /bits/ 64 <625000000>; 324 270 opp-supported-hw = <0x0008>; 271 + required-opps = <&core_opp_1250>; 325 272 }; 326 273 327 274 opp-667000000-1200 { 328 275 opp-microvolt = <1200000 1200000 1350000>; 329 276 opp-hz = /bits/ 64 <667000000>; 330 277 opp-supported-hw = <0x0006>; 278 + required-opps = <&core_opp_1200>; 331 279 }; 332 280 333 281 opp-750000000-1300 { 334 282 opp-microvolt = <1300000 1300000 1350000>; 335 283 opp-hz = /bits/ 64 <750000000>; 336 284 opp-supported-hw = <0x0004>; 285 + required-opps = <&core_opp_1300>; 337 286 }; 338 287 339 288 opp-800000000-1300 { 340 289 opp-microvolt = <1300000 1300000 1350000>; 341 290 opp-hz = /bits/ 64 <800000000>; 342 291 opp-supported-hw = <0x0004>; 292 + required-opps = <&core_opp_1300>; 343 293 }; 344 294 345 295 opp-900000000-1350 { 346 296 opp-microvolt = <1350000 1350000 1350000>; 347 297 opp-hz = /bits/ 64 <900000000>; 348 298 opp-supported-hw = <0x0004>; 299 + required-opps = <&core_opp_1350>; 349 300 }; 350 301 }; 351 302 ··· 494 399 opp-hz = /bits/ 64 <900000000>; 495 400 opp-supported-hw = <0x0004>; 496 401 opp-peak-kBps = <7200000>; 402 + }; 403 + }; 404 + 405 + pcie_dvfs_opp_table: opp-table-pcie { 406 + compatible = "operating-points-v2"; 407 + 408 + opp-250000000-1000 { 409 + opp-microvolt = <1000000 1000000 1350000>; 410 + opp-hz = /bits/ 64 <250000000>; 411 + opp-supported-hw = <0x000F>; 412 + required-opps = <&core_opp_1000>; 413 + }; 414 + }; 415 + 416 + host1x_dvfs_opp_table: opp-table-host1x { 417 + compatible = "operating-points-v2"; 418 + 419 + opp-152000000-1000 { 420 + opp-microvolt = <1000000 1000000 1350000>; 421 + opp-hz = /bits/ 64 <152000000>; 422 + opp-supported-hw = <0x0007>; 423 + required-opps = <&core_opp_1000>; 424 + }; 425 + 426 + opp-188000000-1050 { 427 + opp-microvolt = <1050000 1050000 1350000>; 428 + opp-hz = /bits/ 64 <188000000>; 429 + opp-supported-hw = <0x0007>; 430 + required-opps = <&core_opp_1050>; 431 + }; 432 + 433 + opp-222000000-1100 { 434 + opp-microvolt = <1100000 1100000 1350000>; 435 + opp-hz = /bits/ 64 <222000000>; 436 + opp-supported-hw = <0x0007>; 437 + required-opps = <&core_opp_1100>; 438 + }; 439 + 440 + opp-242000000-1250 { 441 + opp-microvolt = <1250000 1250000 1350000>; 442 + opp-hz = /bits/ 64 <242000000>; 443 + opp-supported-hw = <0x0008>; 444 + required-opps = <&core_opp_1250>; 445 + }; 446 + 447 + opp-254000000-1150 { 448 + opp-microvolt = <1150000 1150000 1350000>; 449 + opp-hz = /bits/ 64 <254000000>; 450 + opp-supported-hw = <0x0007>; 451 + required-opps = <&core_opp_1150>; 452 + }; 453 + 454 + opp-267000000-1200 { 455 + opp-microvolt = <1200000 1200000 1350000>; 456 + opp-hz = /bits/ 64 <267000000>; 457 + opp-supported-hw = <0x0007>; 458 + required-opps = <&core_opp_1200>; 459 + }; 460 + 461 + opp-300000000-1350 { 462 + opp-microvolt = <1350000 1350000 1350000>; 463 + opp-hz = /bits/ 64 <300000000>; 464 + opp-supported-hw = <0x0004>; 465 + required-opps = <&core_opp_1350>; 466 + }; 467 + }; 468 + 469 + mpe_dvfs_opp_table: opp-table-mpe { 470 + compatible = "operating-points-v2"; 471 + 472 + opp-234000000-1000 { 473 + opp-microvolt = <1000000 1000000 1350000>; 474 + opp-hz = /bits/ 64 <234000000>; 475 + opp-supported-hw = <0x0003>; 476 + required-opps = <&core_opp_1000>; 477 + }; 478 + 479 + opp-247000000-1000 { 480 + opp-microvolt = <1000000 1000000 1350000>; 481 + opp-hz = /bits/ 64 <247000000>; 482 + opp-supported-hw = <0x0004>; 483 + required-opps = <&core_opp_1000>; 484 + }; 485 + 486 + opp-285000000-1050 { 487 + opp-microvolt = <1050000 1050000 1350000>; 488 + opp-hz = /bits/ 64 <285000000>; 489 + opp-supported-hw = <0x0003>; 490 + required-opps = <&core_opp_1050>; 491 + }; 492 + 493 + opp-304000000-1050 { 494 + opp-microvolt = <1050000 1050000 1350000>; 495 + opp-hz = /bits/ 64 <304000000>; 496 + opp-supported-hw = <0x0004>; 497 + required-opps = <&core_opp_1050>; 498 + }; 499 + 500 + opp-332000000-1100 { 501 + opp-microvolt = <1100000 1100000 1350000>; 502 + opp-hz = /bits/ 64 <332000000>; 503 + opp-supported-hw = <0x0003>; 504 + required-opps = <&core_opp_1100>; 505 + }; 506 + 507 + opp-361000000-1100 { 508 + opp-microvolt = <1100000 1100000 1350000>; 509 + opp-hz = /bits/ 64 <361000000>; 510 + opp-supported-hw = <0x0004>; 511 + required-opps = <&core_opp_1100>; 512 + }; 513 + 514 + opp-380000000-1150 { 515 + opp-microvolt = <1150000 1150000 1350000>; 516 + opp-hz = /bits/ 64 <380000000>; 517 + opp-supported-hw = <0x0003>; 518 + required-opps = <&core_opp_1150>; 519 + }; 520 + 521 + opp-408000000-1150 { 522 + opp-microvolt = <1150000 1150000 1350000>; 523 + opp-hz = /bits/ 64 <408000000>; 524 + opp-supported-hw = <0x0004>; 525 + required-opps = <&core_opp_1150>; 526 + }; 527 + 528 + opp-416000000-1200 { 529 + opp-microvolt = <1200000 1200000 1350000>; 530 + opp-hz = /bits/ 64 <416000000>; 531 + opp-supported-hw = <0x0003>; 532 + required-opps = <&core_opp_1200>; 533 + }; 534 + 535 + opp-446000000-1200 { 536 + opp-microvolt = <1200000 1200000 1350000>; 537 + opp-hz = /bits/ 64 <446000000>; 538 + opp-supported-hw = <0x0004>; 539 + required-opps = <&core_opp_1200>; 540 + }; 541 + 542 + opp-484000000-1250 { 543 + opp-microvolt = <1250000 1250000 1350000>; 544 + opp-hz = /bits/ 64 <484000000>; 545 + opp-supported-hw = <0x000C>; 546 + required-opps = <&core_opp_1250>; 547 + }; 548 + 549 + opp-520000000-1300 { 550 + opp-microvolt = <1300000 1300000 1350000>; 551 + opp-hz = /bits/ 64 <520000000>; 552 + opp-supported-hw = <0x0004>; 553 + required-opps = <&core_opp_1300>; 554 + }; 555 + 556 + opp-600000000-1350 { 557 + opp-microvolt = <1350000 1350000 1350000>; 558 + opp-hz = /bits/ 64 <600000000>; 559 + opp-supported-hw = <0x0004>; 560 + required-opps = <&core_opp_1350>; 561 + }; 562 + }; 563 + 564 + vi_dvfs_opp_table: opp-table-vi { 565 + compatible = "operating-points-v2"; 566 + 567 + opp-216000000-1000 { 568 + opp-microvolt = <1000000 1000000 1350000>; 569 + opp-hz = /bits/ 64 <216000000>; 570 + opp-supported-hw = <0x0003>; 571 + required-opps = <&core_opp_1000>; 572 + }; 573 + 574 + opp-219000000-1000 { 575 + opp-microvolt = <1000000 1000000 1350000>; 576 + opp-hz = /bits/ 64 <219000000>; 577 + opp-supported-hw = <0x0004>; 578 + required-opps = <&core_opp_1000>; 579 + }; 580 + 581 + opp-267000000-1050 { 582 + opp-microvolt = <1050000 1050000 1350000>; 583 + opp-hz = /bits/ 64 <267000000>; 584 + opp-supported-hw = <0x0006>; 585 + required-opps = <&core_opp_1050>; 586 + }; 587 + 588 + opp-285000000-1050 { 589 + opp-microvolt = <1050000 1050000 1350000>; 590 + opp-hz = /bits/ 64 <285000000>; 591 + opp-supported-hw = <0x0001>; 592 + required-opps = <&core_opp_1050>; 593 + }; 594 + 595 + opp-300000000-1100 { 596 + opp-microvolt = <1100000 1100000 1350000>; 597 + opp-hz = /bits/ 64 <300000000>; 598 + opp-supported-hw = <0x0007>; 599 + required-opps = <&core_opp_1100>; 600 + }; 601 + 602 + opp-371000000-1150 { 603 + opp-microvolt = <1150000 1150000 1350000>; 604 + opp-hz = /bits/ 64 <371000000>; 605 + opp-supported-hw = <0x0006>; 606 + required-opps = <&core_opp_1150>; 607 + }; 608 + 609 + opp-409000000-1200 { 610 + opp-microvolt = <1200000 1200000 1350000>; 611 + opp-hz = /bits/ 64 <409000000>; 612 + opp-supported-hw = <0x0006>; 613 + required-opps = <&core_opp_1200>; 614 + }; 615 + 616 + opp-425000000-1250 { 617 + opp-microvolt = <1250000 1250000 1350000>; 618 + opp-hz = /bits/ 64 <425000000>; 619 + opp-supported-hw = <0x0004>; 620 + required-opps = <&core_opp_1250>; 621 + }; 622 + 623 + opp-470000000-1250 { 624 + opp-microvolt = <1250000 1250000 1350000>; 625 + opp-hz = /bits/ 64 <470000000>; 626 + opp-supported-hw = <0x0008>; 627 + required-opps = <&core_opp_1250>; 628 + }; 629 + }; 630 + 631 + epp_dvfs_opp_table: opp-table-epp { 632 + compatible = "operating-points-v2"; 633 + 634 + opp-267000000-1000 { 635 + opp-microvolt = <1000000 1000000 1350000>; 636 + opp-hz = /bits/ 64 <267000000>; 637 + opp-supported-hw = <0x0007>; 638 + required-opps = <&core_opp_1000>; 639 + }; 640 + 641 + opp-285000000-1050 { 642 + opp-microvolt = <1050000 1050000 1350000>; 643 + opp-hz = /bits/ 64 <285000000>; 644 + opp-supported-hw = <0x0003>; 645 + required-opps = <&core_opp_1050>; 646 + }; 647 + 648 + opp-304000000-1050 { 649 + opp-microvolt = <1050000 1050000 1350000>; 650 + opp-hz = /bits/ 64 <304000000>; 651 + opp-supported-hw = <0x0004>; 652 + required-opps = <&core_opp_1050>; 653 + }; 654 + 655 + opp-332000000-1100 { 656 + opp-microvolt = <1100000 1100000 1350000>; 657 + opp-hz = /bits/ 64 <332000000>; 658 + opp-supported-hw = <0x0003>; 659 + required-opps = <&core_opp_1100>; 660 + }; 661 + 662 + opp-361000000-1100 { 663 + opp-microvolt = <1100000 1100000 1350000>; 664 + opp-hz = /bits/ 64 <361000000>; 665 + opp-supported-hw = <0x0004>; 666 + required-opps = <&core_opp_1100>; 667 + }; 668 + 669 + opp-380000000-1150 { 670 + opp-microvolt = <1150000 1150000 1350000>; 671 + opp-hz = /bits/ 64 <380000000>; 672 + opp-supported-hw = <0x0003>; 673 + required-opps = <&core_opp_1150>; 674 + }; 675 + 676 + opp-408000000-1150 { 677 + opp-microvolt = <1150000 1150000 1350000>; 678 + opp-hz = /bits/ 64 <408000000>; 679 + opp-supported-hw = <0x0004>; 680 + required-opps = <&core_opp_1150>; 681 + }; 682 + 683 + opp-416000000-1200 { 684 + opp-microvolt = <1200000 1200000 1350000>; 685 + opp-hz = /bits/ 64 <416000000>; 686 + opp-supported-hw = <0x0003>; 687 + required-opps = <&core_opp_1200>; 688 + }; 689 + 690 + opp-446000000-1200 { 691 + opp-microvolt = <1200000 1200000 1350000>; 692 + opp-hz = /bits/ 64 <446000000>; 693 + opp-supported-hw = <0x0004>; 694 + required-opps = <&core_opp_1200>; 695 + }; 696 + 697 + opp-484000000-1250 { 698 + opp-microvolt = <1250000 1250000 1350000>; 699 + opp-hz = /bits/ 64 <484000000>; 700 + opp-supported-hw = <0x000C>; 701 + required-opps = <&core_opp_1250>; 702 + }; 703 + 704 + opp-520000000-1300 { 705 + opp-microvolt = <1300000 1300000 1350000>; 706 + opp-hz = /bits/ 64 <520000000>; 707 + opp-supported-hw = <0x0004>; 708 + required-opps = <&core_opp_1300>; 709 + }; 710 + 711 + opp-600000000-1350 { 712 + opp-microvolt = <1350000 1350000 1350000>; 713 + opp-hz = /bits/ 64 <600000000>; 714 + opp-supported-hw = <0x0004>; 715 + required-opps = <&core_opp_1350>; 716 + }; 717 + }; 718 + 719 + gr2d_dvfs_opp_table: opp-table-gr2d { 720 + compatible = "operating-points-v2"; 721 + 722 + opp-267000000-1000 { 723 + opp-microvolt = <1000000 1000000 1350000>; 724 + opp-hz = /bits/ 64 <267000000>; 725 + opp-supported-hw = <0x0007>; 726 + required-opps = <&core_opp_1000>; 727 + }; 728 + 729 + opp-285000000-1050 { 730 + opp-microvolt = <1050000 1050000 1350000>; 731 + opp-hz = /bits/ 64 <285000000>; 732 + opp-supported-hw = <0x0003>; 733 + required-opps = <&core_opp_1050>; 734 + }; 735 + 736 + opp-304000000-1050 { 737 + opp-microvolt = <1050000 1050000 1350000>; 738 + opp-hz = /bits/ 64 <304000000>; 739 + opp-supported-hw = <0x0004>; 740 + required-opps = <&core_opp_1050>; 741 + }; 742 + 743 + opp-332000000-1100 { 744 + opp-microvolt = <1100000 1100000 1350000>; 745 + opp-hz = /bits/ 64 <332000000>; 746 + opp-supported-hw = <0x0003>; 747 + required-opps = <&core_opp_1100>; 748 + }; 749 + 750 + opp-361000000-1100 { 751 + opp-microvolt = <1100000 1100000 1350000>; 752 + opp-hz = /bits/ 64 <361000000>; 753 + opp-supported-hw = <0x0004>; 754 + required-opps = <&core_opp_1100>; 755 + }; 756 + 757 + opp-380000000-1150 { 758 + opp-microvolt = <1150000 1150000 1350000>; 759 + opp-hz = /bits/ 64 <380000000>; 760 + opp-supported-hw = <0x0003>; 761 + required-opps = <&core_opp_1150>; 762 + }; 763 + 764 + opp-408000000-1150 { 765 + opp-microvolt = <1150000 1150000 1350000>; 766 + opp-hz = /bits/ 64 <408000000>; 767 + opp-supported-hw = <0x0004>; 768 + required-opps = <&core_opp_1150>; 769 + }; 770 + 771 + opp-416000000-1200 { 772 + opp-microvolt = <1200000 1200000 1350000>; 773 + opp-hz = /bits/ 64 <416000000>; 774 + opp-supported-hw = <0x0003>; 775 + required-opps = <&core_opp_1200>; 776 + }; 777 + 778 + opp-446000000-1200 { 779 + opp-microvolt = <1200000 1200000 1350000>; 780 + opp-hz = /bits/ 64 <446000000>; 781 + opp-supported-hw = <0x0004>; 782 + required-opps = <&core_opp_1200>; 783 + }; 784 + 785 + opp-484000000-1250 { 786 + opp-microvolt = <1250000 1250000 1350000>; 787 + opp-hz = /bits/ 64 <484000000>; 788 + opp-supported-hw = <0x000C>; 789 + required-opps = <&core_opp_1250>; 790 + }; 791 + 792 + opp-520000000-1300 { 793 + opp-microvolt = <1300000 1300000 1350000>; 794 + opp-hz = /bits/ 64 <520000000>; 795 + opp-supported-hw = <0x0004>; 796 + required-opps = <&core_opp_1300>; 797 + }; 798 + 799 + opp-600000000-1350 { 800 + opp-microvolt = <1350000 1350000 1350000>; 801 + opp-hz = /bits/ 64 <600000000>; 802 + opp-supported-hw = <0x0004>; 803 + required-opps = <&core_opp_1350>; 804 + }; 805 + }; 806 + 807 + gr3d_dvfs_opp_table: opp-table-gr3d { 808 + compatible = "operating-points-v2"; 809 + 810 + opp-234000000-1000 { 811 + opp-microvolt = <1000000 1000000 1350000>; 812 + opp-hz = /bits/ 64 <234000000>; 813 + opp-supported-hw = <0x0003>; 814 + required-opps = <&core_opp_1000>, <&core_opp_1000>; 815 + }; 816 + 817 + opp-247000000-1000 { 818 + opp-microvolt = <1000000 1000000 1350000>; 819 + opp-hz = /bits/ 64 <247000000>; 820 + opp-supported-hw = <0x0004>; 821 + required-opps = <&core_opp_1000>, <&core_opp_1000>; 822 + }; 823 + 824 + opp-285000000-1050 { 825 + opp-microvolt = <1050000 1050000 1350000>; 826 + opp-hz = /bits/ 64 <285000000>; 827 + opp-supported-hw = <0x0003>; 828 + required-opps = <&core_opp_1050>, <&core_opp_1050>; 829 + }; 830 + 831 + opp-304000000-1050 { 832 + opp-microvolt = <1050000 1050000 1350000>; 833 + opp-hz = /bits/ 64 <304000000>; 834 + opp-supported-hw = <0x0004>; 835 + required-opps = <&core_opp_1050>, <&core_opp_1050>; 836 + }; 837 + 838 + opp-332000000-1100 { 839 + opp-microvolt = <1100000 1100000 1350000>; 840 + opp-hz = /bits/ 64 <332000000>; 841 + opp-supported-hw = <0x0003>; 842 + required-opps = <&core_opp_1100>, <&core_opp_1100>; 843 + }; 844 + 845 + opp-361000000-1100 { 846 + opp-microvolt = <1100000 1100000 1350000>; 847 + opp-hz = /bits/ 64 <361000000>; 848 + opp-supported-hw = <0x0004>; 849 + required-opps = <&core_opp_1100>, <&core_opp_1100>; 850 + }; 851 + 852 + opp-380000000-1150 { 853 + opp-microvolt = <1150000 1150000 1350000>; 854 + opp-hz = /bits/ 64 <380000000>; 855 + opp-supported-hw = <0x0003>; 856 + required-opps = <&core_opp_1150>, <&core_opp_1150>; 857 + }; 858 + 859 + opp-408000000-1150 { 860 + opp-microvolt = <1150000 1150000 1350000>; 861 + opp-hz = /bits/ 64 <408000000>; 862 + opp-supported-hw = <0x0004>; 863 + required-opps = <&core_opp_1150>, <&core_opp_1150>; 864 + }; 865 + 866 + opp-416000000-1200 { 867 + opp-microvolt = <1200000 1200000 1350000>; 868 + opp-hz = /bits/ 64 <416000000>; 869 + opp-supported-hw = <0x0003>; 870 + required-opps = <&core_opp_1200>, <&core_opp_1200>; 871 + }; 872 + 873 + opp-446000000-1200 { 874 + opp-microvolt = <1200000 1200000 1350000>; 875 + opp-hz = /bits/ 64 <446000000>; 876 + opp-supported-hw = <0x0004>; 877 + required-opps = <&core_opp_1200>, <&core_opp_1200>; 878 + }; 879 + 880 + opp-484000000-1250 { 881 + opp-microvolt = <1250000 1250000 1350000>; 882 + opp-hz = /bits/ 64 <484000000>; 883 + opp-supported-hw = <0x000C>; 884 + required-opps = <&core_opp_1250>, <&core_opp_1250>; 885 + }; 886 + 887 + opp-520000000-1300 { 888 + opp-microvolt = <1300000 1300000 1350000>; 889 + opp-hz = /bits/ 64 <520000000>; 890 + opp-supported-hw = <0x0004>; 891 + required-opps = <&core_opp_1300>, <&core_opp_1300>; 892 + }; 893 + 894 + opp-600000000-1350 { 895 + opp-microvolt = <1350000 1350000 1350000>; 896 + opp-hz = /bits/ 64 <600000000>; 897 + opp-supported-hw = <0x0004>; 898 + required-opps = <&core_opp_1350>, <&core_opp_1350>; 899 + }; 900 + }; 901 + 902 + disp1_dvfs_opp_table: opp-table-disp1 { 903 + compatible = "operating-points-v2"; 904 + 905 + opp-120000000-1000 { 906 + opp-microvolt = <1000000 1000000 1350000>; 907 + opp-hz = /bits/ 64 <120000000>; 908 + opp-supported-hw = <0x0009>; 909 + required-opps = <&core_opp_1000>; 910 + }; 911 + 912 + opp-155000000-1000 { 913 + opp-microvolt = <1000000 1000000 1350000>; 914 + opp-hz = /bits/ 64 <155000000>; 915 + opp-supported-hw = <0x0006>; 916 + required-opps = <&core_opp_1000>; 917 + }; 918 + 919 + opp-190000000-1200 { 920 + opp-microvolt = <1200000 1200000 1350000>; 921 + opp-hz = /bits/ 64 <190000000>; 922 + opp-supported-hw = <0x0009>; 923 + required-opps = <&core_opp_1200>; 924 + }; 925 + 926 + opp-268000000-1050 { 927 + opp-microvolt = <1050000 1050000 1350000>; 928 + opp-hz = /bits/ 64 <268000000>; 929 + opp-supported-hw = <0x0006>; 930 + required-opps = <&core_opp_1050>; 931 + }; 932 + }; 933 + 934 + disp2_dvfs_opp_table: opp-table-disp2 { 935 + compatible = "operating-points-v2"; 936 + 937 + opp-120000000-1000 { 938 + opp-microvolt = <1000000 1000000 1350000>; 939 + opp-hz = /bits/ 64 <120000000>; 940 + opp-supported-hw = <0x0009>; 941 + required-opps = <&core_opp_1000>; 942 + }; 943 + 944 + opp-155000000-1000 { 945 + opp-microvolt = <1000000 1000000 1350000>; 946 + opp-hz = /bits/ 64 <155000000>; 947 + opp-supported-hw = <0x0006>; 948 + required-opps = <&core_opp_1000>; 949 + }; 950 + 951 + opp-190000000-1200 { 952 + opp-microvolt = <1200000 1200000 1350000>; 953 + opp-hz = /bits/ 64 <190000000>; 954 + opp-supported-hw = <0x0009>; 955 + required-opps = <&core_opp_1200>; 956 + }; 957 + 958 + opp-268000000-1050 { 959 + opp-microvolt = <1050000 1050000 1350000>; 960 + opp-hz = /bits/ 64 <268000000>; 961 + opp-supported-hw = <0x0006>; 962 + required-opps = <&core_opp_1050>; 963 + }; 964 + }; 965 + 966 + hdmi_dvfs_opp_table: opp-table-hdmi { 967 + compatible = "operating-points-v2"; 968 + 969 + opp-148500000-1000 { 970 + opp-microvolt = <1000000 1000000 1350000>; 971 + opp-hz = /bits/ 64 <148500000>; 972 + opp-supported-hw = <0x000F>; 973 + required-opps = <&core_opp_1000>; 974 + }; 975 + }; 976 + 977 + tvo_dvfs_opp_table: opp-table-tvo { 978 + compatible = "operating-points-v2"; 979 + 980 + opp-297000000-1050 { 981 + opp-microvolt = <1050000 1050000 1350000>; 982 + opp-hz = /bits/ 64 <297000000>; 983 + opp-supported-hw = <0x000F>; 984 + required-opps = <&core_opp_1050>; 985 + }; 986 + }; 987 + 988 + dsia_dvfs_opp_table: opp-table-dsia { 989 + compatible = "operating-points-v2"; 990 + 991 + opp-275000000-1000 { 992 + opp-microvolt = <1000000 1000000 1350000>; 993 + opp-hz = /bits/ 64 <275000000>; 994 + opp-supported-hw = <0x000F>; 995 + required-opps = <&core_opp_1000>; 996 + }; 997 + }; 998 + 999 + dsib_dvfs_opp_table: opp-table-dsib { 1000 + compatible = "operating-points-v2"; 1001 + 1002 + opp-275000000-1000 { 1003 + opp-microvolt = <1000000 1000000 1350000>; 1004 + opp-hz = /bits/ 64 <275000000>; 1005 + opp-supported-hw = <0x000F>; 1006 + required-opps = <&core_opp_1000>; 1007 + }; 1008 + }; 1009 + 1010 + sclk_dvfs_opp_table: opp-table-sclk { 1011 + compatible = "operating-points-v2"; 1012 + 1013 + opp-51000000-950 { 1014 + opp-microvolt = <950000 950000 1350000>; 1015 + opp-hz = /bits/ 64 <51000000>; 1016 + opp-supported-hw = <0x0006>; 1017 + required-opps = <&core_opp_950>; 1018 + }; 1019 + 1020 + opp-136000000-1000 { 1021 + opp-microvolt = <1000000 1000000 1350000>; 1022 + opp-hz = /bits/ 64 <136000000>; 1023 + opp-supported-hw = <0x0001>; 1024 + required-opps = <&core_opp_1000>; 1025 + }; 1026 + 1027 + opp-164000000-1050 { 1028 + opp-microvolt = <1050000 1050000 1350000>; 1029 + opp-hz = /bits/ 64 <164000000>; 1030 + opp-supported-hw = <0x0001>; 1031 + required-opps = <&core_opp_1050>; 1032 + }; 1033 + 1034 + opp-191000000-1100 { 1035 + opp-microvolt = <1100000 1100000 1350000>; 1036 + opp-hz = /bits/ 64 <191000000>; 1037 + opp-supported-hw = <0x0001>; 1038 + required-opps = <&core_opp_1100>; 1039 + }; 1040 + 1041 + opp-205000000-1000 { 1042 + opp-microvolt = <1000000 1000000 1350000>; 1043 + opp-hz = /bits/ 64 <205000000>; 1044 + opp-supported-hw = <0x0006>; 1045 + required-opps = <&core_opp_1000>; 1046 + }; 1047 + 1048 + opp-216000000-1150 { 1049 + opp-microvolt = <1150000 1150000 1350000>; 1050 + opp-hz = /bits/ 64 <216000000>; 1051 + opp-supported-hw = <0x0001>; 1052 + required-opps = <&core_opp_1150>; 1053 + }; 1054 + 1055 + opp-227000000-1100 { 1056 + opp-microvolt = <1100000 1100000 1350000>; 1057 + opp-hz = /bits/ 64 <227000000>; 1058 + opp-supported-hw = <0x0006>; 1059 + required-opps = <&core_opp_1100>; 1060 + }; 1061 + 1062 + opp-267000000-1200 { 1063 + opp-microvolt = <1200000 1200000 1350000>; 1064 + opp-hz = /bits/ 64 <267000000>; 1065 + opp-supported-hw = <0x0006>; 1066 + required-opps = <&core_opp_1200>; 1067 + }; 1068 + 1069 + opp-334000000-1250 { 1070 + opp-microvolt = <1250000 1250000 1350000>; 1071 + opp-hz = /bits/ 64 <334000000>; 1072 + opp-supported-hw = <0x0004>; 1073 + required-opps = <&core_opp_1250>; 1074 + }; 1075 + 1076 + opp-378000000-1250 { 1077 + opp-microvolt = <1250000 1250000 1350000>; 1078 + opp-hz = /bits/ 64 <378000000>; 1079 + opp-supported-hw = <0x0008>; 1080 + required-opps = <&core_opp_1250>; 1081 + }; 1082 + }; 1083 + 1084 + pll_c_dvfs_opp_table: opp-table-pllc { 1085 + compatible = "operating-points-v2"; 1086 + 1087 + opp-533000000-950 { 1088 + opp-microvolt = <950000 950000 1350000>; 1089 + opp-hz = /bits/ 64 <533000000>; 1090 + opp-supported-hw = <0x000F>; 1091 + required-opps = <&core_opp_950>; 1092 + }; 1093 + 1094 + opp-667000000-1000 { 1095 + opp-microvolt = <1000000 1000000 1350000>; 1096 + opp-hz = /bits/ 64 <667000000>; 1097 + opp-supported-hw = <0x000F>; 1098 + required-opps = <&core_opp_1000>; 1099 + }; 1100 + 1101 + opp-800000000-1100 { 1102 + opp-microvolt = <1100000 1100000 1350000>; 1103 + opp-hz = /bits/ 64 <800000000>; 1104 + opp-supported-hw = <0x000F>; 1105 + required-opps = <&core_opp_1100>; 1106 + }; 1107 + 1108 + opp-1066000000-1200 { 1109 + opp-microvolt = <1200000 1200000 1350000>; 1110 + opp-hz = /bits/ 64 <1066000000>; 1111 + opp-supported-hw = <0x000F>; 1112 + required-opps = <&core_opp_1200>; 1113 + }; 1114 + 1115 + opp-1200000000-1350 { 1116 + opp-microvolt = <1350000 1350000 1350000>; 1117 + opp-hz = /bits/ 64 <1200000000>; 1118 + opp-supported-hw = <0x000F>; 1119 + required-opps = <&core_opp_1350>; 1120 + }; 1121 + }; 1122 + 1123 + pll_e_dvfs_opp_table: opp-table-plle { 1124 + compatible = "operating-points-v2"; 1125 + 1126 + opp-100000000-1000 { 1127 + opp-microvolt = <1000000 1000000 1350000>; 1128 + opp-hz = /bits/ 64 <100000000>; 1129 + opp-supported-hw = <0x000F>; 1130 + required-opps = <&core_opp_1000>; 1131 + }; 1132 + }; 1133 + 1134 + pll_m_dvfs_opp_table: opp-table-pllm { 1135 + compatible = "operating-points-v2"; 1136 + 1137 + opp-533000000-950 { 1138 + opp-microvolt = <950000 950000 1350000>; 1139 + opp-hz = /bits/ 64 <533000000>; 1140 + opp-supported-hw = <0x000F>; 1141 + required-opps = <&core_opp_950>; 1142 + }; 1143 + 1144 + opp-667000000-1000 { 1145 + opp-microvolt = <1000000 1000000 1350000>; 1146 + opp-hz = /bits/ 64 <667000000>; 1147 + opp-supported-hw = <0x000F>; 1148 + required-opps = <&core_opp_1000>; 1149 + }; 1150 + 1151 + opp-800000000-1100 { 1152 + opp-microvolt = <1100000 1100000 1350000>; 1153 + opp-hz = /bits/ 64 <800000000>; 1154 + opp-supported-hw = <0x000F>; 1155 + required-opps = <&core_opp_1100>; 1156 + }; 1157 + 1158 + opp-1066000000-1200 { 1159 + opp-microvolt = <1200000 1200000 1350000>; 1160 + opp-hz = /bits/ 64 <1066000000>; 1161 + opp-supported-hw = <0x000F>; 1162 + required-opps = <&core_opp_1200>; 1163 + }; 1164 + }; 1165 + 1166 + vde_dvfs_opp_table: opp-table-vde { 1167 + compatible = "operating-points-v2"; 1168 + 1169 + opp-228000000-1000 { 1170 + opp-microvolt = <1000000 1000000 1350000>; 1171 + opp-hz = /bits/ 64 <228000000>; 1172 + opp-supported-hw = <0x0003>; 1173 + required-opps = <&core_opp_1000>; 1174 + }; 1175 + 1176 + opp-247000000-1000 { 1177 + opp-microvolt = <1000000 1000000 1350000>; 1178 + opp-hz = /bits/ 64 <247000000>; 1179 + opp-supported-hw = <0x0004>; 1180 + required-opps = <&core_opp_1000>; 1181 + }; 1182 + 1183 + opp-275000000-1050 { 1184 + opp-microvolt = <1050000 1050000 1350000>; 1185 + opp-hz = /bits/ 64 <275000000>; 1186 + opp-supported-hw = <0x0003>; 1187 + required-opps = <&core_opp_1050>; 1188 + }; 1189 + 1190 + opp-304000000-1050 { 1191 + opp-microvolt = <1050000 1050000 1350000>; 1192 + opp-hz = /bits/ 64 <304000000>; 1193 + opp-supported-hw = <0x0004>; 1194 + required-opps = <&core_opp_1050>; 1195 + }; 1196 + 1197 + opp-332000000-1100 { 1198 + opp-microvolt = <1100000 1100000 1350000>; 1199 + opp-hz = /bits/ 64 <332000000>; 1200 + opp-supported-hw = <0x0003>; 1201 + required-opps = <&core_opp_1100>; 1202 + }; 1203 + 1204 + opp-352000000-1100 { 1205 + opp-microvolt = <1100000 1100000 1350000>; 1206 + opp-hz = /bits/ 64 <352000000>; 1207 + opp-supported-hw = <0x0004>; 1208 + required-opps = <&core_opp_1100>; 1209 + }; 1210 + 1211 + opp-380000000-1150 { 1212 + opp-microvolt = <1150000 1150000 1350000>; 1213 + opp-hz = /bits/ 64 <380000000>; 1214 + opp-supported-hw = <0x0003>; 1215 + required-opps = <&core_opp_1150>; 1216 + }; 1217 + 1218 + opp-400000000-1150 { 1219 + opp-microvolt = <1150000 1150000 1350000>; 1220 + opp-hz = /bits/ 64 <400000000>; 1221 + opp-supported-hw = <0x0004>; 1222 + required-opps = <&core_opp_1150>; 1223 + }; 1224 + 1225 + opp-416000000-1200 { 1226 + opp-microvolt = <1200000 1200000 1350000>; 1227 + opp-hz = /bits/ 64 <416000000>; 1228 + opp-supported-hw = <0x0003>; 1229 + required-opps = <&core_opp_1200>; 1230 + }; 1231 + 1232 + opp-437000000-1200 { 1233 + opp-microvolt = <1200000 1200000 1350000>; 1234 + opp-hz = /bits/ 64 <437000000>; 1235 + opp-supported-hw = <0x0004>; 1236 + required-opps = <&core_opp_1200>; 1237 + }; 1238 + 1239 + opp-484000000-1250 { 1240 + opp-microvolt = <1250000 1250000 1350000>; 1241 + opp-hz = /bits/ 64 <484000000>; 1242 + opp-supported-hw = <0x000C>; 1243 + required-opps = <&core_opp_1250>; 1244 + }; 1245 + 1246 + opp-520000000-1300 { 1247 + opp-microvolt = <1300000 1300000 1350000>; 1248 + opp-hz = /bits/ 64 <520000000>; 1249 + opp-supported-hw = <0x0004>; 1250 + required-opps = <&core_opp_1300>; 1251 + }; 1252 + 1253 + opp-600000000-1350 { 1254 + opp-microvolt = <1350000 1350000 1350000>; 1255 + opp-hz = /bits/ 64 <600000000>; 1256 + opp-supported-hw = <0x0004>; 1257 + required-opps = <&core_opp_1350>; 1258 + }; 1259 + }; 1260 + 1261 + fuse_burn_dvfs_opp_table: opp-table-fuseburn { 1262 + compatible = "operating-points-v2"; 1263 + 1264 + opp-26000000-1150 { 1265 + opp-microvolt = <1150000 1150000 1350000>; 1266 + opp-hz = /bits/ 64 <26000000>; 1267 + opp-supported-hw = <0x000F>; 1268 + required-opps = <&core_opp_1150>; 1269 + }; 1270 + }; 1271 + 1272 + nor_dvfs_opp_table: opp-table-nor { 1273 + compatible = "operating-points-v2"; 1274 + 1275 + opp-108000000-1250 { 1276 + opp-microvolt = <1250000 1250000 1350000>; 1277 + opp-hz = /bits/ 64 <108000000>; 1278 + opp-supported-hw = <0x0008>; 1279 + required-opps = <&core_opp_1250>; 1280 + }; 1281 + 1282 + opp-115000000-1000 { 1283 + opp-microvolt = <1000000 1000000 1350000>; 1284 + opp-hz = /bits/ 64 <115000000>; 1285 + opp-supported-hw = <0x0007>; 1286 + required-opps = <&core_opp_1000>; 1287 + }; 1288 + 1289 + opp-130000000-1050 { 1290 + opp-microvolt = <1050000 1050000 1350000>; 1291 + opp-hz = /bits/ 64 <130000000>; 1292 + opp-supported-hw = <0x0007>; 1293 + required-opps = <&core_opp_1050>; 1294 + }; 1295 + 1296 + opp-133000000-1150 { 1297 + opp-microvolt = <1150000 1150000 1350000>; 1298 + opp-hz = /bits/ 64 <133000000>; 1299 + opp-supported-hw = <0x0007>; 1300 + required-opps = <&core_opp_1150>; 1301 + }; 1302 + }; 1303 + 1304 + pwm_dvfs_opp_table: opp-table-pwm { 1305 + compatible = "operating-points-v2"; 1306 + 1307 + opp-408000000-1000 { 1308 + opp-microvolt = <1000000 1000000 1350000>; 1309 + opp-hz = /bits/ 64 <408000000>; 1310 + opp-supported-hw = <0x000F>; 1311 + required-opps = <&core_opp_1000>; 1312 + }; 1313 + }; 1314 + 1315 + sbc1_dvfs_opp_table: opp-table-sbc1 { 1316 + compatible = "operating-points-v2"; 1317 + 1318 + opp-52000000-1000 { 1319 + opp-microvolt = <1000000 1000000 1350000>; 1320 + opp-hz = /bits/ 64 <52000000>; 1321 + opp-supported-hw = <0x000F>; 1322 + required-opps = <&core_opp_1000>; 1323 + }; 1324 + 1325 + opp-60000000-1050 { 1326 + opp-microvolt = <1050000 1050000 1350000>; 1327 + opp-hz = /bits/ 64 <60000000>; 1328 + opp-supported-hw = <0x000F>; 1329 + required-opps = <&core_opp_1050>; 1330 + }; 1331 + 1332 + opp-100000000-1200 { 1333 + opp-microvolt = <1200000 1200000 1350000>; 1334 + opp-hz = /bits/ 64 <100000000>; 1335 + opp-supported-hw = <0x000F>; 1336 + required-opps = <&core_opp_1200>; 1337 + }; 1338 + }; 1339 + 1340 + sbc2_dvfs_opp_table: opp-table-sbc2 { 1341 + compatible = "operating-points-v2"; 1342 + 1343 + opp-52000000-1000 { 1344 + opp-microvolt = <1000000 1000000 1350000>; 1345 + opp-hz = /bits/ 64 <52000000>; 1346 + opp-supported-hw = <0x000F>; 1347 + required-opps = <&core_opp_1000>; 1348 + }; 1349 + 1350 + opp-60000000-1050 { 1351 + opp-microvolt = <1050000 1050000 1350000>; 1352 + opp-hz = /bits/ 64 <60000000>; 1353 + opp-supported-hw = <0x000F>; 1354 + required-opps = <&core_opp_1050>; 1355 + }; 1356 + 1357 + opp-100000000-1200 { 1358 + opp-microvolt = <1200000 1200000 1350000>; 1359 + opp-hz = /bits/ 64 <100000000>; 1360 + opp-supported-hw = <0x000F>; 1361 + required-opps = <&core_opp_1200>; 1362 + }; 1363 + }; 1364 + 1365 + sbc3_dvfs_opp_table: opp-table-sbc3 { 1366 + compatible = "operating-points-v2"; 1367 + 1368 + opp-52000000-1000 { 1369 + opp-microvolt = <1000000 1000000 1350000>; 1370 + opp-hz = /bits/ 64 <52000000>; 1371 + opp-supported-hw = <0x000F>; 1372 + required-opps = <&core_opp_1000>; 1373 + }; 1374 + 1375 + opp-60000000-1050 { 1376 + opp-microvolt = <1050000 1050000 1350000>; 1377 + opp-hz = /bits/ 64 <60000000>; 1378 + opp-supported-hw = <0x000F>; 1379 + required-opps = <&core_opp_1050>; 1380 + }; 1381 + 1382 + opp-100000000-1200 { 1383 + opp-microvolt = <1200000 1200000 1350000>; 1384 + opp-hz = /bits/ 64 <100000000>; 1385 + opp-supported-hw = <0x000F>; 1386 + required-opps = <&core_opp_1200>; 1387 + }; 1388 + }; 1389 + 1390 + sbc4_dvfs_opp_table: opp-table-sbc4 { 1391 + compatible = "operating-points-v2"; 1392 + 1393 + opp-52000000-1000 { 1394 + opp-microvolt = <1000000 1000000 1350000>; 1395 + opp-hz = /bits/ 64 <52000000>; 1396 + opp-supported-hw = <0x000F>; 1397 + required-opps = <&core_opp_1000>; 1398 + }; 1399 + 1400 + opp-60000000-1050 { 1401 + opp-microvolt = <1050000 1050000 1350000>; 1402 + opp-hz = /bits/ 64 <60000000>; 1403 + opp-supported-hw = <0x000F>; 1404 + required-opps = <&core_opp_1050>; 1405 + }; 1406 + 1407 + opp-100000000-1200 { 1408 + opp-microvolt = <1200000 1200000 1350000>; 1409 + opp-hz = /bits/ 64 <100000000>; 1410 + opp-supported-hw = <0x000F>; 1411 + required-opps = <&core_opp_1200>; 1412 + }; 1413 + }; 1414 + 1415 + sbc5_dvfs_opp_table: opp-table-sbc5 { 1416 + compatible = "operating-points-v2"; 1417 + 1418 + opp-52000000-1000 { 1419 + opp-microvolt = <1000000 1000000 1350000>; 1420 + opp-hz = /bits/ 64 <52000000>; 1421 + opp-supported-hw = <0x000F>; 1422 + required-opps = <&core_opp_1000>; 1423 + }; 1424 + 1425 + opp-60000000-1050 { 1426 + opp-microvolt = <1050000 1050000 1350000>; 1427 + opp-hz = /bits/ 64 <60000000>; 1428 + opp-supported-hw = <0x000F>; 1429 + required-opps = <&core_opp_1050>; 1430 + }; 1431 + 1432 + opp-100000000-1200 { 1433 + opp-microvolt = <1200000 1200000 1350000>; 1434 + opp-hz = /bits/ 64 <100000000>; 1435 + opp-supported-hw = <0x000F>; 1436 + required-opps = <&core_opp_1200>; 1437 + }; 1438 + }; 1439 + 1440 + sbc6_dvfs_opp_table: opp-table-sbc6 { 1441 + compatible = "operating-points-v2"; 1442 + 1443 + opp-52000000-1000 { 1444 + opp-microvolt = <1000000 1000000 1350000>; 1445 + opp-hz = /bits/ 64 <52000000>; 1446 + opp-supported-hw = <0x000F>; 1447 + required-opps = <&core_opp_1000>; 1448 + }; 1449 + 1450 + opp-60000000-1050 { 1451 + opp-microvolt = <1050000 1050000 1350000>; 1452 + opp-hz = /bits/ 64 <60000000>; 1453 + opp-supported-hw = <0x000F>; 1454 + required-opps = <&core_opp_1050>; 1455 + }; 1456 + 1457 + opp-100000000-1200 { 1458 + opp-microvolt = <1200000 1200000 1350000>; 1459 + opp-hz = /bits/ 64 <100000000>; 1460 + opp-supported-hw = <0x000F>; 1461 + required-opps = <&core_opp_1200>; 1462 + }; 1463 + }; 1464 + 1465 + sdmmc1_dvfs_opp_table: opp-table-sdmmc1 { 1466 + compatible = "operating-points-v2"; 1467 + 1468 + opp-104000000-950 { 1469 + opp-microvolt = <950000 950000 1350000>; 1470 + opp-hz = /bits/ 64 <104000000>; 1471 + opp-supported-hw = <0x000F>; 1472 + required-opps = <&core_opp_950>; 1473 + }; 1474 + 1475 + opp-208000000-1200 { 1476 + opp-microvolt = <1200000 1200000 1350000>; 1477 + opp-hz = /bits/ 64 <208000000>; 1478 + opp-supported-hw = <0x000F>; 1479 + required-opps = <&core_opp_1200>; 1480 + }; 1481 + }; 1482 + 1483 + sdmmc3_dvfs_opp_table: opp-table-sdmmc3 { 1484 + compatible = "operating-points-v2"; 1485 + 1486 + opp-104000000-950 { 1487 + opp-microvolt = <950000 950000 1350000>; 1488 + opp-hz = /bits/ 64 <104000000>; 1489 + opp-supported-hw = <0x000F>; 1490 + required-opps = <&core_opp_950>; 1491 + }; 1492 + 1493 + opp-208000000-1200 { 1494 + opp-microvolt = <1200000 1200000 1350000>; 1495 + opp-hz = /bits/ 64 <208000000>; 1496 + opp-supported-hw = <0x000F>; 1497 + required-opps = <&core_opp_1200>; 1498 + }; 1499 + }; 1500 + 1501 + usbd_dvfs_opp_table: opp-table-usbd { 1502 + compatible = "operating-points-v2"; 1503 + 1504 + opp-480000000-1000 { 1505 + opp-microvolt = <1000000 1000000 1350000>; 1506 + opp-hz = /bits/ 64 <480000000>; 1507 + opp-supported-hw = <0x000F>; 1508 + required-opps = <&core_opp_1000>; 1509 + }; 1510 + }; 1511 + 1512 + usb2_dvfs_opp_table: opp-table-usb2 { 1513 + compatible = "operating-points-v2"; 1514 + 1515 + opp-480000000-1000 { 1516 + opp-microvolt = <1000000 1000000 1350000>; 1517 + opp-hz = /bits/ 64 <480000000>; 1518 + opp-supported-hw = <0x000F>; 1519 + required-opps = <&core_opp_1000>; 1520 + }; 1521 + }; 1522 + 1523 + usb3_dvfs_opp_table: opp-table-usb3 { 1524 + compatible = "operating-points-v2"; 1525 + 1526 + opp-480000000-1000 { 1527 + opp-microvolt = <1000000 1000000 1350000>; 1528 + opp-hz = /bits/ 64 <480000000>; 1529 + opp-supported-hw = <0x000F>; 1530 + required-opps = <&core_opp_1000>; 497 1531 }; 498 1532 }; 499 1533 };
+153
arch/arm/boot/dts/tegra30.dtsi
··· 55 55 <&tegra_car 72>, 56 56 <&tegra_car 74>; 57 57 reset-names = "pex", "afi", "pcie_x"; 58 + power-domains = <&pd_core>; 59 + operating-points-v2 = <&pcie_dvfs_opp_table>; 58 60 status = "disabled"; 59 61 60 62 pci@1,0 { ··· 126 124 resets = <&tegra_car 28>; 127 125 reset-names = "host1x"; 128 126 iommus = <&mc TEGRA_SWGROUP_HC>; 127 + power-domains = <&pd_heg>; 128 + operating-points-v2 = <&host1x_dvfs_opp_table>; 129 129 130 130 #address-cells = <1>; 131 131 #size-cells = <1>; ··· 141 137 clocks = <&tegra_car TEGRA30_CLK_MPE>; 142 138 resets = <&tegra_car 60>; 143 139 reset-names = "mpe"; 140 + power-domains = <&pd_mpe>; 141 + operating-points-v2 = <&mpe_dvfs_opp_table>; 144 142 145 143 iommus = <&mc TEGRA_SWGROUP_MPE>; 146 144 }; ··· 154 148 clocks = <&tegra_car TEGRA30_CLK_VI>; 155 149 resets = <&tegra_car 20>; 156 150 reset-names = "vi"; 151 + power-domains = <&pd_venc>; 152 + operating-points-v2 = <&vi_dvfs_opp_table>; 157 153 158 154 iommus = <&mc TEGRA_SWGROUP_VI>; 159 155 }; ··· 167 159 clocks = <&tegra_car TEGRA30_CLK_EPP>; 168 160 resets = <&tegra_car 19>; 169 161 reset-names = "epp"; 162 + power-domains = <&pd_heg>; 163 + operating-points-v2 = <&epp_dvfs_opp_table>; 170 164 171 165 iommus = <&mc TEGRA_SWGROUP_EPP>; 172 166 }; ··· 180 170 clocks = <&tegra_car TEGRA30_CLK_ISP>; 181 171 resets = <&tegra_car 23>; 182 172 reset-names = "isp"; 173 + power-domains = <&pd_venc>; 183 174 184 175 iommus = <&mc TEGRA_SWGROUP_ISP>; 185 176 }; ··· 192 181 clocks = <&tegra_car TEGRA30_CLK_GR2D>; 193 182 resets = <&tegra_car 21>; 194 183 reset-names = "2d"; 184 + power-domains = <&pd_heg>; 185 + operating-points-v2 = <&gr2d_dvfs_opp_table>; 195 186 196 187 iommus = <&mc TEGRA_SWGROUP_G2>; 197 188 }; ··· 207 194 resets = <&tegra_car 24>, 208 195 <&tegra_car 98>; 209 196 reset-names = "3d", "3d2"; 197 + power-domains = <&pd_3d0>, <&pd_3d1>; 198 + power-domain-names = "3d0", "3d1"; 199 + operating-points-v2 = <&gr3d_dvfs_opp_table>; 210 200 211 201 iommus = <&mc TEGRA_SWGROUP_NV>, 212 202 <&mc TEGRA_SWGROUP_NV2>; ··· 224 208 clock-names = "dc", "parent"; 225 209 resets = <&tegra_car 27>; 226 210 reset-names = "dc"; 211 + power-domains = <&pd_core>; 212 + operating-points-v2 = <&disp1_dvfs_opp_table>; 227 213 228 214 iommus = <&mc TEGRA_SWGROUP_DC>; 229 215 ··· 256 238 clock-names = "dc", "parent"; 257 239 resets = <&tegra_car 26>; 258 240 reset-names = "dc"; 241 + power-domains = <&pd_core>; 242 + operating-points-v2 = <&disp2_dvfs_opp_table>; 259 243 260 244 iommus = <&mc TEGRA_SWGROUP_DCB>; 261 245 ··· 288 268 clock-names = "hdmi", "parent"; 289 269 resets = <&tegra_car 51>; 290 270 reset-names = "hdmi"; 271 + power-domains = <&pd_core>; 272 + operating-points-v2 = <&hdmi_dvfs_opp_table>; 291 273 status = "disabled"; 292 274 }; 293 275 ··· 298 276 reg = <0x542c0000 0x00040000>; 299 277 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 300 278 clocks = <&tegra_car TEGRA30_CLK_TVO>; 279 + power-domains = <&pd_core>; 280 + operating-points-v2 = <&tvo_dvfs_opp_table>; 301 281 status = "disabled"; 302 282 }; 303 283 ··· 311 287 clock-names = "dsi", "parent"; 312 288 resets = <&tegra_car 48>; 313 289 reset-names = "dsi"; 290 + power-domains = <&pd_core>; 291 + operating-points-v2 = <&dsia_dvfs_opp_table>; 314 292 status = "disabled"; 315 293 }; 316 294 ··· 324 298 clock-names = "dsi", "parent"; 325 299 resets = <&tegra_car 84>; 326 300 reset-names = "dsi"; 301 + power-domains = <&pd_core>; 302 + operating-points-v2 = <&dsib_dvfs_opp_table>; 327 303 status = "disabled"; 328 304 }; 329 305 }; ··· 386 358 reg = <0x60006000 0x1000>; 387 359 #clock-cells = <1>; 388 360 #reset-cells = <1>; 361 + 362 + sclk { 363 + compatible = "nvidia,tegra30-sclk"; 364 + clocks = <&tegra_car TEGRA30_CLK_SCLK>; 365 + power-domains = <&pd_core>; 366 + operating-points-v2 = <&sclk_dvfs_opp_table>; 367 + }; 368 + 369 + pll-c { 370 + compatible = "nvidia,tegra30-pllc"; 371 + clocks = <&tegra_car TEGRA30_CLK_PLL_C>; 372 + power-domains = <&pd_core>; 373 + operating-points-v2 = <&pll_c_dvfs_opp_table>; 374 + }; 375 + 376 + pll-e { 377 + compatible = "nvidia,tegra30-plle"; 378 + clocks = <&tegra_car TEGRA30_CLK_PLL_E>; 379 + power-domains = <&pd_core>; 380 + operating-points-v2 = <&pll_e_dvfs_opp_table>; 381 + }; 382 + 383 + pll-m { 384 + compatible = "nvidia,tegra30-pllm"; 385 + clocks = <&tegra_car TEGRA30_CLK_PLL_M>; 386 + power-domains = <&pd_core>; 387 + operating-points-v2 = <&pll_m_dvfs_opp_table>; 388 + }; 389 389 }; 390 390 391 391 flow-controller@60007000 { ··· 524 468 reset-names = "vde", "mc"; 525 469 resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>; 526 470 iommus = <&mc TEGRA_SWGROUP_VDE>; 471 + power-domains = <&pd_vde>; 472 + operating-points-v2 = <&vde_dvfs_opp_table>; 527 473 }; 528 474 529 475 apbmisc@70000800 { ··· 623 565 clock-names = "gmi"; 624 566 resets = <&tegra_car 42>; 625 567 reset-names = "gmi"; 568 + power-domains = <&pd_core>; 569 + operating-points-v2 = <&nor_dvfs_opp_table>; 626 570 status = "disabled"; 627 571 }; 628 572 ··· 635 575 clocks = <&tegra_car TEGRA30_CLK_PWM>; 636 576 resets = <&tegra_car 17>; 637 577 reset-names = "pwm"; 578 + power-domains = <&pd_core>; 579 + operating-points-v2 = <&pwm_dvfs_opp_table>; 638 580 status = "disabled"; 639 581 }; 640 582 ··· 738 676 reset-names = "spi"; 739 677 dmas = <&apbdma 15>, <&apbdma 15>; 740 678 dma-names = "rx", "tx"; 679 + power-domains = <&pd_core>; 680 + operating-points-v2 = <&sbc1_dvfs_opp_table>; 741 681 status = "disabled"; 742 682 }; 743 683 ··· 754 690 reset-names = "spi"; 755 691 dmas = <&apbdma 16>, <&apbdma 16>; 756 692 dma-names = "rx", "tx"; 693 + power-domains = <&pd_core>; 694 + operating-points-v2 = <&sbc2_dvfs_opp_table>; 757 695 status = "disabled"; 758 696 }; 759 697 ··· 770 704 reset-names = "spi"; 771 705 dmas = <&apbdma 17>, <&apbdma 17>; 772 706 dma-names = "rx", "tx"; 707 + power-domains = <&pd_core>; 708 + operating-points-v2 = <&sbc3_dvfs_opp_table>; 773 709 status = "disabled"; 774 710 }; 775 711 ··· 786 718 reset-names = "spi"; 787 719 dmas = <&apbdma 18>, <&apbdma 18>; 788 720 dma-names = "rx", "tx"; 721 + power-domains = <&pd_core>; 722 + operating-points-v2 = <&sbc4_dvfs_opp_table>; 789 723 status = "disabled"; 790 724 }; 791 725 ··· 802 732 reset-names = "spi"; 803 733 dmas = <&apbdma 27>, <&apbdma 27>; 804 734 dma-names = "rx", "tx"; 735 + power-domains = <&pd_core>; 736 + operating-points-v2 = <&sbc5_dvfs_opp_table>; 805 737 status = "disabled"; 806 738 }; 807 739 ··· 818 746 reset-names = "spi"; 819 747 dmas = <&apbdma 28>, <&apbdma 28>; 820 748 dma-names = "rx", "tx"; 749 + power-domains = <&pd_core>; 750 + operating-points-v2 = <&sbc6_dvfs_opp_table>; 821 751 status = "disabled"; 822 752 }; 823 753 ··· 839 765 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; 840 766 clock-names = "pclk", "clk32k_in"; 841 767 #clock-cells = <1>; 768 + 769 + pd_core: core-domain { 770 + #power-domain-cells = <0>; 771 + operating-points-v2 = <&core_opp_table>; 772 + }; 773 + 774 + powergates { 775 + pd_3d0: td { 776 + clocks = <&tegra_car TEGRA30_CLK_GR3D>; 777 + resets = <&mc TEGRA30_MC_RESET_3D>, 778 + <&tegra_car TEGRA30_CLK_GR3D>; 779 + power-domains = <&pd_core>; 780 + #power-domain-cells = <0>; 781 + }; 782 + 783 + pd_3d1: td2 { 784 + clocks = <&tegra_car TEGRA30_CLK_GR3D2>; 785 + resets = <&mc TEGRA30_MC_RESET_3D2>, 786 + <&tegra_car TEGRA30_CLK_GR3D2>; 787 + power-domains = <&pd_core>; 788 + #power-domain-cells = <0>; 789 + }; 790 + 791 + pd_venc: venc { 792 + clocks = <&tegra_car TEGRA30_CLK_ISP>, 793 + <&tegra_car TEGRA30_CLK_VI>, 794 + <&tegra_car TEGRA30_CLK_CSI>; 795 + resets = <&mc TEGRA30_MC_RESET_ISP>, 796 + <&mc TEGRA30_MC_RESET_VI>, 797 + <&tegra_car TEGRA30_CLK_ISP>, 798 + <&tegra_car 20 /* VI */>, 799 + <&tegra_car TEGRA30_CLK_CSI>; 800 + power-domains = <&pd_core>; 801 + #power-domain-cells = <0>; 802 + }; 803 + 804 + pd_vde: vdec { 805 + clocks = <&tegra_car TEGRA30_CLK_VDE>; 806 + resets = <&mc TEGRA30_MC_RESET_VDE>, 807 + <&tegra_car TEGRA30_CLK_VDE>; 808 + power-domains = <&pd_core>; 809 + #power-domain-cells = <0>; 810 + }; 811 + 812 + pd_mpe: mpe { 813 + clocks = <&tegra_car TEGRA30_CLK_MPE>; 814 + resets = <&mc TEGRA30_MC_RESET_MPE>, 815 + <&tegra_car TEGRA30_CLK_MPE>; 816 + power-domains = <&pd_core>; 817 + #power-domain-cells = <0>; 818 + }; 819 + 820 + pd_heg: heg { 821 + clocks = <&tegra_car TEGRA30_CLK_GR2D>, 822 + <&tegra_car TEGRA30_CLK_EPP>, 823 + <&tegra_car TEGRA30_CLK_HOST1X>; 824 + resets = <&mc TEGRA30_MC_RESET_2D>, 825 + <&mc TEGRA30_MC_RESET_EPP>, 826 + <&mc TEGRA30_MC_RESET_HC>, 827 + <&tegra_car TEGRA30_CLK_GR2D>, 828 + <&tegra_car TEGRA30_CLK_EPP>, 829 + <&tegra_car TEGRA30_CLK_HOST1X>; 830 + power-domains = <&pd_core>; 831 + #power-domain-cells = <0>; 832 + }; 833 + }; 842 834 }; 843 835 844 836 mc: memory-controller@7000f000 { ··· 925 785 reg = <0x7000f400 0x400>; 926 786 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 927 787 clocks = <&tegra_car TEGRA30_CLK_EMC>; 788 + power-domains = <&pd_core>; 928 789 929 790 nvidia,memory-controller = <&mc>; 930 791 operating-points-v2 = <&emc_icc_dvfs_opp_table>; ··· 940 799 clock-names = "fuse"; 941 800 resets = <&tegra_car 39>; 942 801 reset-names = "fuse"; 802 + power-domains = <&pd_core>; 803 + operating-points-v2 = <&fuse_burn_dvfs_opp_table>; 943 804 }; 944 805 945 806 tsensor: tsensor@70014000 { ··· 1064 921 clock-names = "sdhci"; 1065 922 resets = <&tegra_car 14>; 1066 923 reset-names = "sdhci"; 924 + power-domains = <&pd_core>; 925 + operating-points-v2 = <&sdmmc1_dvfs_opp_table>; 1067 926 status = "disabled"; 1068 927 }; 1069 928 ··· 1088 943 clock-names = "sdhci"; 1089 944 resets = <&tegra_car 69>; 1090 945 reset-names = "sdhci"; 946 + power-domains = <&pd_core>; 947 + operating-points-v2 = <&sdmmc3_dvfs_opp_table>; 1091 948 status = "disabled"; 1092 949 }; 1093 950 ··· 1114 967 reset-names = "usb"; 1115 968 nvidia,needs-double-reset; 1116 969 nvidia,phy = <&phy1>; 970 + power-domains = <&pd_core>; 971 + operating-points-v2 = <&usbd_dvfs_opp_table>; 1117 972 status = "disabled"; 1118 973 }; 1119 974 ··· 1157 1008 resets = <&tegra_car 58>; 1158 1009 reset-names = "usb"; 1159 1010 nvidia,phy = <&phy2>; 1011 + power-domains = <&pd_core>; 1012 + operating-points-v2 = <&usb2_dvfs_opp_table>; 1160 1013 status = "disabled"; 1161 1014 }; 1162 1015 ··· 1199 1048 resets = <&tegra_car 59>; 1200 1049 reset-names = "usb"; 1201 1050 nvidia,phy = <&phy3>; 1051 + power-domains = <&pd_core>; 1052 + operating-points-v2 = <&usb3_dvfs_opp_table>; 1202 1053 status = "disabled"; 1203 1054 }; 1204 1055