tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
ARM: tegra: Add OPP tables and power domains to Tegra20 device-trees
Add OPP tables and power domains to all peripheral devices which
support power management on Tegra20 SoC.
Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
authored by
Dmitry Osipenko
and committed by
Thierry Reding
83b7f0b8
3478494d
+1033
-5
+1
arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
+1
arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
+2
-1
arch/arm/boot/dts/tegra20-colibri.dtsi
+2
-1
arch/arm/boot/dts/tegra20-colibri.dtsi
···
497
497
regulator-always-on;
498
498
};
499
499
500
-
sm0 {
500
+
vdd_core: sm0 {
501
501
regulator-name = "VDD_CORE_1.2V";
502
502
regulator-min-microvolt = <1200000>;
503
503
regulator-max-microvolt = <1200000>;
···
603
603
nvidia,core-pwr-good-time = <3845 3845>;
604
604
nvidia,core-pwr-off-time = <3875>;
605
605
nvidia,sys-clock-req-active-high;
606
+
core-supply = <&vdd_core>;
606
607
607
608
/* Set SLEEP MODE bit in SUPPLYENE register of TPS658643 PMIC */
608
609
i2c-thermtrip {
+2
-1
arch/arm/boot/dts/tegra20-harmony.dts
+2
-1
arch/arm/boot/dts/tegra20-harmony.dts
···
339
339
regulator-always-on;
340
340
};
341
341
342
-
sm0 {
342
+
vdd_core: sm0 {
343
343
regulator-name = "vdd_sm0,vdd_core";
344
344
regulator-min-microvolt = <1200000>;
345
345
regulator-max-microvolt = <1200000>;
···
565
565
nvidia,core-pwr-good-time = <3845 3845>;
566
566
nvidia,core-pwr-off-time = <3875>;
567
567
nvidia,sys-clock-req-active-high;
568
+
core-supply = <&vdd_core>;
568
569
};
569
570
570
571
pcie@80003000 {
+1
arch/arm/boot/dts/tegra20-paz00.dts
+1
arch/arm/boot/dts/tegra20-paz00.dts
+912
arch/arm/boot/dts/tegra20-peripherals-opp.dtsi
+912
arch/arm/boot/dts/tegra20-peripherals-opp.dtsi
···
1
1
// SPDX-License-Identifier: GPL-2.0
2
2
3
3
/ {
4
+
core_opp_table: opp-table-core {
5
+
compatible = "operating-points-v2";
6
+
opp-shared;
7
+
8
+
core_opp_950: opp-950000 {
9
+
opp-microvolt = <950000 950000 1300000>;
10
+
opp-level = <950000>;
11
+
};
12
+
13
+
core_opp_1000: opp-1000000 {
14
+
opp-microvolt = <1000000 1000000 1300000>;
15
+
opp-level = <1000000>;
16
+
};
17
+
18
+
core_opp_1100: opp-1100000 {
19
+
opp-microvolt = <1100000 1100000 1300000>;
20
+
opp-level = <1100000>;
21
+
};
22
+
23
+
core_opp_1200: opp-1200000 {
24
+
opp-microvolt = <1200000 1200000 1300000>;
25
+
opp-level = <1200000>;
26
+
};
27
+
28
+
core_opp_1225: opp-1225000 {
29
+
opp-microvolt = <1225000 1225000 1300000>;
30
+
opp-level = <1225000>;
31
+
};
32
+
33
+
core_opp_1275: opp-1275000 {
34
+
opp-microvolt = <1275000 1275000 1300000>;
35
+
opp-level = <1275000>;
36
+
};
37
+
38
+
core_opp_1300: opp-1300000 {
39
+
opp-microvolt = <1300000 1300000 1300000>;
40
+
opp-level = <1300000>;
41
+
};
42
+
};
43
+
4
44
emc_icc_dvfs_opp_table: opp-table-emc {
5
45
compatible = "operating-points-v2";
6
46
···
48
8
opp-microvolt = <950000 950000 1300000>;
49
9
opp-hz = /bits/ 64 <36000000>;
50
10
opp-supported-hw = <0x000F>;
11
+
required-opps = <&core_opp_950>;
51
12
};
52
13
53
14
opp-47500000 {
54
15
opp-microvolt = <950000 950000 1300000>;
55
16
opp-hz = /bits/ 64 <47500000>;
56
17
opp-supported-hw = <0x000F>;
18
+
required-opps = <&core_opp_950>;
57
19
};
58
20
59
21
opp-50000000 {
60
22
opp-microvolt = <950000 950000 1300000>;
61
23
opp-hz = /bits/ 64 <50000000>;
62
24
opp-supported-hw = <0x000F>;
25
+
required-opps = <&core_opp_950>;
63
26
};
64
27
65
28
opp-54000000 {
66
29
opp-microvolt = <950000 950000 1300000>;
67
30
opp-hz = /bits/ 64 <54000000>;
68
31
opp-supported-hw = <0x000F>;
32
+
required-opps = <&core_opp_950>;
69
33
};
70
34
71
35
opp-57000000 {
72
36
opp-microvolt = <950000 950000 1300000>;
73
37
opp-hz = /bits/ 64 <57000000>;
74
38
opp-supported-hw = <0x000F>;
39
+
required-opps = <&core_opp_950>;
75
40
};
76
41
77
42
opp-100000000 {
78
43
opp-microvolt = <1000000 1000000 1300000>;
79
44
opp-hz = /bits/ 64 <100000000>;
80
45
opp-supported-hw = <0x000F>;
46
+
required-opps = <&core_opp_1000>;
81
47
};
82
48
83
49
opp-108000000 {
84
50
opp-microvolt = <1000000 1000000 1300000>;
85
51
opp-hz = /bits/ 64 <108000000>;
86
52
opp-supported-hw = <0x000F>;
53
+
required-opps = <&core_opp_1000>;
87
54
};
88
55
89
56
opp-126666000 {
90
57
opp-microvolt = <1000000 1000000 1300000>;
91
58
opp-hz = /bits/ 64 <126666000>;
92
59
opp-supported-hw = <0x000F>;
60
+
required-opps = <&core_opp_1000>;
93
61
};
94
62
95
63
opp-150000000 {
96
64
opp-microvolt = <1000000 1000000 1300000>;
97
65
opp-hz = /bits/ 64 <150000000>;
98
66
opp-supported-hw = <0x000F>;
67
+
required-opps = <&core_opp_1000>;
99
68
};
100
69
101
70
opp-190000000 {
102
71
opp-microvolt = <1000000 1000000 1300000>;
103
72
opp-hz = /bits/ 64 <190000000>;
104
73
opp-supported-hw = <0x000F>;
74
+
required-opps = <&core_opp_1000>;
105
75
};
106
76
107
77
opp-216000000 {
108
78
opp-microvolt = <1000000 1000000 1300000>;
109
79
opp-hz = /bits/ 64 <216000000>;
110
80
opp-supported-hw = <0x000F>;
81
+
required-opps = <&core_opp_1000>;
111
82
opp-suspend;
112
83
};
113
84
···
126
75
opp-microvolt = <1000000 1000000 1300000>;
127
76
opp-hz = /bits/ 64 <300000000>;
128
77
opp-supported-hw = <0x000F>;
78
+
required-opps = <&core_opp_1000>;
129
79
};
130
80
131
81
opp-333000000 {
132
82
opp-microvolt = <1000000 1000000 1300000>;
133
83
opp-hz = /bits/ 64 <333000000>;
134
84
opp-supported-hw = <0x000F>;
85
+
required-opps = <&core_opp_1000>;
135
86
};
136
87
137
88
opp-380000000 {
138
89
opp-microvolt = <1100000 1100000 1300000>;
139
90
opp-hz = /bits/ 64 <380000000>;
140
91
opp-supported-hw = <0x000F>;
92
+
required-opps = <&core_opp_1100>;
141
93
};
142
94
143
95
opp-600000000 {
144
96
opp-microvolt = <1200000 1200000 1300000>;
145
97
opp-hz = /bits/ 64 <600000000>;
146
98
opp-supported-hw = <0x000F>;
99
+
required-opps = <&core_opp_1200>;
147
100
};
148
101
149
102
opp-666000000 {
150
103
opp-microvolt = <1200000 1200000 1300000>;
151
104
opp-hz = /bits/ 64 <666000000>;
152
105
opp-supported-hw = <0x000F>;
106
+
required-opps = <&core_opp_1200>;
153
107
};
154
108
155
109
opp-760000000 {
156
110
opp-microvolt = <1300000 1300000 1300000>;
157
111
opp-hz = /bits/ 64 <760000000>;
158
112
opp-supported-hw = <0x000F>;
113
+
required-opps = <&core_opp_1300>;
114
+
};
115
+
};
116
+
117
+
host1x_dvfs_opp_table: opp-table-host1x {
118
+
compatible = "operating-points-v2";
119
+
120
+
opp-104500000-950 {
121
+
opp-microvolt = <950000 950000 1300000>;
122
+
opp-hz = /bits/ 64 <104500000>;
123
+
opp-supported-hw = <0x000F>;
124
+
required-opps = <&core_opp_950>;
125
+
};
126
+
127
+
opp-133000000-1000 {
128
+
opp-microvolt = <1000000 1000000 1300000>;
129
+
opp-hz = /bits/ 64 <133000000>;
130
+
opp-supported-hw = <0x000F>;
131
+
required-opps = <&core_opp_1000>;
132
+
};
133
+
134
+
opp-166000000-1100 {
135
+
opp-microvolt = <1100000 1100000 1300000>;
136
+
opp-hz = /bits/ 64 <166000000>;
137
+
opp-supported-hw = <0x000F>;
138
+
required-opps = <&core_opp_1100>;
139
+
};
140
+
};
141
+
142
+
mpe_dvfs_opp_table: opp-table-mpe {
143
+
compatible = "operating-points-v2";
144
+
145
+
opp-104500000-950 {
146
+
opp-microvolt = <950000 950000 1300000>;
147
+
opp-hz = /bits/ 64 <104500000>;
148
+
opp-supported-hw = <0x0001>;
149
+
required-opps = <&core_opp_950>;
150
+
};
151
+
152
+
opp-142500000-950 {
153
+
opp-microvolt = <950000 950000 1300000>;
154
+
opp-hz = /bits/ 64 <142500000>;
155
+
opp-supported-hw = <0x0002>;
156
+
required-opps = <&core_opp_950>;
157
+
};
158
+
159
+
opp-152000000-1000 {
160
+
opp-microvolt = <1000000 1000000 1300000>;
161
+
opp-hz = /bits/ 64 <152000000>;
162
+
opp-supported-hw = <0x0001>;
163
+
required-opps = <&core_opp_1000>;
164
+
};
165
+
166
+
opp-190000000-1000 {
167
+
opp-microvolt = <1000000 1000000 1300000>;
168
+
opp-hz = /bits/ 64 <190000000>;
169
+
opp-supported-hw = <0x0002>;
170
+
required-opps = <&core_opp_1000>;
171
+
};
172
+
173
+
opp-190000000-950 {
174
+
opp-microvolt = <950000 950000 1300000>;
175
+
opp-hz = /bits/ 64 <190000000>;
176
+
opp-supported-hw = <0x0004>;
177
+
required-opps = <&core_opp_950>;
178
+
};
179
+
180
+
opp-228000000-1100 {
181
+
opp-microvolt = <1100000 1100000 1300000>;
182
+
opp-hz = /bits/ 64 <228000000>;
183
+
opp-supported-hw = <0x0001>;
184
+
required-opps = <&core_opp_1100>;
185
+
};
186
+
187
+
opp-228000000-950 {
188
+
opp-microvolt = <950000 950000 1300000>;
189
+
opp-hz = /bits/ 64 <228000000>;
190
+
opp-supported-hw = <0x0008>;
191
+
required-opps = <&core_opp_950>;
192
+
};
193
+
194
+
opp-237500000-1000 {
195
+
opp-microvolt = <1000000 1000000 1300000>;
196
+
opp-hz = /bits/ 64 <237500000>;
197
+
opp-supported-hw = <0x0004>;
198
+
required-opps = <&core_opp_1000>;
199
+
};
200
+
201
+
opp-266000000-1000 {
202
+
opp-microvolt = <1000000 1000000 1300000>;
203
+
opp-hz = /bits/ 64 <266000000>;
204
+
opp-supported-hw = <0x0008>;
205
+
required-opps = <&core_opp_1000>;
206
+
};
207
+
208
+
opp-275500000-1100 {
209
+
opp-microvolt = <1100000 1100000 1300000>;
210
+
opp-hz = /bits/ 64 <275500000>;
211
+
opp-supported-hw = <0x0002>;
212
+
required-opps = <&core_opp_1100>;
213
+
};
214
+
215
+
opp-300000000-1200 {
216
+
opp-microvolt = <1200000 1200000 1300000>;
217
+
opp-hz = /bits/ 64 <300000000>;
218
+
opp-supported-hw = <0x0003>;
219
+
required-opps = <&core_opp_1200>;
220
+
};
221
+
222
+
opp-300000000-1100 {
223
+
opp-microvolt = <1100000 1100000 1300000>;
224
+
opp-hz = /bits/ 64 <300000000>;
225
+
opp-supported-hw = <0x000C>;
226
+
required-opps = <&core_opp_1100>;
227
+
};
228
+
};
229
+
230
+
vi_dvfs_opp_table: opp-table-vi {
231
+
compatible = "operating-points-v2";
232
+
233
+
opp-85000000-950 {
234
+
opp-microvolt = <950000 950000 1300000>;
235
+
opp-hz = /bits/ 64 <85000000>;
236
+
opp-supported-hw = <0x000F>;
237
+
required-opps = <&core_opp_950>;
238
+
};
239
+
240
+
opp-100000000-1000 {
241
+
opp-microvolt = <1000000 1000000 1300000>;
242
+
opp-hz = /bits/ 64 <100000000>;
243
+
opp-supported-hw = <0x000F>;
244
+
required-opps = <&core_opp_1000>;
245
+
};
246
+
247
+
opp-150000000-1100 {
248
+
opp-microvolt = <1100000 1100000 1300000>;
249
+
opp-hz = /bits/ 64 <150000000>;
250
+
opp-supported-hw = <0x000F>;
251
+
required-opps = <&core_opp_1100>;
252
+
};
253
+
};
254
+
255
+
epp_dvfs_opp_table: opp-table-epp {
256
+
compatible = "operating-points-v2";
257
+
258
+
opp-133000000-950 {
259
+
opp-microvolt = <950000 950000 1300000>;
260
+
opp-hz = /bits/ 64 <133000000>;
261
+
opp-supported-hw = <0x000F>;
262
+
required-opps = <&core_opp_950>;
263
+
};
264
+
265
+
opp-171000000-1000 {
266
+
opp-microvolt = <1000000 1000000 1300000>;
267
+
opp-hz = /bits/ 64 <171000000>;
268
+
opp-supported-hw = <0x000F>;
269
+
required-opps = <&core_opp_1000>;
270
+
};
271
+
272
+
opp-247000000-1100 {
273
+
opp-microvolt = <1100000 1100000 1300000>;
274
+
opp-hz = /bits/ 64 <247000000>;
275
+
opp-supported-hw = <0x000F>;
276
+
required-opps = <&core_opp_1100>;
277
+
};
278
+
279
+
opp-300000000-1200 {
280
+
opp-microvolt = <1200000 1200000 1300000>;
281
+
opp-hz = /bits/ 64 <300000000>;
282
+
opp-supported-hw = <0x000F>;
283
+
required-opps = <&core_opp_1200>;
284
+
};
285
+
};
286
+
287
+
gr2d_dvfs_opp_table: opp-table-gr2d {
288
+
compatible = "operating-points-v2";
289
+
290
+
opp-133000000-950 {
291
+
opp-microvolt = <950000 950000 1300000>;
292
+
opp-hz = /bits/ 64 <133000000>;
293
+
opp-supported-hw = <0x000F>;
294
+
required-opps = <&core_opp_950>;
295
+
};
296
+
297
+
opp-171000000-1000 {
298
+
opp-microvolt = <1000000 1000000 1300000>;
299
+
opp-hz = /bits/ 64 <171000000>;
300
+
opp-supported-hw = <0x000F>;
301
+
required-opps = <&core_opp_1000>;
302
+
};
303
+
304
+
opp-247000000-1100 {
305
+
opp-microvolt = <1100000 1100000 1300000>;
306
+
opp-hz = /bits/ 64 <247000000>;
307
+
opp-supported-hw = <0x000F>;
308
+
required-opps = <&core_opp_1100>;
309
+
};
310
+
311
+
opp-300000000-1200 {
312
+
opp-microvolt = <1200000 1200000 1300000>;
313
+
opp-hz = /bits/ 64 <300000000>;
314
+
opp-supported-hw = <0x000F>;
315
+
required-opps = <&core_opp_1200>;
316
+
};
317
+
};
318
+
319
+
gr3d_dvfs_opp_table: opp-table-gr3d {
320
+
compatible = "operating-points-v2";
321
+
322
+
opp-114000000-950 {
323
+
opp-microvolt = <950000 950000 1300000>;
324
+
opp-hz = /bits/ 64 <114000000>;
325
+
opp-supported-hw = <0x0001>;
326
+
required-opps = <&core_opp_950>;
327
+
};
328
+
329
+
opp-161500000-1000 {
330
+
opp-microvolt = <1000000 1000000 1300000>;
331
+
opp-hz = /bits/ 64 <161500000>;
332
+
opp-supported-hw = <0x0001>;
333
+
required-opps = <&core_opp_1000>;
334
+
};
335
+
336
+
opp-161500000-950 {
337
+
opp-microvolt = <950000 950000 1300000>;
338
+
opp-hz = /bits/ 64 <161500000>;
339
+
opp-supported-hw = <0x0002>;
340
+
required-opps = <&core_opp_950>;
341
+
};
342
+
343
+
opp-209000000-1000 {
344
+
opp-microvolt = <1000000 1000000 1300000>;
345
+
opp-hz = /bits/ 64 <209000000>;
346
+
opp-supported-hw = <0x0002>;
347
+
required-opps = <&core_opp_1000>;
348
+
};
349
+
350
+
opp-218500000-950 {
351
+
opp-microvolt = <950000 950000 1300000>;
352
+
opp-hz = /bits/ 64 <218500000>;
353
+
opp-supported-hw = <0x0004>;
354
+
required-opps = <&core_opp_950>;
355
+
};
356
+
357
+
opp-247000000-1100 {
358
+
opp-microvolt = <1100000 1100000 1300000>;
359
+
opp-hz = /bits/ 64 <247000000>;
360
+
opp-supported-hw = <0x0001>;
361
+
required-opps = <&core_opp_1100>;
362
+
};
363
+
364
+
opp-247000000-950 {
365
+
opp-microvolt = <950000 950000 1300000>;
366
+
opp-hz = /bits/ 64 <247000000>;
367
+
opp-supported-hw = <0x0008>;
368
+
required-opps = <&core_opp_950>;
369
+
};
370
+
371
+
opp-256500000-1000 {
372
+
opp-microvolt = <1000000 1000000 1300000>;
373
+
opp-hz = /bits/ 64 <256500000>;
374
+
opp-supported-hw = <0x0004>;
375
+
required-opps = <&core_opp_1000>;
376
+
};
377
+
378
+
opp-285000000-1100 {
379
+
opp-microvolt = <1100000 1100000 1300000>;
380
+
opp-hz = /bits/ 64 <285000000>;
381
+
opp-supported-hw = <0x0002>;
382
+
required-opps = <&core_opp_1100>;
383
+
};
384
+
385
+
opp-285000000-1000 {
386
+
opp-microvolt = <1000000 1000000 1300000>;
387
+
opp-hz = /bits/ 64 <285000000>;
388
+
opp-supported-hw = <0x0008>;
389
+
required-opps = <&core_opp_1000>;
390
+
};
391
+
392
+
opp-304000000-1200 {
393
+
opp-microvolt = <1200000 1200000 1300000>;
394
+
opp-hz = /bits/ 64 <304000000>;
395
+
opp-supported-hw = <0x0001>;
396
+
required-opps = <&core_opp_1200>;
397
+
};
398
+
399
+
opp-323000000-1100 {
400
+
opp-microvolt = <1100000 1100000 1300000>;
401
+
opp-hz = /bits/ 64 <323000000>;
402
+
opp-supported-hw = <0x0004>;
403
+
required-opps = <&core_opp_1100>;
404
+
};
405
+
406
+
opp-333500000-1275 {
407
+
opp-microvolt = <1275000 1275000 1300000>;
408
+
opp-hz = /bits/ 64 <333500000>;
409
+
opp-supported-hw = <0x0001>;
410
+
required-opps = <&core_opp_1275>;
411
+
};
412
+
413
+
opp-333500000-1200 {
414
+
opp-microvolt = <1200000 1200000 1300000>;
415
+
opp-hz = /bits/ 64 <333500000>;
416
+
opp-supported-hw = <0x0002>;
417
+
required-opps = <&core_opp_1200>;
418
+
};
419
+
420
+
opp-351500000-1100 {
421
+
opp-microvolt = <1100000 1100000 1300000>;
422
+
opp-hz = /bits/ 64 <351500000>;
423
+
opp-supported-hw = <0x0008>;
424
+
required-opps = <&core_opp_1100>;
425
+
};
426
+
427
+
opp-361000000-1275 {
428
+
opp-microvolt = <1275000 1275000 1300000>;
429
+
opp-hz = /bits/ 64 <361000000>;
430
+
opp-supported-hw = <0x0002>;
431
+
required-opps = <&core_opp_1275>;
432
+
};
433
+
434
+
opp-380000000-1200 {
435
+
opp-microvolt = <1200000 1200000 1300000>;
436
+
opp-hz = /bits/ 64 <380000000>;
437
+
opp-supported-hw = <0x0004>;
438
+
required-opps = <&core_opp_1200>;
439
+
};
440
+
441
+
opp-400000000-1275 {
442
+
opp-microvolt = <1275000 1275000 1300000>;
443
+
opp-hz = /bits/ 64 <400000000>;
444
+
opp-supported-hw = <0x0004>;
445
+
required-opps = <&core_opp_1275>;
446
+
};
447
+
448
+
opp-400000000-1200 {
449
+
opp-microvolt = <1200000 1200000 1300000>;
450
+
opp-hz = /bits/ 64 <400000000>;
451
+
opp-supported-hw = <0x0008>;
452
+
required-opps = <&core_opp_1200>;
453
+
};
454
+
};
455
+
456
+
disp1_dvfs_opp_table: opp-table-disp1 {
457
+
compatible = "operating-points-v2";
458
+
459
+
opp-158000000-950 {
460
+
opp-microvolt = <950000 950000 1300000>;
461
+
opp-hz = /bits/ 64 <158000000>;
462
+
opp-supported-hw = <0x000F>;
463
+
required-opps = <&core_opp_950>;
464
+
};
465
+
466
+
opp-190000000-1100 {
467
+
opp-microvolt = <1100000 1100000 1300000>;
468
+
opp-hz = /bits/ 64 <190000000>;
469
+
opp-supported-hw = <0x000F>;
470
+
required-opps = <&core_opp_1100>;
471
+
};
472
+
};
473
+
474
+
disp2_dvfs_opp_table: opp-table-disp2 {
475
+
compatible = "operating-points-v2";
476
+
477
+
opp-158000000-950 {
478
+
opp-microvolt = <950000 950000 1300000>;
479
+
opp-hz = /bits/ 64 <158000000>;
480
+
opp-supported-hw = <0x000F>;
481
+
required-opps = <&core_opp_950>;
482
+
};
483
+
484
+
opp-190000000-1100 {
485
+
opp-microvolt = <1100000 1100000 1300000>;
486
+
opp-hz = /bits/ 64 <190000000>;
487
+
opp-supported-hw = <0x000F>;
488
+
required-opps = <&core_opp_1100>;
489
+
};
490
+
};
491
+
492
+
dsi_dvfs_opp_table: opp-table-dsi {
493
+
compatible = "operating-points-v2";
494
+
495
+
opp-100000000-950 {
496
+
opp-microvolt = <950000 950000 1300000>;
497
+
opp-hz = /bits/ 64 <100000000>;
498
+
opp-supported-hw = <0x000F>;
499
+
required-opps = <&core_opp_950>;
500
+
};
501
+
502
+
opp-500000000-1200 {
503
+
opp-microvolt = <1200000 1200000 1300000>;
504
+
opp-hz = /bits/ 64 <500000000>;
505
+
opp-supported-hw = <0x000F>;
506
+
required-opps = <&core_opp_1200>;
507
+
};
508
+
};
509
+
510
+
hdmi_dvfs_opp_table: opp-table-hdmi {
511
+
compatible = "operating-points-v2";
512
+
513
+
opp-148500000-1200 {
514
+
opp-microvolt = <1200000 1200000 1300000>;
515
+
opp-hz = /bits/ 64 <148500000>;
516
+
opp-supported-hw = <0x000F>;
517
+
required-opps = <&core_opp_1200>;
518
+
};
519
+
};
520
+
521
+
tvo_dvfs_opp_table: opp-table-tvo {
522
+
compatible = "operating-points-v2";
523
+
524
+
opp-250000000-1200 {
525
+
opp-microvolt = <1200000 1200000 1300000>;
526
+
opp-hz = /bits/ 64 <250000000>;
527
+
opp-supported-hw = <0x000F>;
528
+
required-opps = <&core_opp_1200>;
529
+
};
530
+
};
531
+
532
+
sclk_dvfs_opp_table: opp-table-sclk {
533
+
compatible = "operating-points-v2";
534
+
535
+
opp-95000000-950 {
536
+
opp-microvolt = <950000 950000 1300000>;
537
+
opp-hz = /bits/ 64 <95000000>;
538
+
opp-supported-hw = <0x0001>;
539
+
required-opps = <&core_opp_950>;
540
+
};
541
+
542
+
opp-123500000-950 {
543
+
opp-microvolt = <950000 950000 1300000>;
544
+
opp-hz = /bits/ 64 <123500000>;
545
+
opp-supported-hw = <0x0002>;
546
+
required-opps = <&core_opp_950>;
547
+
};
548
+
549
+
opp-133000000-1000 {
550
+
opp-microvolt = <1000000 1000000 1300000>;
551
+
opp-hz = /bits/ 64 <133000000>;
552
+
opp-supported-hw = <0x0001>;
553
+
required-opps = <&core_opp_1000>;
554
+
};
555
+
556
+
opp-152000000-950 {
557
+
opp-microvolt = <950000 950000 1300000>;
558
+
opp-hz = /bits/ 64 <152000000>;
559
+
opp-supported-hw = <0x0004>;
560
+
required-opps = <&core_opp_950>;
561
+
};
562
+
563
+
opp-159500000-1000 {
564
+
opp-microvolt = <1000000 1000000 1300000>;
565
+
opp-hz = /bits/ 64 <159500000>;
566
+
opp-supported-hw = <0x0002>;
567
+
required-opps = <&core_opp_1000>;
568
+
};
569
+
570
+
opp-171000000-950 {
571
+
opp-microvolt = <950000 950000 1300000>;
572
+
opp-hz = /bits/ 64 <171000000>;
573
+
opp-supported-hw = <0x0008>;
574
+
required-opps = <&core_opp_950>;
575
+
};
576
+
577
+
opp-180500000-1000 {
578
+
opp-microvolt = <1000000 1000000 1300000>;
579
+
opp-hz = /bits/ 64 <180500000>;
580
+
opp-supported-hw = <0x0004>;
581
+
required-opps = <&core_opp_1000>;
582
+
};
583
+
584
+
opp-190000000-1100 {
585
+
opp-microvolt = <1100000 1100000 1300000>;
586
+
opp-hz = /bits/ 64 <190000000>;
587
+
opp-supported-hw = <0x0001>;
588
+
required-opps = <&core_opp_1100>;
589
+
};
590
+
591
+
opp-207000000-1100 {
592
+
opp-microvolt = <1100000 1100000 1300000>;
593
+
opp-hz = /bits/ 64 <207000000>;
594
+
opp-supported-hw = <0x0002>;
595
+
required-opps = <&core_opp_1100>;
596
+
};
597
+
598
+
opp-218500000-1000 {
599
+
opp-microvolt = <1000000 1000000 1300000>;
600
+
opp-hz = /bits/ 64 <218500000>;
601
+
opp-supported-hw = <0x0008>;
602
+
required-opps = <&core_opp_1000>;
603
+
};
604
+
605
+
opp-222500000-1200 {
606
+
opp-microvolt = <1200000 1200000 1300000>;
607
+
opp-hz = /bits/ 64 <222500000>;
608
+
opp-supported-hw = <0x0001>;
609
+
required-opps = <&core_opp_1200>;
610
+
};
611
+
612
+
opp-229500000-1100 {
613
+
opp-microvolt = <1100000 1100000 1300000>;
614
+
opp-hz = /bits/ 64 <229500000>;
615
+
opp-supported-hw = <0x0004>;
616
+
required-opps = <&core_opp_1100>;
617
+
};
618
+
619
+
opp-240000000-1225 {
620
+
opp-microvolt = <1225000 1225000 1300000>;
621
+
opp-hz = /bits/ 64 <240000000>;
622
+
opp-supported-hw = <0x0001>;
623
+
required-opps = <&core_opp_1225>;
624
+
};
625
+
626
+
opp-240000000-1200 {
627
+
opp-microvolt = <1200000 1200000 1300000>;
628
+
opp-hz = /bits/ 64 <240000000>;
629
+
opp-supported-hw = <0x0002>;
630
+
required-opps = <&core_opp_1200>;
631
+
};
632
+
633
+
opp-247000000-1275 {
634
+
opp-microvolt = <1275000 1275000 1300000>;
635
+
opp-hz = /bits/ 64 <247000000>;
636
+
opp-supported-hw = <0x0001>;
637
+
required-opps = <&core_opp_1275>;
638
+
};
639
+
640
+
opp-256500000-1100 {
641
+
opp-microvolt = <1100000 1100000 1300000>;
642
+
opp-hz = /bits/ 64 <256500000>;
643
+
opp-supported-hw = <0x0008>;
644
+
required-opps = <&core_opp_1100>;
645
+
};
646
+
647
+
opp-260000000-1200 {
648
+
opp-microvolt = <1200000 1200000 1300000>;
649
+
opp-hz = /bits/ 64 <260000000>;
650
+
opp-supported-hw = <0x0004>;
651
+
required-opps = <&core_opp_1200>;
652
+
};
653
+
654
+
opp-262000000-1300 {
655
+
opp-microvolt = <1300000 1300000 1300000>;
656
+
opp-hz = /bits/ 64 <262000000>;
657
+
opp-supported-hw = <0x0001>;
658
+
required-opps = <&core_opp_1300>;
659
+
};
660
+
661
+
opp-264000000-1275 {
662
+
opp-microvolt = <1275000 1275000 1300000>;
663
+
opp-hz = /bits/ 64 <264000000>;
664
+
opp-supported-hw = <0x0002>;
665
+
required-opps = <&core_opp_1275>;
666
+
};
667
+
668
+
opp-277500000-1300 {
669
+
opp-microvolt = <1300000 1300000 1300000>;
670
+
opp-hz = /bits/ 64 <277500000>;
671
+
opp-supported-hw = <0x0002>;
672
+
required-opps = <&core_opp_1300>;
673
+
};
674
+
675
+
opp-285000000-1275 {
676
+
opp-microvolt = <1275000 1275000 1300000>;
677
+
opp-hz = /bits/ 64 <285000000>;
678
+
opp-supported-hw = <0x0004>;
679
+
required-opps = <&core_opp_1275>;
680
+
};
681
+
682
+
opp-292500000-1200 {
683
+
opp-microvolt = <1200000 1200000 1300000>;
684
+
opp-hz = /bits/ 64 <292500000>;
685
+
opp-supported-hw = <0x0008>;
686
+
required-opps = <&core_opp_1200>;
687
+
};
688
+
689
+
opp-300000000-1300 {
690
+
opp-microvolt = <1300000 1300000 1300000>;
691
+
opp-hz = /bits/ 64 <300000000>;
692
+
opp-supported-hw = <0x0004>;
693
+
required-opps = <&core_opp_1300>;
694
+
};
695
+
696
+
opp-300000000-1275 {
697
+
opp-microvolt = <1275000 1275000 1300000>;
698
+
opp-hz = /bits/ 64 <300000000>;
699
+
opp-supported-hw = <0x0008>;
700
+
required-opps = <&core_opp_1275>;
701
+
};
702
+
};
703
+
704
+
vde_dvfs_opp_table: opp-table-vde {
705
+
compatible = "operating-points-v2";
706
+
707
+
opp-95000000-950 {
708
+
opp-microvolt = <950000 950000 1300000>;
709
+
opp-hz = /bits/ 64 <95000000>;
710
+
opp-supported-hw = <0x0001>;
711
+
required-opps = <&core_opp_950>;
712
+
};
713
+
714
+
opp-123500000-1000 {
715
+
opp-microvolt = <1000000 1000000 1300000>;
716
+
opp-hz = /bits/ 64 <123500000>;
717
+
opp-supported-hw = <0x0001>;
718
+
required-opps = <&core_opp_1000>;
719
+
};
720
+
721
+
opp-123500000-950 {
722
+
opp-microvolt = <950000 950000 1300000>;
723
+
opp-hz = /bits/ 64 <123500000>;
724
+
opp-supported-hw = <0x0002>;
725
+
required-opps = <&core_opp_950>;
726
+
};
727
+
728
+
opp-152000000-1000 {
729
+
opp-microvolt = <1000000 1000000 1300000>;
730
+
opp-hz = /bits/ 64 <152000000>;
731
+
opp-supported-hw = <0x0002>;
732
+
required-opps = <&core_opp_1000>;
733
+
};
734
+
735
+
opp-152000000-950 {
736
+
opp-microvolt = <950000 950000 1300000>;
737
+
opp-hz = /bits/ 64 <152000000>;
738
+
opp-supported-hw = <0x0004>;
739
+
required-opps = <&core_opp_950>;
740
+
};
741
+
742
+
opp-171000000-950 {
743
+
opp-microvolt = <950000 950000 1300000>;
744
+
opp-hz = /bits/ 64 <171000000>;
745
+
opp-supported-hw = <0x0008>;
746
+
required-opps = <&core_opp_950>;
747
+
};
748
+
749
+
opp-209000000-1100 {
750
+
opp-microvolt = <1100000 1100000 1300000>;
751
+
opp-hz = /bits/ 64 <209000000>;
752
+
opp-supported-hw = <0x0001>;
753
+
required-opps = <&core_opp_1100>;
754
+
};
755
+
756
+
opp-209000000-1000 {
757
+
opp-microvolt = <1000000 1000000 1300000>;
758
+
opp-hz = /bits/ 64 <209000000>;
759
+
opp-supported-hw = <0x0004>;
760
+
required-opps = <&core_opp_1000>;
761
+
};
762
+
763
+
opp-218500000-1000 {
764
+
opp-microvolt = <1000000 1000000 1300000>;
765
+
opp-hz = /bits/ 64 <218500000>;
766
+
opp-supported-hw = <0x0008>;
767
+
required-opps = <&core_opp_1000>;
768
+
};
769
+
770
+
opp-237500000-1100 {
771
+
opp-microvolt = <1100000 1100000 1300000>;
772
+
opp-hz = /bits/ 64 <237500000>;
773
+
opp-supported-hw = <0x0002>;
774
+
required-opps = <&core_opp_1100>;
775
+
};
776
+
777
+
opp-275500000-1200 {
778
+
opp-microvolt = <1200000 1200000 1300000>;
779
+
opp-hz = /bits/ 64 <275500000>;
780
+
opp-supported-hw = <0x0001>;
781
+
required-opps = <&core_opp_1200>;
782
+
};
783
+
784
+
opp-285000000-1100 {
785
+
opp-microvolt = <1100000 1100000 1300000>;
786
+
opp-hz = /bits/ 64 <285000000>;
787
+
opp-supported-hw = <0x0004>;
788
+
required-opps = <&core_opp_1100>;
789
+
};
790
+
791
+
opp-300000000-1275 {
792
+
opp-microvolt = <1275000 1275000 1300000>;
793
+
opp-hz = /bits/ 64 <300000000>;
794
+
opp-supported-hw = <0x0001>;
795
+
required-opps = <&core_opp_1275>;
796
+
};
797
+
798
+
opp-300000000-1200 {
799
+
opp-microvolt = <1200000 1200000 1300000>;
800
+
opp-hz = /bits/ 64 <300000000>;
801
+
opp-supported-hw = <0x0006>;
802
+
required-opps = <&core_opp_1200>;
803
+
};
804
+
805
+
opp-300000000-1100 {
806
+
opp-microvolt = <1100000 1100000 1300000>;
807
+
opp-hz = /bits/ 64 <300000000>;
808
+
opp-supported-hw = <0x0008>;
809
+
required-opps = <&core_opp_1100>;
810
+
};
811
+
};
812
+
813
+
ndflash_dvfs_opp_table: opp-table-ndflash {
814
+
compatible = "operating-points-v2";
815
+
816
+
opp-130000000-950 {
817
+
opp-microvolt = <950000 950000 1300000>;
818
+
opp-hz = /bits/ 64 <130000000>;
819
+
opp-supported-hw = <0x000F>;
820
+
required-opps = <&core_opp_950>;
821
+
};
822
+
823
+
opp-150000000-1000 {
824
+
opp-microvolt = <1000000 1000000 1300000>;
825
+
opp-hz = /bits/ 64 <150000000>;
826
+
opp-supported-hw = <0x000F>;
827
+
required-opps = <&core_opp_1000>;
828
+
};
829
+
830
+
opp-158000000-1100 {
831
+
opp-microvolt = <1100000 1100000 1300000>;
832
+
opp-hz = /bits/ 64 <158000000>;
833
+
opp-supported-hw = <0x000F>;
834
+
required-opps = <&core_opp_1100>;
835
+
};
836
+
837
+
opp-164000000-1200 {
838
+
opp-microvolt = <1200000 1200000 1300000>;
839
+
opp-hz = /bits/ 64 <164000000>;
840
+
opp-supported-hw = <0x000F>;
841
+
required-opps = <&core_opp_1200>;
842
+
};
843
+
};
844
+
845
+
nor_dvfs_opp_table: opp-table-nor {
846
+
compatible = "operating-points-v2";
847
+
848
+
opp-92000000-1000 {
849
+
opp-microvolt = <1000000 1000000 1300000>;
850
+
opp-hz = /bits/ 64 <92000000>;
851
+
opp-supported-hw = <0x000F>;
852
+
required-opps = <&core_opp_1000>;
853
+
};
854
+
};
855
+
856
+
sdmmc1_dvfs_opp_table: opp-table-sdmmc1 {
857
+
compatible = "operating-points-v2";
858
+
859
+
opp-44000000-950 {
860
+
opp-microvolt = <950000 950000 1300000>;
861
+
opp-hz = /bits/ 64 <44000000>;
862
+
opp-supported-hw = <0x000F>;
863
+
required-opps = <&core_opp_950>;
864
+
};
865
+
866
+
opp-52000000-1000 {
867
+
opp-microvolt = <1000000 1000000 1300000>;
868
+
opp-hz = /bits/ 64 <52000000>;
869
+
opp-supported-hw = <0x000F>;
870
+
required-opps = <&core_opp_1000>;
871
+
};
872
+
};
873
+
874
+
sdmmc2_dvfs_opp_table: opp-table-sdmmc2 {
875
+
compatible = "operating-points-v2";
876
+
877
+
opp-44000000-950 {
878
+
opp-microvolt = <950000 950000 1300000>;
879
+
opp-hz = /bits/ 64 <44000000>;
880
+
opp-supported-hw = <0x000F>;
881
+
required-opps = <&core_opp_950>;
882
+
};
883
+
884
+
opp-52000000-1000 {
885
+
opp-microvolt = <1000000 1000000 1300000>;
886
+
opp-hz = /bits/ 64 <52000000>;
887
+
opp-supported-hw = <0x000F>;
888
+
required-opps = <&core_opp_1000>;
889
+
};
890
+
};
891
+
892
+
sdmmc3_dvfs_opp_table: opp-table-sdmmc3 {
893
+
compatible = "operating-points-v2";
894
+
895
+
opp-44000000-950 {
896
+
opp-microvolt = <950000 950000 1300000>;
897
+
opp-hz = /bits/ 64 <44000000>;
898
+
opp-supported-hw = <0x000F>;
899
+
required-opps = <&core_opp_950>;
900
+
};
901
+
902
+
opp-52000000-1000 {
903
+
opp-microvolt = <1000000 1000000 1300000>;
904
+
opp-hz = /bits/ 64 <52000000>;
905
+
opp-supported-hw = <0x000F>;
906
+
required-opps = <&core_opp_1000>;
907
+
};
908
+
};
909
+
910
+
sdmmc4_dvfs_opp_table: opp-table-sdmmc4 {
911
+
compatible = "operating-points-v2";
912
+
913
+
opp-44000000-950 {
914
+
opp-microvolt = <950000 950000 1300000>;
915
+
opp-hz = /bits/ 64 <44000000>;
916
+
opp-supported-hw = <0x000F>;
917
+
required-opps = <&core_opp_950>;
918
+
};
919
+
920
+
opp-52000000-1000 {
921
+
opp-microvolt = <1000000 1000000 1300000>;
922
+
opp-hz = /bits/ 64 <52000000>;
923
+
opp-supported-hw = <0x000F>;
924
+
required-opps = <&core_opp_1000>;
925
+
};
926
+
};
927
+
928
+
pcie_dvfs_opp_table: opp-table-pcie {
929
+
compatible = "operating-points-v2";
930
+
931
+
opp-250000000-1200 {
932
+
opp-microvolt = <1200000 1200000 1300000>;
933
+
opp-hz = /bits/ 64 <250000000>;
934
+
opp-supported-hw = <0x000F>;
935
+
required-opps = <&core_opp_1200>;
936
+
};
937
+
};
938
+
939
+
usbd_dvfs_opp_table: opp-table-usbd {
940
+
compatible = "operating-points-v2";
941
+
942
+
opp-480000000-1100 {
943
+
opp-microvolt = <1100000 1100000 1300000>;
944
+
opp-hz = /bits/ 64 <480000000>;
945
+
opp-supported-hw = <0x000F>;
946
+
required-opps = <&core_opp_1100>;
947
+
};
948
+
};
949
+
950
+
usb2_dvfs_opp_table: opp-table-usb2 {
951
+
compatible = "operating-points-v2";
952
+
953
+
opp-480000000-1100 {
954
+
opp-microvolt = <1100000 1100000 1300000>;
955
+
opp-hz = /bits/ 64 <480000000>;
956
+
opp-supported-hw = <0x000F>;
957
+
required-opps = <&core_opp_1100>;
958
+
};
959
+
};
960
+
961
+
usb3_dvfs_opp_table: opp-table-usb3 {
962
+
compatible = "operating-points-v2";
963
+
964
+
opp-480000000-1100 {
965
+
opp-microvolt = <1100000 1100000 1300000>;
966
+
opp-hz = /bits/ 64 <480000000>;
967
+
opp-supported-hw = <0x000F>;
968
+
required-opps = <&core_opp_1100>;
159
969
};
160
970
};
161
971
};
+2
-1
arch/arm/boot/dts/tegra20-seaboard.dts
+2
-1
arch/arm/boot/dts/tegra20-seaboard.dts
···
444
444
regulator-always-on;
445
445
};
446
446
447
-
sm0 {
447
+
vdd_core: sm0 {
448
448
regulator-name = "vdd_sm0,vdd_core";
449
449
regulator-min-microvolt = <1300000>;
450
450
regulator-max-microvolt = <1300000>;
···
689
689
nvidia,core-pwr-good-time = <3845 3845>;
690
690
nvidia,core-pwr-off-time = <3875>;
691
691
nvidia,sys-clock-req-active-high;
692
+
core-supply = <&vdd_core>;
692
693
};
693
694
694
695
memory-controller@7000f400 {
+2
-1
arch/arm/boot/dts/tegra20-tamonten.dtsi
+2
-1
arch/arm/boot/dts/tegra20-tamonten.dtsi
···
357
357
regulator-always-on;
358
358
};
359
359
360
-
sm0 {
360
+
vdd_core: sm0 {
361
361
regulator-name = "vdd_sys_sm0,vdd_core";
362
362
regulator-min-microvolt = <1200000>;
363
363
regulator-max-microvolt = <1200000>;
···
477
477
nvidia,core-pwr-good-time = <3845 3845>;
478
478
nvidia,core-pwr-off-time = <3875>;
479
479
nvidia,sys-clock-req-active-high;
480
+
core-supply = <&vdd_core>;
480
481
};
481
482
482
483
pcie@80003000 {
+9
arch/arm/boot/dts/tegra20-trimslice.dts
+9
arch/arm/boot/dts/tegra20-trimslice.dts
···
322
322
nvidia,core-pwr-good-time = <3845 3845>;
323
323
nvidia,core-pwr-off-time = <3875>;
324
324
nvidia,sys-clock-req-active-high;
325
+
core-supply = <&vdd_core>;
325
326
};
326
327
327
328
pcie@80003000 {
···
441
440
regulator-name = "pci_vdd";
442
441
regulator-min-microvolt = <1050000>;
443
442
regulator-max-microvolt = <1050000>;
443
+
regulator-always-on;
444
+
};
445
+
446
+
vdd_core: regulator-core {
447
+
compatible = "regulator-fixed";
448
+
regulator-name = "vdd_core";
449
+
regulator-min-microvolt = <1300000>;
450
+
regulator-max-microvolt = <1300000>;
444
451
regulator-always-on;
445
452
};
446
453
+1
arch/arm/boot/dts/tegra20-ventana.dts
+1
arch/arm/boot/dts/tegra20-ventana.dts
+101
-1
arch/arm/boot/dts/tegra20.dtsi
+101
-1
arch/arm/boot/dts/tegra20.dtsi
···
42
42
clock-names = "host1x";
43
43
resets = <&tegra_car 28>;
44
44
reset-names = "host1x";
45
+
power-domains = <&pd_core>;
46
+
operating-points-v2 = <&host1x_dvfs_opp_table>;
45
47
46
48
#address-cells = <1>;
47
49
#size-cells = <1>;
···
57
55
clocks = <&tegra_car TEGRA20_CLK_MPE>;
58
56
resets = <&tegra_car 60>;
59
57
reset-names = "mpe";
58
+
power-domains = <&pd_mpe>;
59
+
operating-points-v2 = <&mpe_dvfs_opp_table>;
60
60
};
61
61
62
62
vi@54080000 {
···
68
64
clocks = <&tegra_car TEGRA20_CLK_VI>;
69
65
resets = <&tegra_car 20>;
70
66
reset-names = "vi";
67
+
power-domains = <&pd_venc>;
68
+
operating-points-v2 = <&vi_dvfs_opp_table>;
71
69
};
72
70
73
71
epp@540c0000 {
···
79
73
clocks = <&tegra_car TEGRA20_CLK_EPP>;
80
74
resets = <&tegra_car 19>;
81
75
reset-names = "epp";
76
+
power-domains = <&pd_core>;
77
+
operating-points-v2 = <&epp_dvfs_opp_table>;
82
78
};
83
79
84
80
isp@54100000 {
···
90
82
clocks = <&tegra_car TEGRA20_CLK_ISP>;
91
83
resets = <&tegra_car 23>;
92
84
reset-names = "isp";
85
+
power-domains = <&pd_venc>;
93
86
};
94
87
95
88
gr2d@54140000 {
···
100
91
clocks = <&tegra_car TEGRA20_CLK_GR2D>;
101
92
resets = <&tegra_car 21>;
102
93
reset-names = "2d";
94
+
power-domains = <&pd_core>;
95
+
operating-points-v2 = <&gr2d_dvfs_opp_table>;
103
96
};
104
97
105
98
gr3d@54180000 {
···
110
99
clocks = <&tegra_car TEGRA20_CLK_GR3D>;
111
100
resets = <&tegra_car 24>;
112
101
reset-names = "3d";
102
+
power-domains = <&pd_3d>;
103
+
operating-points-v2 = <&gr3d_dvfs_opp_table>;
113
104
};
114
105
115
106
dc@54200000 {
···
123
110
clock-names = "dc", "parent";
124
111
resets = <&tegra_car 27>;
125
112
reset-names = "dc";
113
+
power-domains = <&pd_core>;
114
+
operating-points-v2 = <&disp1_dvfs_opp_table>;
126
115
127
116
nvidia,head = <0>;
128
117
···
153
138
clock-names = "dc", "parent";
154
139
resets = <&tegra_car 26>;
155
140
reset-names = "dc";
141
+
power-domains = <&pd_core>;
142
+
operating-points-v2 = <&disp2_dvfs_opp_table>;
156
143
157
144
nvidia,head = <1>;
158
145
···
183
166
clock-names = "hdmi", "parent";
184
167
resets = <&tegra_car 51>;
185
168
reset-names = "hdmi";
169
+
power-domains = <&pd_core>;
170
+
operating-points-v2 = <&hdmi_dvfs_opp_table>;
186
171
status = "disabled";
187
172
};
188
173
···
193
174
reg = <0x542c0000 0x00040000>;
194
175
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
195
176
clocks = <&tegra_car TEGRA20_CLK_TVO>;
177
+
power-domains = <&pd_core>;
178
+
operating-points-v2 = <&tvo_dvfs_opp_table>;
196
179
status = "disabled";
197
180
};
198
181
···
206
185
clock-names = "dsi", "parent";
207
186
resets = <&tegra_car 48>;
208
187
reset-names = "dsi";
188
+
power-domains = <&pd_core>;
189
+
operating-points-v2 = <&dsi_dvfs_opp_table>;
209
190
status = "disabled";
210
191
};
211
192
};
···
265
242
reg = <0x60006000 0x1000>;
266
243
#clock-cells = <1>;
267
244
#reset-cells = <1>;
245
+
246
+
sclk {
247
+
compatible = "nvidia,tegra20-sclk";
248
+
clocks = <&tegra_car TEGRA20_CLK_SCLK>;
249
+
power-domains = <&pd_core>;
250
+
operating-points-v2 = <&sclk_dvfs_opp_table>;
251
+
};
268
252
};
269
253
270
254
flow-controller@60007000 {
···
349
319
clocks = <&tegra_car TEGRA20_CLK_VDE>;
350
320
reset-names = "vde", "mc";
351
321
resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>;
322
+
power-domains = <&pd_vde>;
323
+
operating-points-v2 = <&vde_dvfs_opp_table>;
352
324
};
353
325
354
326
apbmisc@70000800 {
···
492
460
reset-names = "nand";
493
461
assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
494
462
assigned-clock-rates = <150000000>;
463
+
power-domains = <&pd_core>;
464
+
operating-points-v2 = <&ndflash_dvfs_opp_table>;
495
465
status = "disabled";
496
466
};
497
467
···
507
473
clock-names = "gmi";
508
474
resets = <&tegra_car 42>;
509
475
reset-names = "gmi";
476
+
power-domains = <&pd_core>;
477
+
operating-points-v2 = <&nor_dvfs_opp_table>;
510
478
status = "disabled";
511
479
};
512
480
···
679
643
clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
680
644
clock-names = "pclk", "clk32k_in";
681
645
#clock-cells = <1>;
646
+
647
+
pd_core: core-domain {
648
+
#power-domain-cells = <0>;
649
+
operating-points-v2 = <&core_opp_table>;
650
+
};
651
+
652
+
powergates {
653
+
pd_3d: td {
654
+
clocks = <&tegra_car TEGRA20_CLK_GR3D>;
655
+
resets = <&mc TEGRA20_MC_RESET_3D>,
656
+
<&tegra_car TEGRA20_CLK_GR3D>;
657
+
power-domains = <&pd_core>;
658
+
#power-domain-cells = <0>;
659
+
};
660
+
661
+
pd_venc: venc {
662
+
clocks = <&tegra_car TEGRA20_CLK_ISP>,
663
+
<&tegra_car TEGRA20_CLK_VI>,
664
+
<&tegra_car TEGRA20_CLK_CSI>;
665
+
resets = <&mc TEGRA20_MC_RESET_ISP>,
666
+
<&mc TEGRA20_MC_RESET_VI>,
667
+
<&tegra_car TEGRA20_CLK_ISP>,
668
+
<&tegra_car 20 /* VI */>,
669
+
<&tegra_car TEGRA20_CLK_CSI>;
670
+
power-domains = <&pd_core>;
671
+
#power-domain-cells = <0>;
672
+
};
673
+
674
+
pd_vde: vdec {
675
+
clocks = <&tegra_car TEGRA20_CLK_VDE>;
676
+
resets = <&mc TEGRA20_MC_RESET_VDE>,
677
+
<&tegra_car TEGRA20_CLK_VDE>;
678
+
power-domains = <&pd_core>;
679
+
#power-domain-cells = <0>;
680
+
};
681
+
682
+
pd_mpe: mpe {
683
+
clocks = <&tegra_car TEGRA20_CLK_MPE>;
684
+
resets = <&mc TEGRA20_MC_RESET_MPEA>,
685
+
<&mc TEGRA20_MC_RESET_MPEB>,
686
+
<&mc TEGRA20_MC_RESET_MPEC>,
687
+
<&tegra_car TEGRA20_CLK_MPE>;
688
+
power-domains = <&pd_core>;
689
+
#power-domain-cells = <0>;
690
+
};
691
+
};
682
692
};
683
693
684
694
mc: memory-controller@7000f000 {
···
744
662
reg = <0x7000f400 0x400>;
745
663
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
746
664
clocks = <&tegra_car TEGRA20_CLK_EMC>;
665
+
power-domains = <&pd_core>;
747
666
#address-cells = <1>;
748
667
#size-cells = <0>;
749
668
#interconnect-cells = <0>;
750
669
751
-
operating-points-v2 = <&emc_icc_dvfs_opp_table>;
752
670
nvidia,memory-controller = <&mc>;
671
+
operating-points-v2 = <&emc_icc_dvfs_opp_table>;
753
672
};
754
673
755
674
fuse@7000f800 {
···
795
712
<&tegra_car 72>,
796
713
<&tegra_car 74>;
797
714
reset-names = "pex", "afi", "pcie_x";
715
+
power-domains = <&pd_core>;
716
+
operating-points-v2 = <&pcie_dvfs_opp_table>;
717
+
798
718
status = "disabled";
799
719
800
720
pci@1,0 {
···
839
753
reset-names = "usb";
840
754
nvidia,needs-double-reset;
841
755
nvidia,phy = <&phy1>;
756
+
power-domains = <&pd_core>;
757
+
operating-points-v2 = <&usbd_dvfs_opp_table>;
842
758
status = "disabled";
843
759
};
844
760
···
880
792
resets = <&tegra_car 58>;
881
793
reset-names = "usb";
882
794
nvidia,phy = <&phy2>;
795
+
power-domains = <&pd_core>;
796
+
operating-points-v2 = <&usb2_dvfs_opp_table>;
883
797
status = "disabled";
884
798
};
885
799
···
910
820
resets = <&tegra_car 59>;
911
821
reset-names = "usb";
912
822
nvidia,phy = <&phy3>;
823
+
power-domains = <&pd_core>;
824
+
operating-points-v2 = <&usb3_dvfs_opp_table>;
913
825
status = "disabled";
914
826
};
915
827
···
948
856
clock-names = "sdhci";
949
857
resets = <&tegra_car 14>;
950
858
reset-names = "sdhci";
859
+
power-domains = <&pd_core>;
860
+
operating-points-v2 = <&sdmmc1_dvfs_opp_table>;
951
861
status = "disabled";
952
862
};
953
863
···
961
867
clock-names = "sdhci";
962
868
resets = <&tegra_car 9>;
963
869
reset-names = "sdhci";
870
+
power-domains = <&pd_core>;
871
+
operating-points-v2 = <&sdmmc2_dvfs_opp_table>;
964
872
status = "disabled";
965
873
};
966
874
···
974
878
clock-names = "sdhci";
975
879
resets = <&tegra_car 69>;
976
880
reset-names = "sdhci";
881
+
power-domains = <&pd_core>;
882
+
operating-points-v2 = <&sdmmc3_dvfs_opp_table>;
977
883
status = "disabled";
978
884
};
979
885
···
987
889
clock-names = "sdhci";
988
890
resets = <&tegra_car 15>;
989
891
reset-names = "sdhci";
892
+
power-domains = <&pd_core>;
893
+
operating-points-v2 = <&sdmmc4_dvfs_opp_table>;
990
894
status = "disabled";
991
895
};
992
896