tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm

Pull ARM updates from Russell King:

- handle inexact watchpoint addresses (Douglas Anderson)

- decompressor serial debug cleanups (Linus Walleij)

- update L2 cache prefetch bits (Guillaume Tucker)

- add text offset and malloc size to the decompressor kexec data

* tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm:
ARM: add malloc size to decompressor kexec size structure
ARM: add TEXT_OFFSET to decompressor kexec image structure
ARM: 9007/1: l2c: fix prefetch bits init in L2X0_AUX_CTRL using DT values
ARM: 9010/1: uncompress: Print the location of appended DTB
ARM: 9009/1: uncompress: Enable debug in head.S
ARM: 9008/1: uncompress: Drop excess whitespace print
ARM: 9006/1: uncompress: Wait for ready and busy in debug prints
ARM: 9005/1: debug: Select flow control for all debug UARTs
ARM: 9004/1: debug: Split waituart to CTS and TXRDY
ARM: 9003/1: uncompress: Delete unused debug macros
ARM: 8997/2: hw_breakpoint: Handle inexact watchpoint addresses

Linus Torvalds 709ebe6d b32649b8

+263 -112
+11 -5
arch/arm/Kconfig.debug
··· 1546 1546 bool 1547 1547 depends on ARCH_SIRF 1548 1548 1549 + config DEBUG_UART_FLOW_CONTROL 1550 + bool "Enable flow control (CTS) for the debug UART" 1551 + depends on DEBUG_LL 1552 + default y if ARCH_EBSA110 || DEBUG_FOOTBRIDGE_COM1 || DEBUG_GEMINI || ARCH_RPC 1553 + help 1554 + Some UART ports are connected to terminals that will use modem 1555 + control signals to indicate whether they are ready to receive text. 1556 + In practice this means that the terminal is asserting the special 1557 + control signal CTS (Clear To Send). If your debug UART supports 1558 + this and your debug terminal will require it, enable this option. 1559 + 1549 1560 config DEBUG_LL_INCLUDE 1550 1561 string 1551 1562 default "debug/sa1100.S" if DEBUG_SA1100 ··· 1903 1892 Palmchip provides a UART implementation compatible with 16550 1904 1893 except for having a different register layout. Say Y here if 1905 1894 the debug UART is of this type. 1906 - 1907 - config DEBUG_UART_8250_FLOW_CONTROL 1908 - bool "Enable flow control for 8250 UART" 1909 - depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250 1910 - default y if ARCH_EBSA110 || DEBUG_FOOTBRIDGE_COM1 || DEBUG_GEMINI || ARCH_RPC 1911 1895 1912 1896 config DEBUG_UNCOMPRESS 1913 1897 bool "Enable decompressor debugging via DEBUG_LL output"
+3
arch/arm/Makefile
··· 143 143 144 144 # Text offset. This list is sorted numerically by address in order to 145 145 # provide a means to avoid/resolve conflicts in multi-arch kernels. 146 + # Note: the 32kB below this value is reserved for use by the kernel 147 + # during boot, and this offset is critical to the functioning of 148 + # kexec-tools. 146 149 textofs-y := 0x00008000 147 150 # We don't want the htc bootloader to corrupt kernel during resume 148 151 textofs-$(CONFIG_PM_H1940) := 0x00108000
+6 -1
arch/arm/boot/compressed/Makefile
··· 7 7 8 8 OBJS = 9 9 10 - AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET) 11 10 HEAD = head.o 12 11 OBJS += misc.o decompress.o 13 12 ifeq ($(CONFIG_DEBUG_UNCOMPRESS),y) 14 13 OBJS += debug.o 14 + AFLAGS_head.o += -DDEBUG 15 15 endif 16 16 FONTC = $(srctree)/lib/fonts/font_acorn_8x8.c 17 17 ··· 68 68 ZBSSADDR := ALIGN(8) 69 69 endif 70 70 71 + MALLOC_SIZE := 65536 72 + 73 + AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET) -DMALLOC_SIZE=$(MALLOC_SIZE) 71 74 CPPFLAGS_vmlinux.lds := -DTEXT_START="$(ZTEXTADDR)" -DBSS_START="$(ZBSSADDR)" 75 + CPPFLAGS_vmlinux.lds += -DTEXT_OFFSET="$(TEXT_OFFSET)" 76 + CPPFLAGS_vmlinux.lds += -DMALLOC_SIZE="$(MALLOC_SIZE)" 72 77 73 78 compress-$(CONFIG_KERNEL_GZIP) = gzip 74 79 compress-$(CONFIG_KERNEL_LZO) = lzo
+4 -1
arch/arm/boot/compressed/debug.S
··· 8 8 9 9 ENTRY(putc) 10 10 addruart r1, r2, r3 11 - waituart r3, r1 11 + #ifdef CONFIG_DEBUG_UART_FLOW_CONTROL 12 + waituartcts r3, r1 13 + #endif 14 + waituarttxrdy r3, r1 12 15 senduart r0, r1 13 16 busyuart r3, r1 14 17 mov pc, lr
+35 -39
arch/arm/boot/compressed/head.S
··· 28 28 #if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7) 29 29 .macro loadsp, rb, tmp1, tmp2 30 30 .endm 31 - .macro writeb, ch, rb 31 + .macro writeb, ch, rb, tmp 32 32 mcr p14, 0, \ch, c0, c5, 0 33 33 .endm 34 34 #elif defined(CONFIG_CPU_XSCALE) 35 35 .macro loadsp, rb, tmp1, tmp2 36 36 .endm 37 - .macro writeb, ch, rb 37 + .macro writeb, ch, rb, tmp 38 38 mcr p14, 0, \ch, c8, c0, 0 39 39 .endm 40 40 #else 41 41 .macro loadsp, rb, tmp1, tmp2 42 42 .endm 43 - .macro writeb, ch, rb 43 + .macro writeb, ch, rb, tmp 44 44 mcr p14, 0, \ch, c1, c0, 0 45 45 .endm 46 46 #endif ··· 49 49 50 50 #include CONFIG_DEBUG_LL_INCLUDE 51 51 52 - .macro writeb, ch, rb 52 + .macro writeb, ch, rb, tmp 53 + #ifdef CONFIG_DEBUG_UART_FLOW_CONTROL 54 + waituartcts \tmp, \rb 55 + #endif 56 + waituarttxrdy \tmp, \rb 53 57 senduart \ch, \rb 58 + busyuart \tmp, \rb 54 59 .endm 55 60 56 61 #if defined(CONFIG_ARCH_SA1100) ··· 86 81 bl phex 87 82 .endm 88 83 89 - .macro debug_reloc_start 90 - #ifdef DEBUG 91 - kputc #'\n' 92 - kphex r6, 8 /* processor id */ 93 - kputc #':' 94 - kphex r7, 8 /* architecture id */ 95 - #ifdef CONFIG_CPU_CP15 96 - kputc #':' 97 - mrc p15, 0, r0, c1, c0 98 - kphex r0, 8 /* control reg */ 99 - #endif 100 - kputc #'\n' 101 - kphex r5, 8 /* decompressed kernel start */ 102 - kputc #'-' 103 - kphex r9, 8 /* decompressed kernel end */ 104 - kputc #'>' 105 - kphex r4, 8 /* kernel execution address */ 106 - kputc #'\n' 107 - #endif 108 - .endm 109 - 110 - .macro debug_reloc_end 111 - #ifdef DEBUG 112 - kphex r5, 8 /* end of kernel */ 113 - kputc #'\n' 114 - mov r0, r4 115 - bl memdump /* dump 256 bytes at start of kernel */ 116 - #endif 117 - .endm 118 - 119 84 /* 120 85 * Debug kernel copy by printing the memory addresses involved 121 86 */ 122 87 .macro dbgkc, begin, end, cbegin, cend 123 88 #ifdef DEBUG 124 - kputc #'\n' 125 89 kputc #'C' 126 90 kputc #':' 127 91 kputc #'0' ··· 110 136 kputc #'x' 111 137 kphex \cend, 8 /* End of kernel copy */ 112 138 kputc #'\n' 113 - kputc #'\r' 139 + #endif 140 + .endm 141 + 142 + /* 143 + * Debug print of the final appended DTB location 144 + */ 145 + .macro dbgadtb, begin, end 146 + #ifdef DEBUG 147 + kputc #'D' 148 + kputc #'T' 149 + kputc #'B' 150 + kputc #':' 151 + kputc #'0' 152 + kputc #'x' 153 + kphex \begin, 8 /* Start of appended DTB */ 154 + kputc #' ' 155 + kputc #'(' 156 + kputc #'0' 157 + kputc #'x' 158 + kphex \end, 8 /* End of appended DTB */ 159 + kputc #')' 160 + kputc #'\n' 114 161 #endif 115 162 .endm 116 163 ··· 298 303 299 304 #ifndef CONFIG_ZBOOT_ROM 300 305 /* malloc space is above the relocated stack (64k max) */ 301 - add r10, sp, #0x10000 306 + add r10, sp, #MALLOC_SIZE 302 307 #else 303 308 /* 304 309 * With ZBOOT_ROM the bss/stack is non relocatable, ··· 352 357 mov r5, r5, ror #8 353 358 eor r5, r5, r1, lsr #8 354 359 #endif 360 + dbgadtb r6, r5 355 361 /* 50% DTB growth should be good enough */ 356 362 add r5, r5, r5, lsr #1 357 363 /* preserve 64-bit alignment */ ··· 610 614 */ 611 615 mov r0, r4 612 616 mov r1, sp @ malloc space above stack 613 - add r2, sp, #0x10000 @ 64k max 617 + add r2, sp, #MALLOC_SIZE @ 64k max 614 618 mov r3, r7 615 619 bl decompress_kernel 616 620 ··· 1352 1356 1: ldrb r2, [r0], #1 1353 1357 teq r2, #0 1354 1358 moveq pc, lr 1355 - 2: writeb r2, r3 1359 + 2: writeb r2, r3, r1 1356 1360 mov r1, #0x00020000 1357 1361 3: subs r1, r1, #1 1358 1362 bne 3b
+3 -1
arch/arm/boot/compressed/vmlinux.lds.S
··· 44 44 } 45 45 .table : ALIGN(4) { 46 46 _table_start = .; 47 - LONG(ZIMAGE_MAGIC(4)) 47 + LONG(ZIMAGE_MAGIC(6)) 48 48 LONG(ZIMAGE_MAGIC(0x5a534c4b)) 49 49 LONG(ZIMAGE_MAGIC(__piggy_size_addr - _start)) 50 50 LONG(ZIMAGE_MAGIC(_kernel_bss_size)) 51 + LONG(ZIMAGE_MAGIC(TEXT_OFFSET)) 52 + LONG(ZIMAGE_MAGIC(MALLOC_SIZE)) 51 53 LONG(0) 52 54 _table_end = .; 53 55 }
+4 -3
arch/arm/include/debug/8250.S
··· 45 45 bne 1002b 46 46 .endm 47 47 48 - .macro waituart,rd,rx 49 - #ifdef CONFIG_DEBUG_UART_8250_FLOW_CONTROL 48 + .macro waituarttxrdy,rd,rx 49 + .endm 50 + 51 + .macro waituartcts,rd,rx 50 52 1001: load \rd, [\rx, #UART_MSR << UART_SHIFT] 51 53 tst \rd, #UART_MSR_CTS 52 54 beq 1001b 53 - #endif 54 55 .endm
+4 -1
arch/arm/include/debug/asm9260.S
··· 11 11 ldr \rv, = CONFIG_DEBUG_UART_VIRT 12 12 .endm 13 13 14 - .macro waituart,rd,rx 14 + .macro waituarttxrdy,rd,rx 15 + .endm 16 + 17 + .macro waituartcts,rd,rx 15 18 .endm 16 19 17 20 .macro senduart,rd,rx
+4 -1
arch/arm/include/debug/at91.S
··· 19 19 strb \rd, [\rx, #(AT91_DBGU_THR)] @ Write to Transmitter Holding Register 20 20 .endm 21 21 22 - .macro waituart,rd,rx 22 + .macro waituarttxrdy,rd,rx 23 23 1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register 24 24 tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit 25 25 beq 1001b 26 + .endm 27 + 28 + .macro waituartcts,rd,rx 26 29 .endm 27 30 28 31 .macro busyuart,rd,rx
+4 -1
arch/arm/include/debug/bcm63xx.S
··· 17 17 strb \rd, [\rx, #UART_FIFO_REG] 18 18 .endm 19 19 20 - .macro waituart, rd, rx 20 + .macro waituarttxrdy, rd, rx 21 21 1001: ldr \rd, [\rx, #UART_IR_REG] 22 22 tst \rd, #(1 << UART_IR_TXEMPTY) 23 23 beq 1001b 24 + .endm 25 + 26 + .macro waituartcts, rd, rx 24 27 .endm 25 28 26 29 .macro busyuart, rd, rx
+4 -1
arch/arm/include/debug/brcmstb.S
··· 142 142 bne 1002b 143 143 .endm 144 144 145 - .macro waituart,rd,rx 145 + .macro waituarttxrdy,rd,rx 146 + .endm 147 + 148 + .macro waituartcts,rd,rx 146 149 .endm 147 150 148 151 /*
+4 -1
arch/arm/include/debug/clps711x.S
··· 20 20 ldr \rp, =CLPS711X_UART_PADDR 21 21 .endm 22 22 23 - .macro waituart,rd,rx 23 + .macro waituartcts,rd,rx 24 + .endm 25 + 26 + .macro waituarttxrdy,rd,rx 24 27 .endm 25 28 26 29 .macro senduart,rd,rx
+4 -1
arch/arm/include/debug/dc21285.S
··· 34 34 bne 1001b 35 35 .endm 36 36 37 - .macro waituart,rd,rx 37 + .macro waituartcts,rd,rx 38 + .endm 39 + 40 + .macro waituarttxrdy,rd,rx 38 41 .endm
+4 -1
arch/arm/include/debug/digicolor.S
··· 21 21 strb \rd, [\rx, #UA0_EMI_REC] 22 22 .endm 23 23 24 - .macro waituart,rd,rx 24 + .macro waituartcts,rd,rx 25 + .endm 26 + 27 + .macro waituarttxrdy,rd,rx 25 28 .endm 26 29 27 30 .macro busyuart,rd,rx
+4 -1
arch/arm/include/debug/efm32.S
··· 29 29 strb \rd, [\rx, #UARTn_TXDATA] 30 30 .endm 31 31 32 - .macro waituart,rd,rx 32 + .macro waituartcts,rd,rx 33 + .endm 34 + 35 + .macro waituarttxrdy,rd,rx 33 36 1001: ldr \rd, [\rx, #UARTn_STATUS] 34 37 tst \rd, #UARTn_STATUS_TXBL 35 38 beq 1001b
+12 -3
arch/arm/include/debug/icedcc.S
··· 23 23 beq 1001b 24 24 .endm 25 25 26 - .macro waituart, rd, rx 26 + .macro waituartcts, rd, rx 27 + .endm 28 + 29 + .macro waituarttxrdy, rd, rx 27 30 mov \rd, #0x2000000 28 31 1001: 29 32 subs \rd, \rd, #1 ··· 50 47 beq 1001b 51 48 .endm 52 49 53 - .macro waituart, rd, rx 50 + .macro waituartcts, rd, rx 51 + .endm 52 + 53 + .macro waituarttxrdy, rd, rx 54 54 mov \rd, #0x10000000 55 55 1001: 56 56 subs \rd, \rd, #1 ··· 78 72 79 73 .endm 80 74 81 - .macro waituart, rd, rx 75 + .macro waituartcts, rd, rx 76 + .endm 77 + 78 + .macro waituarttxrdy, rd, rx 82 79 mov \rd, #0x2000000 83 80 1001: 84 81 subs \rd, \rd, #1
+4 -1
arch/arm/include/debug/imx.S
··· 35 35 str \rd, [\rx, #0x40] @ TXDATA 36 36 .endm 37 37 38 - .macro waituart,rd,rx 38 + .macro waituartcts,rd,rx 39 + .endm 40 + 41 + .macro waituarttxrdy,rd,rx 39 42 .endm 40 43 41 44 .macro busyuart,rd,rx
+4 -1
arch/arm/include/debug/meson.S
··· 25 25 beq 1002b 26 26 .endm 27 27 28 - .macro waituart,rd,rx 28 + .macro waituartcts,rd,rx 29 + .endm 30 + 31 + .macro waituarttxrdy,rd,rx 29 32 1001: ldr \rd, [\rx, #MESON_AO_UART_STATUS] 30 33 tst \rd, #MESON_AO_UART_TX_FIFO_FULL 31 34 bne 1001b
+4 -1
arch/arm/include/debug/msm.S
··· 17 17 str \rd, [\rx, #0x70] 18 18 .endm 19 19 20 - .macro waituart, rd, rx 20 + .macro waituartcts,rd,rx 21 + .endm 22 + 23 + .macro waituarttxrdy, rd, rx 21 24 @ check for TX_EMT in UARTDM_SR 22 25 ldr \rd, [\rx, #0x08] 23 26 ARM_BE8(rev \rd, \rd )
+4 -1
arch/arm/include/debug/omap2plus.S
··· 75 75 bne 1001b 76 76 .endm 77 77 78 - .macro waituart,rd,rx 78 + .macro waituartcts,rd,rx 79 + .endm 80 + 81 + .macro waituarttxrdy,rd,rx 79 82 .endm
+4 -1
arch/arm/include/debug/pl01x.S
··· 26 26 strb \rd, [\rx, #UART01x_DR] 27 27 .endm 28 28 29 - .macro waituart,rd,rx 29 + .macro waituartcts,rd,rx 30 + .endm 31 + 32 + .macro waituarttxrdy,rd,rx 30 33 1001: ldr \rd, [\rx, #UART01x_FR] 31 34 ARM_BE8( rev \rd, \rd ) 32 35 tst \rd, #UART01x_FR_TXFF
+4 -1
arch/arm/include/debug/renesas-scif.S
··· 33 33 ldr \rv, =SCIF_VIRT 34 34 .endm 35 35 36 - .macro waituart, rd, rx 36 + .macro waituartcts,rd,rx 37 + .endm 38 + 39 + .macro waituarttxrdy, rd, rx 37 40 1001: ldrh \rd, [\rx, #FSR] 38 41 tst \rd, #TDFE 39 42 beq 1001b
+4 -1
arch/arm/include/debug/sa1100.S
··· 51 51 str \rd, [\rx, #UTDR] 52 52 .endm 53 53 54 - .macro waituart,rd,rx 54 + .macro waituartcts,rd,rx 55 + .endm 56 + 57 + .macro waituarttxrdy,rd,rx 55 58 1001: ldr \rd, [\rx, #UTSR1] 56 59 tst \rd, #UTSR1_TNF 57 60 beq 1001b
+4 -1
arch/arm/include/debug/samsung.S
··· 69 69 1002: @ exit busyuart 70 70 .endm 71 71 72 - .macro waituart,rd,rx 72 + .macro waituartcts,rd,rx 73 + .endm 74 + 75 + .macro waituarttxrdy,rd,rx 73 76 ldr \rd, [\rx, # S3C2410_UFCON] 74 77 ARM_BE8(rev \rd, \rd) 75 78 tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
+4 -1
arch/arm/include/debug/sirf.S
··· 29 29 .macro busyuart,rd,rx 30 30 .endm 31 31 32 - .macro waituart,rd,rx 32 + .macro waituartcts,rd,rx 33 + .endm 34 + 35 + .macro waituarttxrdy,rd,rx 33 36 1001: ldr \rd, [\rx, #SIRF_LLUART_TXFIFO_STATUS] 34 37 tst \rd, #SIRF_LLUART_TXFIFO_EMPTY 35 38 beq 1001b
+4 -1
arch/arm/include/debug/sti.S
··· 45 45 strb \rd, [\rx, #ASC_TX_BUF_OFF] 46 46 .endm 47 47 48 - .macro waituart,rd,rx 48 + .macro waituartcts,rd,rx 49 + .endm 50 + 51 + .macro waituarttxrdy,rd,rx 49 52 1001: ldr \rd, [\rx, #ASC_STA_OFF] 50 53 tst \rd, #ASC_STA_TX_FULL 51 54 bne 1001b
+4 -1
arch/arm/include/debug/stm32.S
··· 27 27 strb \rd, [\rx, #STM32_USART_TDR_OFF] 28 28 .endm 29 29 30 - .macro waituart,rd,rx 30 + .macro waituartcts,rd,rx 31 + .endm 32 + 33 + .macro waituarttxrdy,rd,rx 31 34 1001: ldr \rd, [\rx, #(STM32_USART_SR_OFF)] @ Read Status Register 32 35 tst \rd, #STM32_USART_TXE @ TXE = 1 = tx empty 33 36 beq 1001b
+4 -3
arch/arm/include/debug/tegra.S
··· 178 178 1002: 179 179 .endm 180 180 181 - .macro waituart, rd, rx 182 - #ifdef FLOW_CONTROL 181 + .macro waituartcts, rd, rx 183 182 cmp \rx, #0 184 183 beq 1002f 185 184 1001: ldrb \rd, [\rx, #UART_MSR << UART_SHIFT] 186 185 tst \rd, #UART_MSR_CTS 187 186 beq 1001b 188 187 1002: 189 - #endif 188 + .endm 189 + 190 + .macro waituarttxrdy,rd,rx 190 191 .endm 191 192 192 193 /*
+4 -1
arch/arm/include/debug/vf.S
··· 29 29 beq 1001b @ wait until transmit done 30 30 .endm 31 31 32 - .macro waituart,rd,rx 32 + .macro waituartcts,rd,rx 33 + .endm 34 + 35 + .macro waituarttxrdy,rd,rx 33 36 .endm
+4 -1
arch/arm/include/debug/vt8500.S
··· 28 28 bne 1001b 29 29 .endm 30 30 31 - .macro waituart,rd,rx 31 + .macro waituartcts,rd,rx 32 + .endm 33 + 34 + .macro waituarttxrdy,rd,rx 32 35 .endm 33 36 34 37 #endif
+4 -1
arch/arm/include/debug/zynq.S
··· 33 33 strb \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA 34 34 .endm 35 35 36 - .macro waituart,rd,rx 36 + .macro waituartcts,rd,rx 37 + .endm 38 + 39 + .macro waituarttxrdy,rd,rx 37 40 1001: ldr \rd, [\rx, #UART_SR_OFFSET] 38 41 ARM_BE8( rev \rd, \rd ) 39 42 tst \rd, #UART_SR_TXEMPTY
+9 -2
arch/arm/kernel/debug.S
··· 89 89 2: teq r1, #'\n' 90 90 bne 3f 91 91 mov r1, #'\r' 92 - waituart r2, r3 92 + #ifdef CONFIG_DEBUG_UART_FLOW_CONTROL 93 + waituartcts r2, r3 94 + #endif 95 + waituarttxrdy r2, r3 93 96 senduart r1, r3 94 97 busyuart r2, r3 95 98 mov r1, #'\n' 96 - 3: waituart r2, r3 99 + 3: 100 + #ifdef CONFIG_DEBUG_UART_FLOW_CONTROL 101 + waituartcts r2, r3 102 + #endif 103 + waituarttxrdy r2, r3 97 104 senduart r1, r3 98 105 busyuart r2, r3 99 106 b 1b
+72 -28
arch/arm/kernel/hw_breakpoint.c
··· 683 683 arch_install_hw_breakpoint(bp); 684 684 } 685 685 686 + /* 687 + * Arm32 hardware does not always report a watchpoint hit address that matches 688 + * one of the watchpoints set. It can also report an address "near" the 689 + * watchpoint if a single instruction access both watched and unwatched 690 + * addresses. There is no straight-forward way, short of disassembling the 691 + * offending instruction, to map that address back to the watchpoint. This 692 + * function computes the distance of the memory access from the watchpoint as a 693 + * heuristic for the likelyhood that a given access triggered the watchpoint. 694 + * 695 + * See this same function in the arm64 platform code, which has the same 696 + * problem. 697 + * 698 + * The function returns the distance of the address from the bytes watched by 699 + * the watchpoint. In case of an exact match, it returns 0. 700 + */ 701 + static u32 get_distance_from_watchpoint(unsigned long addr, u32 val, 702 + struct arch_hw_breakpoint_ctrl *ctrl) 703 + { 704 + u32 wp_low, wp_high; 705 + u32 lens, lene; 706 + 707 + lens = __ffs(ctrl->len); 708 + lene = __fls(ctrl->len); 709 + 710 + wp_low = val + lens; 711 + wp_high = val + lene; 712 + if (addr < wp_low) 713 + return wp_low - addr; 714 + else if (addr > wp_high) 715 + return addr - wp_high; 716 + else 717 + return 0; 718 + } 719 + 686 720 static int watchpoint_fault_on_uaccess(struct pt_regs *regs, 687 721 struct arch_hw_breakpoint *info) 688 722 { ··· 726 692 static void watchpoint_handler(unsigned long addr, unsigned int fsr, 727 693 struct pt_regs *regs) 728 694 { 729 - int i, access; 730 - u32 val, ctrl_reg, alignment_mask; 695 + int i, access, closest_match = 0; 696 + u32 min_dist = -1, dist; 697 + u32 val, ctrl_reg; 731 698 struct perf_event *wp, **slots; 732 699 struct arch_hw_breakpoint *info; 733 700 struct arch_hw_breakpoint_ctrl ctrl; 734 701 735 702 slots = this_cpu_ptr(wp_on_reg); 736 703 704 + /* 705 + * Find all watchpoints that match the reported address. If no exact 706 + * match is found. Attribute the hit to the closest watchpoint. 707 + */ 708 + rcu_read_lock(); 737 709 for (i = 0; i < core_num_wrps; ++i) { 738 - rcu_read_lock(); 739 - 740 710 wp = slots[i]; 741 - 742 711 if (wp == NULL) 743 - goto unlock; 712 + continue; 744 713 745 - info = counter_arch_bp(wp); 746 714 /* 747 715 * The DFAR is an unknown value on debug architectures prior 748 716 * to 7.1. Since we only allow a single watchpoint on these ··· 753 717 */ 754 718 if (debug_arch < ARM_DEBUG_ARCH_V7_1) { 755 719 BUG_ON(i > 0); 720 + info = counter_arch_bp(wp); 756 721 info->trigger = wp->attr.bp_addr; 757 722 } else { 758 - if (info->ctrl.len == ARM_BREAKPOINT_LEN_8) 759 - alignment_mask = 0x7; 760 - else 761 - alignment_mask = 0x3; 762 - 763 - /* Check if the watchpoint value matches. */ 764 - val = read_wb_reg(ARM_BASE_WVR + i); 765 - if (val != (addr & ~alignment_mask)) 766 - goto unlock; 767 - 768 - /* Possible match, check the byte address select. */ 769 - ctrl_reg = read_wb_reg(ARM_BASE_WCR + i); 770 - decode_ctrl_reg(ctrl_reg, &ctrl); 771 - if (!((1 << (addr & alignment_mask)) & ctrl.len)) 772 - goto unlock; 773 - 774 723 /* Check that the access type matches. */ 775 724 if (debug_exception_updates_fsr()) { 776 725 access = (fsr & ARM_FSR_ACCESS_MASK) ? 777 726 HW_BREAKPOINT_W : HW_BREAKPOINT_R; 778 727 if (!(access & hw_breakpoint_type(wp))) 779 - goto unlock; 728 + continue; 780 729 } 781 730 731 + val = read_wb_reg(ARM_BASE_WVR + i); 732 + ctrl_reg = read_wb_reg(ARM_BASE_WCR + i); 733 + decode_ctrl_reg(ctrl_reg, &ctrl); 734 + dist = get_distance_from_watchpoint(addr, val, &ctrl); 735 + if (dist < min_dist) { 736 + min_dist = dist; 737 + closest_match = i; 738 + } 739 + /* Is this an exact match? */ 740 + if (dist != 0) 741 + continue; 742 + 782 743 /* We have a winner. */ 744 + info = counter_arch_bp(wp); 783 745 info->trigger = addr; 784 746 } 785 747 ··· 799 765 * we can single-step over the watchpoint trigger. 800 766 */ 801 767 if (!is_default_overflow_handler(wp)) 802 - goto unlock; 803 - 768 + continue; 804 769 step: 805 770 enable_single_step(wp, instruction_pointer(regs)); 806 - unlock: 807 - rcu_read_unlock(); 808 771 } 772 + 773 + if (min_dist > 0 && min_dist != -1) { 774 + /* No exact match found. */ 775 + wp = slots[closest_match]; 776 + info = counter_arch_bp(wp); 777 + info->trigger = addr; 778 + pr_debug("watchpoint fired: address = 0x%x\n", info->trigger); 779 + perf_bp_event(wp, regs); 780 + if (is_default_overflow_handler(wp)) 781 + enable_single_step(wp, instruction_pointer(regs)); 782 + } 783 + 784 + rcu_read_unlock(); 809 785 } 810 786 811 787 static void watchpoint_single_step_handler(unsigned long pc)
+12 -4
arch/arm/mm/cache-l2x0.c
··· 1249 1249 1250 1250 ret = of_property_read_u32(np, "prefetch-data", &val); 1251 1251 if (ret == 0) { 1252 - if (val) 1252 + if (val) { 1253 1253 prefetch |= L310_PREFETCH_CTRL_DATA_PREFETCH; 1254 - else 1254 + *aux_val |= L310_PREFETCH_CTRL_DATA_PREFETCH; 1255 + } else { 1255 1256 prefetch &= ~L310_PREFETCH_CTRL_DATA_PREFETCH; 1257 + *aux_val &= ~L310_PREFETCH_CTRL_DATA_PREFETCH; 1258 + } 1259 + *aux_mask &= ~L310_PREFETCH_CTRL_DATA_PREFETCH; 1256 1260 } else if (ret != -EINVAL) { 1257 1261 pr_err("L2C-310 OF prefetch-data property value is missing\n"); 1258 1262 } 1259 1263 1260 1264 ret = of_property_read_u32(np, "prefetch-instr", &val); 1261 1265 if (ret == 0) { 1262 - if (val) 1266 + if (val) { 1263 1267 prefetch |= L310_PREFETCH_CTRL_INSTR_PREFETCH; 1264 - else 1268 + *aux_val |= L310_PREFETCH_CTRL_INSTR_PREFETCH; 1269 + } else { 1265 1270 prefetch &= ~L310_PREFETCH_CTRL_INSTR_PREFETCH; 1271 + *aux_val &= ~L310_PREFETCH_CTRL_INSTR_PREFETCH; 1272 + } 1273 + *aux_mask &= ~L310_PREFETCH_CTRL_INSTR_PREFETCH; 1266 1274 } else if (ret != -EINVAL) { 1267 1275 pr_err("L2C-310 OF prefetch-instr property value is missing\n"); 1268 1276 }