tjh.dev / kernel
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Merge tag 'arc-5.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc

Pull ARC updates from Vineet Gupta:
"The bulk of ARC pull request is removal of EZChip NPS platform which
was suffering from constant bitrot. In recent years EZChip has gone
though multiple successive acquisitions and I guess things and people
move on. I would like to take this opportunity to recognize and thank
all those good folks (Gilad, Noam, Ofer...) for contributing major
bits to ARC port (SMP, Big Endian).

Summary:

- drop support for EZChip NPS platform

- misc other fixes"

* tag 'arc-5.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
arc: include/asm: fix typos of "themselves"
ARC: SMP: fix typo and use "come up" instead of "comeup"
ARC: [dts] fix the errors detected by dtbs_check
arc: plat-hsdk: fix kconfig dependency warning when !RESET_CONTROLLER
ARC: [plat-eznps]: Drop support for EZChip NPS platform

Linus Torvalds b32649b8 270315b8

+15 -1362
-7
MAINTAINERS
··· 6652 6652 S: Maintained 6653 6653 F: drivers/iommu/exynos-iommu.c 6654 6654 6655 - EZchip NPS platform support 6656 - M: Vineet Gupta <vgupta@synopsys.com> 6657 - M: Ofer Levi <oferle@nvidia.com> 6658 - S: Supported 6659 - F: arch/arc/boot/dts/eznps.dts 6660 - F: arch/arc/plat-eznps 6661 - 6662 6655 F2FS FILE SYSTEM 6663 6656 M: Jaegeuk Kim <jaegeuk@kernel.org> 6664 6657 M: Chao Yu <yuchao0@huawei.com>
-2
arch/arc/Kconfig
··· 96 96 97 97 source "arch/arc/plat-tb10x/Kconfig" 98 98 source "arch/arc/plat-axs10x/Kconfig" 99 - #New platform adds here 100 - source "arch/arc/plat-eznps/Kconfig" 101 99 source "arch/arc/plat-hsdk/Kconfig" 102 100 103 101 endmenu
-5
arch/arc/Makefile
··· 94 94 core-y += arch/arc/plat-sim/ 95 95 core-$(CONFIG_ARC_PLAT_TB10X) += arch/arc/plat-tb10x/ 96 96 core-$(CONFIG_ARC_PLAT_AXS10X) += arch/arc/plat-axs10x/ 97 - core-$(CONFIG_ARC_PLAT_EZNPS) += arch/arc/plat-eznps/ 98 97 core-$(CONFIG_ARC_SOC_HSDK) += arch/arc/plat-hsdk/ 99 - 100 - ifdef CONFIG_ARC_PLAT_EZNPS 101 - KBUILD_CPPFLAGS += -I$(srctree)/arch/arc/plat-eznps/include 102 - endif 103 98 104 99 drivers-$(CONFIG_OPROFILE) += arch/arc/oprofile/ 105 100
+1 -1
arch/arc/boot/dts/axc001.dtsi
··· 91 91 * avoid duplicating the MB dtsi file given that IRQ from 92 92 * this intc to cpu intc are different for axs101 and axs103 93 93 */ 94 - mb_intc: dw-apb-ictl@e0012000 { 94 + mb_intc: interrupt-controller@e0012000 { 95 95 #interrupt-cells = <1>; 96 96 compatible = "snps,dw-apb-ictl"; 97 97 reg = < 0x0 0xe0012000 0x0 0x200 >;
+1 -1
arch/arc/boot/dts/axc003.dtsi
··· 129 129 * avoid duplicating the MB dtsi file given that IRQ from 130 130 * this intc to cpu intc are different for axs101 and axs103 131 131 */ 132 - mb_intc: dw-apb-ictl@e0012000 { 132 + mb_intc: interrupt-controller@e0012000 { 133 133 #interrupt-cells = <1>; 134 134 compatible = "snps,dw-apb-ictl"; 135 135 reg = < 0x0 0xe0012000 0x0 0x200 >;
+1 -1
arch/arc/boot/dts/axc003_idu.dtsi
··· 135 135 * avoid duplicating the MB dtsi file given that IRQ from 136 136 * this intc to cpu intc are different for axs101 and axs103 137 137 */ 138 - mb_intc: dw-apb-ictl@e0012000 { 138 + mb_intc: interrupt-controller@e0012000 { 139 139 #interrupt-cells = <1>; 140 140 compatible = "snps,dw-apb-ictl"; 141 141 reg = < 0x0 0xe0012000 0x0 0x200 >;
-84
arch/arc/boot/dts/eznps.dts
··· 1 - // SPDX-License-Identifier: GPL-2.0-only 2 - /* 3 - * Copyright(c) 2015 EZchip Technologies. 4 - */ 5 - 6 - /dts-v1/; 7 - 8 - / { 9 - compatible = "ezchip,arc-nps"; 10 - #address-cells = <1>; 11 - #size-cells = <1>; 12 - interrupt-parent = <&intc>; 13 - present-cpus = "0-1,16-17"; 14 - possible-cpus = "0-4095"; 15 - 16 - aliases { 17 - ethernet0 = &gmac0; 18 - }; 19 - 20 - chosen { 21 - bootargs = "earlycon=uart8250,mmio32be,0xf7209000,115200n8 console=ttyS0,115200n8"; 22 - }; 23 - 24 - memory { 25 - device_type = "memory"; 26 - reg = <0x80000000 0x20000000>; /* 512M */ 27 - }; 28 - 29 - clocks { 30 - sysclk: sysclk { 31 - compatible = "fixed-clock"; 32 - #clock-cells = <0>; 33 - clock-frequency = <83333333>; 34 - }; 35 - }; 36 - 37 - soc { 38 - compatible = "simple-bus"; 39 - #address-cells = <1>; 40 - #size-cells = <1>; 41 - 42 - /* child and parent address space 1:1 mapped */ 43 - ranges; 44 - 45 - intc: interrupt-controller { 46 - compatible = "ezchip,nps400-ic"; 47 - interrupt-controller; 48 - #interrupt-cells = <1>; 49 - }; 50 - 51 - timer0: timer_clkevt { 52 - compatible = "snps,arc-timer"; 53 - interrupts = <3>; 54 - clocks = <&sysclk>; 55 - }; 56 - 57 - timer1: timer_clksrc { 58 - compatible = "ezchip,nps400-timer"; 59 - clocks = <&sysclk>; 60 - clock-names="sysclk"; 61 - }; 62 - 63 - uart@f7209000 { 64 - compatible = "snps,dw-apb-uart"; 65 - device_type = "serial"; 66 - reg = <0xf7209000 0x100>; 67 - interrupts = <6>; 68 - clocks = <&sysclk>; 69 - clock-names="baudclk"; 70 - baud = <115200>; 71 - reg-shift = <2>; 72 - reg-io-width = <4>; 73 - native-endian; 74 - }; 75 - 76 - gmac0: ethernet@f7470000 { 77 - compatible = "ezchip,nps-mgt-enet"; 78 - reg = <0xf7470000 0x1940>; 79 - interrupts = <7>; 80 - /* Filled in by U-Boot */ 81 - mac-address = [ 00 C0 00 F0 04 03 ]; 82 - }; 83 - }; 84 - };
+1 -1
arch/arc/boot/dts/vdk_axc003.dtsi
··· 46 46 47 47 }; 48 48 49 - mb_intc: dw-apb-ictl@e0012000 { 49 + mb_intc: interrupt-controller@e0012000 { 50 50 #interrupt-cells = <1>; 51 51 compatible = "snps,dw-apb-ictl"; 52 52 reg = < 0xe0012000 0x200 >;
+1 -1
arch/arc/boot/dts/vdk_axc003_idu.dtsi
··· 54 54 55 55 }; 56 56 57 - mb_intc: dw-apb-ictl@e0012000 { 57 + mb_intc: interrupt-controller@e0012000 { 58 58 #interrupt-cells = <1>; 59 59 compatible = "snps,dw-apb-ictl"; 60 60 reg = < 0xe0012000 0x200 >;
-80
arch/arc/configs/nps_defconfig
··· 1 - # CONFIG_LOCALVERSION_AUTO is not set 2 - # CONFIG_SWAP is not set 3 - CONFIG_SYSVIPC=y 4 - CONFIG_NO_HZ_IDLE=y 5 - CONFIG_HIGH_RES_TIMERS=y 6 - CONFIG_IKCONFIG=y 7 - CONFIG_IKCONFIG_PROC=y 8 - CONFIG_BLK_DEV_INITRD=y 9 - CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE_O3=y 10 - # CONFIG_EPOLL is not set 11 - # CONFIG_SIGNALFD is not set 12 - # CONFIG_TIMERFD is not set 13 - # CONFIG_EVENTFD is not set 14 - # CONFIG_AIO is not set 15 - CONFIG_EMBEDDED=y 16 - CONFIG_PERF_EVENTS=y 17 - # CONFIG_COMPAT_BRK is not set 18 - CONFIG_ISA_ARCOMPACT=y 19 - CONFIG_KPROBES=y 20 - CONFIG_MODULES=y 21 - CONFIG_MODULE_FORCE_LOAD=y 22 - CONFIG_MODULE_UNLOAD=y 23 - # CONFIG_BLK_DEV_BSG is not set 24 - CONFIG_ARC_PLAT_EZNPS=y 25 - CONFIG_SMP=y 26 - CONFIG_NR_CPUS=4096 27 - CONFIG_ARC_CACHE_LINE_SHIFT=5 28 - # CONFIG_ARC_CACHE_PAGES is not set 29 - # CONFIG_ARC_HAS_LLSC is not set 30 - CONFIG_ARC_KVADDR_SIZE=402 31 - CONFIG_ARC_EMUL_UNALIGNED=y 32 - CONFIG_PREEMPT=y 33 - CONFIG_NET=y 34 - CONFIG_UNIX=y 35 - CONFIG_INET=y 36 - CONFIG_IP_PNP=y 37 - # CONFIG_INET_XFRM_MODE_TRANSPORT is not set 38 - # CONFIG_INET_XFRM_MODE_TUNNEL is not set 39 - # CONFIG_INET_XFRM_MODE_BEET is not set 40 - # CONFIG_INET_DIAG is not set 41 - # CONFIG_IPV6 is not set 42 - # CONFIG_WIRELESS is not set 43 - CONFIG_DEVTMPFS=y 44 - CONFIG_DEVTMPFS_MOUNT=y 45 - # CONFIG_PREVENT_FIRMWARE_BUILD is not set 46 - CONFIG_BLK_DEV_RAM=y 47 - CONFIG_BLK_DEV_RAM_COUNT=1 48 - CONFIG_BLK_DEV_RAM_SIZE=2048 49 - CONFIG_NETDEVICES=y 50 - CONFIG_NETCONSOLE=y 51 - # CONFIG_NET_VENDOR_BROADCOM is not set 52 - # CONFIG_NET_VENDOR_MICREL is not set 53 - # CONFIG_NET_VENDOR_STMICRO is not set 54 - # CONFIG_WLAN is not set 55 - # CONFIG_INPUT_MOUSEDEV is not set 56 - # CONFIG_INPUT_KEYBOARD is not set 57 - # CONFIG_INPUT_MOUSE is not set 58 - # CONFIG_SERIO is not set 59 - # CONFIG_LEGACY_PTYS is not set 60 - CONFIG_SERIAL_8250=y 61 - CONFIG_SERIAL_8250_CONSOLE=y 62 - CONFIG_SERIAL_8250_NR_UARTS=1 63 - CONFIG_SERIAL_8250_RUNTIME_UARTS=1 64 - CONFIG_SERIAL_8250_DW=y 65 - CONFIG_SERIAL_OF_PLATFORM=y 66 - # CONFIG_HW_RANDOM is not set 67 - # CONFIG_HWMON is not set 68 - # CONFIG_USB_SUPPORT is not set 69 - # CONFIG_DNOTIFY is not set 70 - CONFIG_PROC_KCORE=y 71 - CONFIG_TMPFS=y 72 - # CONFIG_MISC_FILESYSTEMS is not set 73 - CONFIG_NFS_FS=y 74 - CONFIG_NFS_V3_ACL=y 75 - CONFIG_ROOT_NFS=y 76 - CONFIG_DEBUG_INFO=y 77 - # CONFIG_ENABLE_MUST_CHECK is not set 78 - CONFIG_MAGIC_SYSRQ=y 79 - CONFIG_DEBUG_MEMORY_INIT=y 80 - CONFIG_ENABLE_DEFAULT_TRACERS=y
+2 -106
arch/arc/include/asm/atomic.h
··· 14 14 #include <asm/barrier.h> 15 15 #include <asm/smp.h> 16 16 17 - #ifndef CONFIG_ARC_PLAT_EZNPS 18 - 19 17 #define atomic_read(v) READ_ONCE((v)->counter) 20 18 21 19 #ifdef CONFIG_ARC_HAS_LLSC ··· 43 45 \ 44 46 /* \ 45 47 * Explicit full memory barrier needed before/after as \ 46 - * LLOCK/SCOND thmeselves don't provide any such semantics \ 48 + * LLOCK/SCOND themselves don't provide any such semantics \ 47 49 */ \ 48 50 smp_mb(); \ 49 51 \ ··· 69 71 \ 70 72 /* \ 71 73 * Explicit full memory barrier needed before/after as \ 72 - * LLOCK/SCOND thmeselves don't provide any such semantics \ 74 + * LLOCK/SCOND themselves don't provide any such semantics \ 73 75 */ \ 74 76 smp_mb(); \ 75 77 \ ··· 192 194 ATOMIC_OPS(andnot, &= ~, bic) 193 195 ATOMIC_OPS(or, |=, or) 194 196 ATOMIC_OPS(xor, ^=, xor) 195 - 196 - #else /* CONFIG_ARC_PLAT_EZNPS */ 197 - 198 - static inline int atomic_read(const atomic_t *v) 199 - { 200 - int temp; 201 - 202 - __asm__ __volatile__( 203 - " ld.di %0, [%1]" 204 - : "=r"(temp) 205 - : "r"(&v->counter) 206 - : "memory"); 207 - return temp; 208 - } 209 - 210 - static inline void atomic_set(atomic_t *v, int i) 211 - { 212 - __asm__ __volatile__( 213 - " st.di %0,[%1]" 214 - : 215 - : "r"(i), "r"(&v->counter) 216 - : "memory"); 217 - } 218 - 219 - #define ATOMIC_OP(op, c_op, asm_op) \ 220 - static inline void atomic_##op(int i, atomic_t *v) \ 221 - { \ 222 - __asm__ __volatile__( \ 223 - " mov r2, %0\n" \ 224 - " mov r3, %1\n" \ 225 - " .word %2\n" \ 226 - : \ 227 - : "r"(i), "r"(&v->counter), "i"(asm_op) \ 228 - : "r2", "r3", "memory"); \ 229 - } \ 230 - 231 - #define ATOMIC_OP_RETURN(op, c_op, asm_op) \ 232 - static inline int atomic_##op##_return(int i, atomic_t *v) \ 233 - { \ 234 - unsigned int temp = i; \ 235 - \ 236 - /* Explicit full memory barrier needed before/after */ \ 237 - smp_mb(); \ 238 - \ 239 - __asm__ __volatile__( \ 240 - " mov r2, %0\n" \ 241 - " mov r3, %1\n" \ 242 - " .word %2\n" \ 243 - " mov %0, r2" \ 244 - : "+r"(temp) \ 245 - : "r"(&v->counter), "i"(asm_op) \ 246 - : "r2", "r3", "memory"); \ 247 - \ 248 - smp_mb(); \ 249 - \ 250 - temp c_op i; \ 251 - \ 252 - return temp; \ 253 - } 254 - 255 - #define ATOMIC_FETCH_OP(op, c_op, asm_op) \ 256 - static inline int atomic_fetch_##op(int i, atomic_t *v) \ 257 - { \ 258 - unsigned int temp = i; \ 259 - \ 260 - /* Explicit full memory barrier needed before/after */ \ 261 - smp_mb(); \ 262 - \ 263 - __asm__ __volatile__( \ 264 - " mov r2, %0\n" \ 265 - " mov r3, %1\n" \ 266 - " .word %2\n" \ 267 - " mov %0, r2" \ 268 - : "+r"(temp) \ 269 - : "r"(&v->counter), "i"(asm_op) \ 270 - : "r2", "r3", "memory"); \ 271 - \ 272 - smp_mb(); \ 273 - \ 274 - return temp; \ 275 - } 276 - 277 - #define ATOMIC_OPS(op, c_op, asm_op) \ 278 - ATOMIC_OP(op, c_op, asm_op) \ 279 - ATOMIC_OP_RETURN(op, c_op, asm_op) \ 280 - ATOMIC_FETCH_OP(op, c_op, asm_op) 281 - 282 - ATOMIC_OPS(add, +=, CTOP_INST_AADD_DI_R2_R2_R3) 283 - #define atomic_sub(i, v) atomic_add(-(i), (v)) 284 - #define atomic_sub_return(i, v) atomic_add_return(-(i), (v)) 285 - #define atomic_fetch_sub(i, v) atomic_fetch_add(-(i), (v)) 286 - 287 - #undef ATOMIC_OPS 288 - #define ATOMIC_OPS(op, c_op, asm_op) \ 289 - ATOMIC_OP(op, c_op, asm_op) \ 290 - ATOMIC_FETCH_OP(op, c_op, asm_op) 291 - 292 - ATOMIC_OPS(and, &=, CTOP_INST_AAND_DI_R2_R2_R3) 293 - ATOMIC_OPS(or, |=, CTOP_INST_AOR_DI_R2_R2_R3) 294 - ATOMIC_OPS(xor, ^=, CTOP_INST_AXOR_DI_R2_R2_R3) 295 - 296 - #endif /* CONFIG_ARC_PLAT_EZNPS */ 297 197 298 198 #undef ATOMIC_OPS 299 199 #undef ATOMIC_FETCH_OP
+1 -8
arch/arc/include/asm/barrier.h
··· 27 27 #define rmb() asm volatile("dmb 1\n" : : : "memory") 28 28 #define wmb() asm volatile("dmb 2\n" : : : "memory") 29 29 30 - #elif !defined(CONFIG_ARC_PLAT_EZNPS) /* CONFIG_ISA_ARCOMPACT */ 30 + #else 31 31 32 32 /* 33 33 * ARCompact based cores (ARC700) only have SYNC instruction which is super ··· 36 36 */ 37 37 38 38 #define mb() asm volatile("sync\n" : : : "memory") 39 - 40 - #else /* CONFIG_ARC_PLAT_EZNPS */ 41 - 42 - #include <plat/ctop.h> 43 - 44 - #define mb() asm volatile (".word %0" : : "i"(CTOP_INST_SCHD_RW) : "memory") 45 - #define rmb() asm volatile (".word %0" : : "i"(CTOP_INST_SCHD_RD) : "memory") 46 39 47 40 #endif 48 41
+2 -56
arch/arc/include/asm/bitops.h
··· 85 85 return (old & (1 << nr)) != 0; \ 86 86 } 87 87 88 - #elif !defined(CONFIG_ARC_PLAT_EZNPS) 88 + #else /* !CONFIG_ARC_HAS_LLSC */ 89 89 90 90 /* 91 91 * Non hardware assisted Atomic-R-M-W ··· 136 136 return (old & (1UL << (nr & 0x1f))) != 0; \ 137 137 } 138 138 139 - #else /* CONFIG_ARC_PLAT_EZNPS */ 140 - 141 - #define BIT_OP(op, c_op, asm_op) \ 142 - static inline void op##_bit(unsigned long nr, volatile unsigned long *m)\ 143 - { \ 144 - m += nr >> 5; \ 145 - \ 146 - nr = (1UL << (nr & 0x1f)); \ 147 - if (asm_op == CTOP_INST_AAND_DI_R2_R2_R3) \ 148 - nr = ~nr; \ 149 - \ 150 - __asm__ __volatile__( \ 151 - " mov r2, %0\n" \ 152 - " mov r3, %1\n" \ 153 - " .word %2\n" \ 154 - : \ 155 - : "r"(nr), "r"(m), "i"(asm_op) \ 156 - : "r2", "r3", "memory"); \ 157 - } 158 - 159 - #define TEST_N_BIT_OP(op, c_op, asm_op) \ 160 - static inline int test_and_##op##_bit(unsigned long nr, volatile unsigned long *m)\ 161 - { \ 162 - unsigned long old; \ 163 - \ 164 - m += nr >> 5; \ 165 - \ 166 - nr = old = (1UL << (nr & 0x1f)); \ 167 - if (asm_op == CTOP_INST_AAND_DI_R2_R2_R3) \ 168 - old = ~old; \ 169 - \ 170 - /* Explicit full memory barrier needed before/after */ \ 171 - smp_mb(); \ 172 - \ 173 - __asm__ __volatile__( \ 174 - " mov r2, %0\n" \ 175 - " mov r3, %1\n" \ 176 - " .word %2\n" \ 177 - " mov %0, r2" \ 178 - : "+r"(old) \ 179 - : "r"(m), "i"(asm_op) \ 180 - : "r2", "r3", "memory"); \ 181 - \ 182 - smp_mb(); \ 183 - \ 184 - return (old & nr) != 0; \ 185 - } 186 - 187 - #endif /* CONFIG_ARC_PLAT_EZNPS */ 139 + #endif 188 140 189 141 /*************************************** 190 142 * Non atomic variants ··· 178 226 /* __test_and_set_bit(), __test_and_clear_bit(), __test_and_change_bit() */\ 179 227 __TEST_N_BIT_OP(op, c_op, asm_op) 180 228 181 - #ifndef CONFIG_ARC_PLAT_EZNPS 182 229 BIT_OPS(set, |, bset) 183 230 BIT_OPS(clear, & ~, bclr) 184 231 BIT_OPS(change, ^, bxor) 185 - #else 186 - BIT_OPS(set, |, CTOP_INST_AOR_DI_R2_R2_R3) 187 - BIT_OPS(clear, & ~, CTOP_INST_AAND_DI_R2_R2_R3) 188 - BIT_OPS(change, ^, CTOP_INST_AXOR_DI_R2_R2_R3) 189 - #endif 190 232 191 233 /* 192 234 * This routine doesn't need to be atomic.
+3 -69
arch/arc/include/asm/cmpxchg.h
··· 20 20 21 21 /* 22 22 * Explicit full memory barrier needed before/after as 23 - * LLOCK/SCOND thmeselves don't provide any such semantics 23 + * LLOCK/SCOND themselves don't provide any such semantics 24 24 */ 25 25 smp_mb(); 26 26 ··· 41 41 return prev; 42 42 } 43 43 44 - #elif !defined(CONFIG_ARC_PLAT_EZNPS) 44 + #else /* !CONFIG_ARC_HAS_LLSC */ 45 45 46 46 static inline unsigned long 47 47 __cmpxchg(volatile void *ptr, unsigned long expected, unsigned long new) ··· 61 61 return prev; 62 62 } 63 63 64 - #else /* CONFIG_ARC_PLAT_EZNPS */ 65 - 66 - static inline unsigned long 67 - __cmpxchg(volatile void *ptr, unsigned long expected, unsigned long new) 68 - { 69 - /* 70 - * Explicit full memory barrier needed before/after 71 - */ 72 - smp_mb(); 73 - 74 - write_aux_reg(CTOP_AUX_GPA1, expected); 75 - 76 - __asm__ __volatile__( 77 - " mov r2, %0\n" 78 - " mov r3, %1\n" 79 - " .word %2\n" 80 - " mov %0, r2" 81 - : "+r"(new) 82 - : "r"(ptr), "i"(CTOP_INST_EXC_DI_R2_R2_R3) 83 - : "r2", "r3", "memory"); 84 - 85 - smp_mb(); 86 - 87 - return new; 88 - } 89 - 90 - #endif /* CONFIG_ARC_HAS_LLSC */ 64 + #endif 91 65 92 66 #define cmpxchg(ptr, o, n) ({ \ 93 67 (typeof(*(ptr)))__cmpxchg((ptr), \ ··· 77 103 */ 78 104 #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n))) 79 105 80 - 81 - #ifndef CONFIG_ARC_PLAT_EZNPS 82 106 83 107 /* 84 108 * xchg (reg with memory) based on "Native atomic" EX insn ··· 139 167 #define xchg(ptr, with) _xchg(ptr, with) 140 168 141 169 #endif 142 - 143 - #else /* CONFIG_ARC_PLAT_EZNPS */ 144 - 145 - static inline unsigned long __xchg(unsigned long val, volatile void *ptr, 146 - int size) 147 - { 148 - extern unsigned long __xchg_bad_pointer(void); 149 - 150 - switch (size) { 151 - case 4: 152 - /* 153 - * Explicit full memory barrier needed before/after 154 - */ 155 - smp_mb(); 156 - 157 - __asm__ __volatile__( 158 - " mov r2, %0\n" 159 - " mov r3, %1\n" 160 - " .word %2\n" 161 - " mov %0, r2\n" 162 - : "+r"(val) 163 - : "r"(ptr), "i"(CTOP_INST_XEX_DI_R2_R2_R3) 164 - : "r2", "r3", "memory"); 165 - 166 - smp_mb(); 167 - 168 - return val; 169 - } 170 - return __xchg_bad_pointer(); 171 - } 172 - 173 - #define xchg(ptr, with) ({ \ 174 - (typeof(*(ptr)))__xchg((unsigned long)(with), \ 175 - (ptr), \ 176 - sizeof(*(ptr))); \ 177 - }) 178 - 179 - #endif /* CONFIG_ARC_PLAT_EZNPS */ 180 170 181 171 /* 182 172 * "atomic" variant of xchg()
-27
arch/arc/include/asm/entry-compact.h
··· 33 33 #include <asm/irqflags-compact.h> 34 34 #include <asm/thread_info.h> /* For THREAD_SIZE */ 35 35 36 - #ifdef CONFIG_ARC_PLAT_EZNPS 37 - #include <plat/ctop.h> 38 - #endif 39 - 40 36 /*-------------------------------------------------------------- 41 37 * Switch to Kernel Mode stack if SP points to User Mode stack 42 38 * ··· 185 189 PUSHAX lp_start 186 190 PUSHAX erbta 187 191 188 - #ifdef CONFIG_ARC_PLAT_EZNPS 189 - .word CTOP_INST_SCHD_RW 190 - PUSHAX CTOP_AUX_GPA1 191 - PUSHAX CTOP_AUX_EFLAGS 192 - #endif 193 - 194 192 lr r10, [ecr] 195 193 st r10, [sp, PT_event] /* EV_Trap expects r10 to have ECR */ 196 194 .endm ··· 201 211 * by hardware and that is not good. 202 212 *-------------------------------------------------------------*/ 203 213 .macro EXCEPTION_EPILOGUE 204 - #ifdef CONFIG_ARC_PLAT_EZNPS 205 - .word CTOP_INST_SCHD_RW 206 - POPAX CTOP_AUX_EFLAGS 207 - POPAX CTOP_AUX_GPA1 208 - #endif 209 214 210 215 POPAX erbta 211 216 POPAX lp_start ··· 263 278 PUSHAX lp_start 264 279 PUSHAX bta_l\LVL\() 265 280 266 - #ifdef CONFIG_ARC_PLAT_EZNPS 267 - .word CTOP_INST_SCHD_RW 268 - PUSHAX CTOP_AUX_GPA1 269 - PUSHAX CTOP_AUX_EFLAGS 270 - #endif 271 281 .endm 272 282 273 283 /*-------------------------------------------------------------- ··· 275 295 * by hardware and that is not good. 276 296 *-------------------------------------------------------------*/ 277 297 .macro INTERRUPT_EPILOGUE LVL 278 - #ifdef CONFIG_ARC_PLAT_EZNPS 279 - .word CTOP_INST_SCHD_RW 280 - POPAX CTOP_AUX_EFLAGS 281 - POPAX CTOP_AUX_GPA1 282 - #endif 283 298 284 299 POPAX bta_l\LVL\() 285 300 POPAX lp_start ··· 302 327 bic \reg, sp, (THREAD_SIZE - 1) 303 328 .endm 304 329 305 - #ifndef CONFIG_ARC_PLAT_EZNPS 306 330 /* Get CPU-ID of this core */ 307 331 .macro GET_CPU_ID reg 308 332 lr \reg, [identity] 309 333 lsr \reg, \reg, 8 310 334 bmsk \reg, \reg, 7 311 335 .endm 312 - #endif 313 336 314 337 #endif /* __ASM_ARC_ENTRY_COMPACT_H */
-37
arch/arc/include/asm/processor.h
··· 17 17 #include <asm/dsp.h> 18 18 #include <asm/fpu.h> 19 19 20 - #ifdef CONFIG_ARC_PLAT_EZNPS 21 - struct eznps_dp { 22 - unsigned int eflags; 23 - unsigned int gpa1; 24 - }; 25 - #endif 26 - 27 20 /* Arch specific stuff which needs to be saved per task. 28 21 * However these items are not so important so as to earn a place in 29 22 * struct thread_info ··· 30 37 #endif 31 38 #ifdef CONFIG_ARC_FPU_SAVE_RESTORE 32 39 struct arc_fpu fpu; 33 - #endif 34 - #ifdef CONFIG_ARC_PLAT_EZNPS 35 - struct eznps_dp dp; 36 40 #endif 37 41 }; 38 42 ··· 50 60 * A lot of busy-wait loops in SMP are based off of non-volatile data otherwise 51 61 * get optimised away by gcc 52 62 */ 53 - #ifndef CONFIG_EZNPS_MTM_EXT 54 - 55 63 #define cpu_relax() barrier() 56 - 57 - #else 58 - 59 - #define cpu_relax() \ 60 - __asm__ __volatile__ (".word %0" : : "i"(CTOP_INST_SCHD_RW) : "memory") 61 - 62 - #endif 63 64 64 65 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->ret) 65 66 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->sp) ··· 99 118 100 119 #define USER_KERNEL_GUTTER (VMALLOC_START - TASK_SIZE) 101 120 102 - #ifdef CONFIG_ARC_PLAT_EZNPS 103 - /* NPS architecture defines special window of 129M in user address space for 104 - * special memory areas, when accessing this window the MMU do not use TLB. 105 - * Instead MMU direct the access to: 106 - * 0x57f00000:0x57ffffff -- 1M of closely coupled memory (aka CMEM) 107 - * 0x58000000:0x5fffffff -- 16 huge pages, 8M each, with fixed map (aka FMTs) 108 - * 109 - * CMEM - is the fastest memory we got and its size is 16K. 110 - * FMT - is used to map either to internal/external memory. 111 - * Internal memory is the second fast memory and its size is 16M 112 - * External memory is the biggest memory (16G) and also the slowest. 113 - * 114 - * STACK_TOP need to be PMD align (21bit) that is why we supply 0x57e00000. 115 - */ 116 - #define STACK_TOP 0x57e00000 117 - #else 118 121 #define STACK_TOP TASK_SIZE 119 - #endif 120 - 121 122 #define STACK_TOP_MAX STACK_TOP 122 123 123 124 /* This decides where the kernel will search for a free chunk of vm
-5
arch/arc/include/asm/ptrace.h
··· 16 16 #ifdef CONFIG_ISA_ARCOMPACT 17 17 struct pt_regs { 18 18 19 - #ifdef CONFIG_ARC_PLAT_EZNPS 20 - unsigned long eflags; /* Extended FLAGS */ 21 - unsigned long gpa1; /* General Purpose Aux */ 22 - #endif 23 - 24 19 /* Real registers */ 25 20 unsigned long bta; /* bta_l1, bta_l2, erbta */ 26 21
-4
arch/arc/include/asm/setup.h
··· 9 9 #include <linux/types.h> 10 10 #include <uapi/asm/setup.h> 11 11 12 - #ifdef CONFIG_ARC_PLAT_EZNPS 13 - #define COMMAND_LINE_SIZE 2048 14 - #else 15 12 #define COMMAND_LINE_SIZE 256 16 - #endif 17 13 18 14 /* 19 15 * Data structure to map a ID to string
-6
arch/arc/include/asm/spinlock.h
··· 232 232 233 233 __asm__ __volatile__( 234 234 "1: ex %0, [%1] \n" 235 - #ifdef CONFIG_EZNPS_MTM_EXT 236 - " .word %3 \n" 237 - #endif 238 235 " breq %0, %2, 1b \n" 239 236 : "+&r" (val) 240 237 : "r"(&(lock->slock)), "ir"(__ARCH_SPIN_LOCK_LOCKED__) 241 - #ifdef CONFIG_EZNPS_MTM_EXT 242 - , "i"(CTOP_INST_SCHD_RW) 243 - #endif 244 238 : "memory"); 245 239 246 240 smp_mb();
-9
arch/arc/include/asm/switch_to.h
··· 12 12 #include <asm/dsp-impl.h> 13 13 #include <asm/fpu.h> 14 14 15 - #ifdef CONFIG_ARC_PLAT_EZNPS 16 - extern void dp_save_restore(struct task_struct *p, struct task_struct *n); 17 - #define ARC_EZNPS_DP_PREV(p, n) dp_save_restore(p, n) 18 - #else 19 - #define ARC_EZNPS_DP_PREV(p, n) 20 - 21 - #endif /* !CONFIG_ARC_PLAT_EZNPS */ 22 - 23 15 struct task_struct *__switch_to(struct task_struct *p, struct task_struct *n); 24 16 25 17 #define switch_to(prev, next, last) \ 26 18 do { \ 27 - ARC_EZNPS_DP_PREV(prev, next); \ 28 19 dsp_save_restore(prev, next); \ 29 20 fpu_save_restore(prev, next); \ 30 21 last = __switch_to(prev, next);\
-13
arch/arc/kernel/ctx_sw.c
··· 14 14 #include <asm/asm-offsets.h> 15 15 #include <linux/sched.h> 16 16 #include <linux/sched/debug.h> 17 - #ifdef CONFIG_ARC_PLAT_EZNPS 18 - #include <plat/ctop.h> 19 - #endif 20 17 21 18 #define KSP_WORD_OFF ((TASK_THREAD + THREAD_KSP) / 4) 22 19 ··· 65 68 #ifndef CONFIG_SMP 66 69 "st %2, [@_current_task] \n\t" 67 70 #else 68 - #ifdef CONFIG_ARC_PLAT_EZNPS 69 - "lr r24, [%4] \n\t" 70 - #ifndef CONFIG_EZNPS_MTM_EXT 71 - "lsr r24, r24, 4 \n\t" 72 - #endif 73 - #else 74 71 "lr r24, [identity] \n\t" 75 72 "lsr r24, r24, 8 \n\t" 76 73 "bmsk r24, r24, 7 \n\t" 77 - #endif 78 74 "add2 r24, @_current_task, r24 \n\t" 79 75 "st %2, [r24] \n\t" 80 76 #endif ··· 105 115 106 116 : "=r"(tmp) 107 117 : "n"(KSP_WORD_OFF), "r"(next), "r"(prev) 108 - #ifdef CONFIG_ARC_PLAT_EZNPS 109 - , "i"(CTOP_AUX_LOGIC_GLOBAL_ID) 110 - #endif 111 118 : "blink" 112 119 ); 113 120
-2
arch/arc/kernel/devtree.c
··· 29 29 else if (of_flat_dt_is_compatible(dt_root, "snps,arc-sdp") || 30 30 of_flat_dt_is_compatible(dt_root, "snps,hsdk")) 31 31 arc_base_baud = 33333333; /* Fixed 33MHz clk (AXS10x & HSDK) */ 32 - else if (of_flat_dt_is_compatible(dt_root, "ezchip,arc-nps")) 33 - arc_base_baud = 800000000; /* Fixed 800MHz clk (NPS) */ 34 32 else 35 33 arc_base_baud = 50000000; /* Fixed default 50MHz */ 36 34 }
-15
arch/arc/kernel/process.c
··· 116 116 :"I"(arg)); /* can't be "r" has to be embedded const */ 117 117 } 118 118 119 - #elif defined(CONFIG_EZNPS_MTM_EXT) /* ARC700 variant in NPS */ 120 - 121 - void arch_cpu_idle(void) 122 - { 123 - /* only the calling HW thread needs to sleep */ 124 - __asm__ __volatile__( 125 - ".word %0 \n" 126 - : 127 - :"i"(CTOP_INST_HWSCHD_WFT_IE12)); 128 - } 129 - 130 119 #else /* ARC700 */ 131 120 132 121 void arch_cpu_idle(void) ··· 266 277 * Interrupts enabled 267 278 */ 268 279 regs->status32 = STATUS_U_MASK | STATUS_L_MASK | ISA_INIT_STATUS_BITS; 269 - 270 - #ifdef CONFIG_EZNPS_MTM_EXT 271 - regs->eflags = 0; 272 - #endif 273 280 274 281 fpu_init_task(regs); 275 282
+1 -1
arch/arc/kernel/smp.c
··· 226 226 } 227 227 228 228 if (!cpu_online(cpu)) { 229 - pr_info("Timeout: CPU%u FAILED to comeup !!!\n", cpu); 229 + pr_info("Timeout: CPU%u FAILED to come up !!!\n", cpu); 230 230 return -1; 231 231 } 232 232
-7
arch/arc/mm/tlbex.S
··· 281 281 .macro COMMIT_ENTRY_TO_MMU 282 282 #if (CONFIG_ARC_MMU_VER < 4) 283 283 284 - #ifdef CONFIG_EZNPS_MTM_EXT 285 - /* verify if entry for this vaddr+ASID already exists */ 286 - sr TLBProbe, [ARC_REG_TLBCOMMAND] 287 - lr r0, [ARC_REG_TLBINDEX] 288 - bbit0 r0, 31, 88f 289 - #endif 290 - 291 284 /* Get free TLB slot: Set = computed from vaddr, way = random */ 292 285 sr TLBGetIndex, [ARC_REG_TLBCOMMAND] 293 286
-58
arch/arc/plat-eznps/Kconfig
··· 1 - # SPDX-License-Identifier: GPL-2.0 2 - # 3 - # For a description of the syntax of this configuration file, 4 - # see Documentation/kbuild/kconfig-language.rst. 5 - # 6 - 7 - menuconfig ARC_PLAT_EZNPS 8 - bool "\"EZchip\" ARC dev platform" 9 - depends on ISA_ARCOMPACT 10 - select CPU_BIG_ENDIAN 11 - select CLKSRC_NPS if !PHYS_ADDR_T_64BIT 12 - select EZNPS_GIC 13 - select EZCHIP_NPS_MANAGEMENT_ENET if ETHERNET 14 - help 15 - Support for EZchip development platforms, 16 - based on ARC700 cores. 17 - We handle few flavors: 18 - - Hardware Emulator AKA HE which is FPGA based chassis 19 - - Simulator based on MetaWare nSIM 20 - - NPS400 chip based on ASIC 21 - 22 - config EZNPS_MTM_EXT 23 - bool "ARC-EZchip MTM Extensions" 24 - select CPUMASK_OFFSTACK 25 - depends on ARC_PLAT_EZNPS && SMP 26 - default y 27 - help 28 - Here we add new hierarchy for CPUs topology. 29 - We got: 30 - Core 31 - Thread 32 - At the new thread level each CPU represent one HW thread. 33 - At highest hierarchy each core contain 16 threads, 34 - any of them seem like CPU from Linux point of view. 35 - All threads within same core share the execution unit of the 36 - core and HW scheduler round robin between them. 37 - 38 - config EZNPS_MEM_ERROR_ALIGN 39 - bool "ARC-EZchip Memory error as an exception" 40 - depends on EZNPS_MTM_EXT 41 - default n 42 - help 43 - On the real chip of the NPS, user memory errors are handled 44 - as a machine check exception, which is fatal, whereas on 45 - simulator platform for NPS, is handled as a Level 2 interrupt 46 - (just a stock ARC700) which is recoverable. This option makes 47 - simulator behave like hardware. 48 - 49 - config EZNPS_SHARED_AUX_REGS 50 - bool "ARC-EZchip Shared Auxiliary Registers Per Core" 51 - depends on ARC_PLAT_EZNPS 52 - default y 53 - help 54 - On the real chip of the NPS, auxiliary registers are shared between 55 - all the cpus of the core, whereas on simulator platform for NPS, 56 - each cpu has a different set of auxiliary registers. Configuration 57 - should be unset if auxiliary registers are not shared between the cpus 58 - of the core, so there will be a need to initialize them per cpu.
-8
arch/arc/plat-eznps/Makefile
··· 1 - # SPDX-License-Identifier: GPL-2.0-only 2 - # 3 - # Makefile for the linux kernel. 4 - # 5 - 6 - obj-y := entry.o platform.o ctop.o 7 - obj-$(CONFIG_SMP) += smp.o 8 - obj-$(CONFIG_EZNPS_MTM_EXT) += mtm.o
-21
arch/arc/plat-eznps/ctop.c
··· 1 - // SPDX-License-Identifier: GPL-2.0-only 2 - /* 3 - * Copyright(c) 2015 EZchip Technologies. 4 - */ 5 - 6 - #include <linux/sched.h> 7 - #include <asm/processor.h> 8 - #include <plat/ctop.h> 9 - 10 - void dp_save_restore(struct task_struct *prev, struct task_struct *next) 11 - { 12 - struct eznps_dp *prev_task_dp = &prev->thread.dp; 13 - struct eznps_dp *next_task_dp = &next->thread.dp; 14 - 15 - /* Here we save all Data Plane related auxiliary registers */ 16 - prev_task_dp->eflags = read_aux_reg(CTOP_AUX_EFLAGS); 17 - write_aux_reg(CTOP_AUX_EFLAGS, next_task_dp->eflags); 18 - 19 - prev_task_dp->gpa1 = read_aux_reg(CTOP_AUX_GPA1); 20 - write_aux_reg(CTOP_AUX_GPA1, next_task_dp->gpa1); 21 - }
-60
arch/arc/plat-eznps/entry.S
··· 1 - /* SPDX-License-Identifier: GPL-2.0-only */ 2 - /******************************************************************************* 3 - 4 - EZNPS CPU startup Code 5 - Copyright(c) 2012 EZchip Technologies. 6 - 7 - 8 - *******************************************************************************/ 9 - #include <linux/linkage.h> 10 - #include <asm/entry.h> 11 - #include <asm/cache.h> 12 - #include <plat/ctop.h> 13 - 14 - .cpu A7 15 - 16 - .section .init.text, "ax",@progbits 17 - .align 1024 ; HW requierment for restart first PC 18 - 19 - ENTRY(res_service) 20 - #if defined(CONFIG_EZNPS_MTM_EXT) && defined(CONFIG_EZNPS_SHARED_AUX_REGS) 21 - ; There is no work for HW thread id != 0 22 - lr r3, [CTOP_AUX_THREAD_ID] 23 - cmp r3, 0 24 - jne stext 25 - #endif 26 - 27 - #ifdef CONFIG_ARC_HAS_DCACHE 28 - ; With no cache coherency mechanism D$ need to be used very carefully. 29 - ; Address space: 30 - ; 0G-2G: We disable CONFIG_ARC_CACHE_PAGES. 31 - ; 2G-3G: We disable D$ by setting this bit. 32 - ; 3G-4G: D$ is disabled by architecture. 33 - ; FMT are huge pages for user application reside at 0-2G. 34 - ; Only FMT left as one who can use D$ where each such page got 35 - ; disable/enable bit for cachability. 36 - ; Programmer will use FMT pages for private data so cache coherency 37 - ; would not be a problem. 38 - ; First thing we invalidate D$ 39 - sr 1, [ARC_REG_DC_IVDC] 40 - sr HW_COMPLY_KRN_NOT_D_CACHED, [CTOP_AUX_HW_COMPLY] 41 - #endif 42 - 43 - #ifdef CONFIG_SMP 44 - ; We set logical cpuid to be used by GET_CPUID 45 - ; We do not use physical cpuid since we want ids to be continious when 46 - ; it comes to cpus on the same quad cluster. 47 - ; This is useful for applications that used shared resources of a quad 48 - ; cluster such SRAMS. 49 - lr r3, [CTOP_AUX_CORE_ID] 50 - sr r3, [CTOP_AUX_LOGIC_CORE_ID] 51 - lr r3, [CTOP_AUX_CLUSTER_ID] 52 - ; Set logical is acheived by swap of 2 middle bits of cluster id (4 bit) 53 - ; r3 is used since we use short instruction and we need q-class reg 54 - .short CTOP_INST_MOV2B_FLIP_R3_B1_B2_INST 55 - .word CTOP_INST_MOV2B_FLIP_R3_B1_B2_LIMM 56 - sr r3, [CTOP_AUX_LOGIC_CLUSTER_ID] 57 - #endif 58 - 59 - j stext 60 - END(res_service)
-208
arch/arc/plat-eznps/include/plat/ctop.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0-only */ 2 - /* 3 - * Copyright(c) 2015 EZchip Technologies. 4 - */ 5 - 6 - #ifndef _PLAT_EZNPS_CTOP_H 7 - #define _PLAT_EZNPS_CTOP_H 8 - 9 - #ifndef CONFIG_ARC_PLAT_EZNPS 10 - #error "Incorrect ctop.h include" 11 - #endif 12 - 13 - #include <linux/bits.h> 14 - #include <linux/types.h> 15 - #include <soc/nps/common.h> 16 - 17 - /* core auxiliary registers */ 18 - #ifdef __ASSEMBLY__ 19 - #define CTOP_AUX_BASE (-0x800) 20 - #else 21 - #define CTOP_AUX_BASE 0xFFFFF800 22 - #endif 23 - 24 - #define CTOP_AUX_GLOBAL_ID (CTOP_AUX_BASE + 0x000) 25 - #define CTOP_AUX_CLUSTER_ID (CTOP_AUX_BASE + 0x004) 26 - #define CTOP_AUX_CORE_ID (CTOP_AUX_BASE + 0x008) 27 - #define CTOP_AUX_THREAD_ID (CTOP_AUX_BASE + 0x00C) 28 - #define CTOP_AUX_LOGIC_GLOBAL_ID (CTOP_AUX_BASE + 0x010) 29 - #define CTOP_AUX_LOGIC_CLUSTER_ID (CTOP_AUX_BASE + 0x014) 30 - #define CTOP_AUX_LOGIC_CORE_ID (CTOP_AUX_BASE + 0x018) 31 - #define CTOP_AUX_MT_CTRL (CTOP_AUX_BASE + 0x020) 32 - #define CTOP_AUX_HW_COMPLY (CTOP_AUX_BASE + 0x024) 33 - #define CTOP_AUX_DPC (CTOP_AUX_BASE + 0x02C) 34 - #define CTOP_AUX_LPC (CTOP_AUX_BASE + 0x030) 35 - #define CTOP_AUX_EFLAGS (CTOP_AUX_BASE + 0x080) 36 - #define CTOP_AUX_GPA1 (CTOP_AUX_BASE + 0x08C) 37 - #define CTOP_AUX_UDMC (CTOP_AUX_BASE + 0x300) 38 - 39 - /* EZchip core instructions */ 40 - #define CTOP_INST_HWSCHD_WFT_IE12 0x3E6F7344 41 - #define CTOP_INST_HWSCHD_OFF_R4 0x3C6F00BF 42 - #define CTOP_INST_HWSCHD_RESTORE_R4 0x3E6F7103 43 - #define CTOP_INST_SCHD_RW 0x3E6F7004 44 - #define CTOP_INST_SCHD_RD 0x3E6F7084 45 - #define CTOP_INST_ASRI_0_R3 0x3B56003E 46 - #define CTOP_INST_XEX_DI_R2_R2_R3 0x4A664C00 47 - #define CTOP_INST_EXC_DI_R2_R2_R3 0x4A664C01 48 - #define CTOP_INST_AADD_DI_R2_R2_R3 0x4A664C02 49 - #define CTOP_INST_AAND_DI_R2_R2_R3 0x4A664C04 50 - #define CTOP_INST_AOR_DI_R2_R2_R3 0x4A664C05 51 - #define CTOP_INST_AXOR_DI_R2_R2_R3 0x4A664C06 52 - 53 - /* Do not use D$ for address in 2G-3G */ 54 - #define HW_COMPLY_KRN_NOT_D_CACHED BIT(28) 55 - 56 - #define NPS_MSU_EN_CFG 0x80 57 - #define NPS_CRG_BLKID 0x480 58 - #define NPS_CRG_SYNC_BIT BIT(0) 59 - #define NPS_GIM_BLKID 0x5C0 60 - 61 - /* GIM registers and fields*/ 62 - #define NPS_GIM_UART_LINE BIT(7) 63 - #define NPS_GIM_DBG_LAN_EAST_TX_DONE_LINE BIT(10) 64 - #define NPS_GIM_DBG_LAN_EAST_RX_RDY_LINE BIT(11) 65 - #define NPS_GIM_DBG_LAN_WEST_TX_DONE_LINE BIT(25) 66 - #define NPS_GIM_DBG_LAN_WEST_RX_RDY_LINE BIT(26) 67 - 68 - #ifndef __ASSEMBLY__ 69 - /* Functional registers definition */ 70 - struct nps_host_reg_mtm_cfg { 71 - union { 72 - struct { 73 - u32 gen:1, gdis:1, clk_gate_dis:1, asb:1, 74 - __reserved:9, nat:3, ten:16; 75 - }; 76 - u32 value; 77 - }; 78 - }; 79 - 80 - struct nps_host_reg_mtm_cpu_cfg { 81 - union { 82 - struct { 83 - u32 csa:22, dmsid:6, __reserved:3, cs:1; 84 - }; 85 - u32 value; 86 - }; 87 - }; 88 - 89 - struct nps_host_reg_thr_init { 90 - union { 91 - struct { 92 - u32 str:1, __reserved:27, thr_id:4; 93 - }; 94 - u32 value; 95 - }; 96 - }; 97 - 98 - struct nps_host_reg_thr_init_sts { 99 - union { 100 - struct { 101 - u32 bsy:1, err:1, __reserved:26, thr_id:4; 102 - }; 103 - u32 value; 104 - }; 105 - }; 106 - 107 - struct nps_host_reg_msu_en_cfg { 108 - union { 109 - struct { 110 - u32 __reserved1:11, 111 - rtc_en:1, ipc_en:1, gim_1_en:1, 112 - gim_0_en:1, ipi_en:1, buff_e_rls_bmuw:1, 113 - buff_e_alc_bmuw:1, buff_i_rls_bmuw:1, buff_i_alc_bmuw:1, 114 - buff_e_rls_bmue:1, buff_e_alc_bmue:1, buff_i_rls_bmue:1, 115 - buff_i_alc_bmue:1, __reserved2:1, buff_e_pre_en:1, 116 - buff_i_pre_en:1, pmuw_ja_en:1, pmue_ja_en:1, 117 - pmuw_nj_en:1, pmue_nj_en:1, msu_en:1; 118 - }; 119 - u32 value; 120 - }; 121 - }; 122 - 123 - struct nps_host_reg_gim_p_int_dst { 124 - union { 125 - struct { 126 - u32 int_out_en:1, __reserved1:4, 127 - is:1, intm:2, __reserved2:4, 128 - nid:4, __reserved3:4, cid:4, 129 - __reserved4:4, tid:4; 130 - }; 131 - u32 value; 132 - }; 133 - }; 134 - 135 - /* AUX registers definition */ 136 - struct nps_host_reg_aux_dpc { 137 - union { 138 - struct { 139 - u32 ien:1, men:1, hen:1, reserved:29; 140 - }; 141 - u32 value; 142 - }; 143 - }; 144 - 145 - struct nps_host_reg_aux_udmc { 146 - union { 147 - struct { 148 - u32 dcp:1, cme:1, __reserved:19, nat:3, 149 - __reserved2:5, dcas:3; 150 - }; 151 - u32 value; 152 - }; 153 - }; 154 - 155 - struct nps_host_reg_aux_mt_ctrl { 156 - union { 157 - struct { 158 - u32 mten:1, hsen:1, scd:1, sten:1, 159 - st_cnt:8, __reserved:8, 160 - hs_cnt:8, __reserved1:4; 161 - }; 162 - u32 value; 163 - }; 164 - }; 165 - 166 - struct nps_host_reg_aux_hw_comply { 167 - union { 168 - struct { 169 - u32 me:1, le:1, te:1, knc:1, __reserved:28; 170 - }; 171 - u32 value; 172 - }; 173 - }; 174 - 175 - struct nps_host_reg_aux_lpc { 176 - union { 177 - struct { 178 - u32 mep:1, __reserved:31; 179 - }; 180 - u32 value; 181 - }; 182 - }; 183 - 184 - /* CRG registers */ 185 - #define REG_GEN_PURP_0 nps_host_reg_non_cl(NPS_CRG_BLKID, 0x1BF) 186 - 187 - /* GIM registers */ 188 - #define REG_GIM_P_INT_EN_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x100) 189 - #define REG_GIM_P_INT_POL_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x110) 190 - #define REG_GIM_P_INT_SENS_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x114) 191 - #define REG_GIM_P_INT_BLK_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x118) 192 - #define REG_GIM_P_INT_DST_10 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x13A) 193 - #define REG_GIM_P_INT_DST_11 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x13B) 194 - #define REG_GIM_P_INT_DST_25 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x149) 195 - #define REG_GIM_P_INT_DST_26 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x14A) 196 - 197 - #else 198 - 199 - .macro GET_CPU_ID reg 200 - lr \reg, [CTOP_AUX_LOGIC_GLOBAL_ID] 201 - #ifndef CONFIG_EZNPS_MTM_EXT 202 - lsr \reg, \reg, 4 203 - #endif 204 - .endm 205 - 206 - #endif /* __ASSEMBLY__ */ 207 - 208 - #endif /* _PLAT_EZNPS_CTOP_H */
-49
arch/arc/plat-eznps/include/plat/mtm.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0-only */ 2 - /* 3 - * Copyright(c) 2015 EZchip Technologies. 4 - */ 5 - 6 - #ifndef _PLAT_EZNPS_MTM_H 7 - #define _PLAT_EZNPS_MTM_H 8 - 9 - #include <plat/ctop.h> 10 - 11 - static inline void *nps_mtm_reg_addr(u32 cpu, u32 reg) 12 - { 13 - struct global_id gid; 14 - u32 core, blkid; 15 - 16 - gid.value = cpu; 17 - core = gid.core; 18 - blkid = (((core & 0x0C) << 2) | (core & 0x03)); 19 - 20 - return nps_host_reg(cpu, blkid, reg); 21 - } 22 - 23 - #ifdef CONFIG_EZNPS_MTM_EXT 24 - #define NPS_CPU_TO_THREAD_NUM(cpu) \ 25 - ({ struct global_id gid; gid.value = cpu; gid.thread; }) 26 - 27 - /* MTM registers */ 28 - #define MTM_CFG(cpu) nps_mtm_reg_addr(cpu, 0x81) 29 - #define MTM_THR_INIT(cpu) nps_mtm_reg_addr(cpu, 0x92) 30 - #define MTM_THR_INIT_STS(cpu) nps_mtm_reg_addr(cpu, 0x93) 31 - 32 - #define get_thread(map) map.thread 33 - #define eznps_max_cpus 4096 34 - #define eznps_cpus_per_cluster 256 35 - 36 - void mtm_enable_core(unsigned int cpu); 37 - int mtm_enable_thread(int cpu); 38 - #else /* !CONFIG_EZNPS_MTM_EXT */ 39 - 40 - #define get_thread(map) 0 41 - #define eznps_max_cpus 256 42 - #define eznps_cpus_per_cluster 16 43 - #define mtm_enable_core(cpu) 44 - #define mtm_enable_thread(cpu) 1 45 - #define NPS_CPU_TO_THREAD_NUM(cpu) 0 46 - 47 - #endif /* CONFIG_EZNPS_MTM_EXT */ 48 - 49 - #endif /* _PLAT_EZNPS_MTM_H */
-15
arch/arc/plat-eznps/include/plat/smp.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0-only */ 2 - /* 3 - * Copyright(c) 2015 EZchip Technologies. 4 - */ 5 - 6 - #ifndef __PLAT_EZNPS_SMP_H 7 - #define __PLAT_EZNPS_SMP_H 8 - 9 - #ifdef CONFIG_SMP 10 - 11 - extern void res_service(void); 12 - 13 - #endif /* CONFIG_SMP */ 14 - 15 - #endif
-166
arch/arc/plat-eznps/mtm.c
··· 1 - // SPDX-License-Identifier: GPL-2.0-only 2 - /* 3 - * Copyright(c) 2015 EZchip Technologies. 4 - */ 5 - 6 - #include <linux/smp.h> 7 - #include <linux/init.h> 8 - #include <linux/kernel.h> 9 - #include <linux/io.h> 10 - #include <linux/log2.h> 11 - #include <asm/arcregs.h> 12 - #include <plat/mtm.h> 13 - #include <plat/smp.h> 14 - 15 - #define MT_HS_CNT_MIN 0x01 16 - #define MT_HS_CNT_MAX 0xFF 17 - #define MT_CTRL_ST_CNT 0xF 18 - #define NPS_NUM_HW_THREADS 0x10 19 - 20 - static int mtm_hs_ctr = MT_HS_CNT_MAX; 21 - 22 - #ifdef CONFIG_EZNPS_MEM_ERROR_ALIGN 23 - int do_memory_error(unsigned long address, struct pt_regs *regs) 24 - { 25 - die("Invalid Mem Access", regs, address); 26 - 27 - return 1; 28 - } 29 - #endif 30 - 31 - static void mtm_init_nat(int cpu) 32 - { 33 - struct nps_host_reg_mtm_cfg mtm_cfg; 34 - struct nps_host_reg_aux_udmc udmc; 35 - int log_nat, nat = 0, i, t; 36 - 37 - /* Iterate core threads and update nat */ 38 - for (i = 0, t = cpu; i < NPS_NUM_HW_THREADS; i++, t++) 39 - nat += test_bit(t, cpumask_bits(cpu_possible_mask)); 40 - 41 - log_nat = ilog2(nat); 42 - 43 - udmc.value = read_aux_reg(CTOP_AUX_UDMC); 44 - udmc.nat = log_nat; 45 - write_aux_reg(CTOP_AUX_UDMC, udmc.value); 46 - 47 - mtm_cfg.value = ioread32be(MTM_CFG(cpu)); 48 - mtm_cfg.nat = log_nat; 49 - iowrite32be(mtm_cfg.value, MTM_CFG(cpu)); 50 - } 51 - 52 - static void mtm_init_thread(int cpu) 53 - { 54 - int i, tries = 5; 55 - struct nps_host_reg_thr_init thr_init; 56 - struct nps_host_reg_thr_init_sts thr_init_sts; 57 - 58 - /* Set thread init register */ 59 - thr_init.value = 0; 60 - iowrite32be(thr_init.value, MTM_THR_INIT(cpu)); 61 - thr_init.thr_id = NPS_CPU_TO_THREAD_NUM(cpu); 62 - thr_init.str = 1; 63 - iowrite32be(thr_init.value, MTM_THR_INIT(cpu)); 64 - 65 - /* Poll till thread init is done */ 66 - for (i = 0; i < tries; i++) { 67 - thr_init_sts.value = ioread32be(MTM_THR_INIT_STS(cpu)); 68 - if (thr_init_sts.thr_id == thr_init.thr_id) { 69 - if (thr_init_sts.bsy) 70 - continue; 71 - else if (thr_init_sts.err) 72 - pr_warn("Failed to thread init cpu %u\n", cpu); 73 - break; 74 - } 75 - 76 - pr_warn("Wrong thread id in thread init for cpu %u\n", cpu); 77 - break; 78 - } 79 - 80 - if (i == tries) 81 - pr_warn("Got thread init timeout for cpu %u\n", cpu); 82 - } 83 - 84 - int mtm_enable_thread(int cpu) 85 - { 86 - struct nps_host_reg_mtm_cfg mtm_cfg; 87 - 88 - if (NPS_CPU_TO_THREAD_NUM(cpu) == 0) 89 - return 1; 90 - 91 - /* Enable thread in mtm */ 92 - mtm_cfg.value = ioread32be(MTM_CFG(cpu)); 93 - mtm_cfg.ten |= (1 << (NPS_CPU_TO_THREAD_NUM(cpu))); 94 - iowrite32be(mtm_cfg.value, MTM_CFG(cpu)); 95 - 96 - return 0; 97 - } 98 - 99 - void mtm_enable_core(unsigned int cpu) 100 - { 101 - int i; 102 - struct nps_host_reg_aux_mt_ctrl mt_ctrl; 103 - struct nps_host_reg_mtm_cfg mtm_cfg; 104 - struct nps_host_reg_aux_dpc dpc; 105 - 106 - /* 107 - * Initializing dpc register in each CPU. 108 - * Overwriting the init value of the DPC 109 - * register so that CMEM and FMT virtual address 110 - * spaces are accessible, and Data Plane HW 111 - * facilities are enabled. 112 - */ 113 - dpc.ien = 1; 114 - dpc.men = 1; 115 - write_aux_reg(CTOP_AUX_DPC, dpc.value); 116 - 117 - if (NPS_CPU_TO_THREAD_NUM(cpu) != 0) 118 - return; 119 - 120 - /* Initialize Number of Active Threads */ 121 - mtm_init_nat(cpu); 122 - 123 - /* Initialize mtm_cfg */ 124 - mtm_cfg.value = ioread32be(MTM_CFG(cpu)); 125 - mtm_cfg.ten = 1; 126 - iowrite32be(mtm_cfg.value, MTM_CFG(cpu)); 127 - 128 - /* Initialize all other threads in core */ 129 - for (i = 1; i < NPS_NUM_HW_THREADS; i++) 130 - mtm_init_thread(cpu + i); 131 - 132 - 133 - /* Enable HW schedule, stall counter, mtm */ 134 - mt_ctrl.value = 0; 135 - mt_ctrl.hsen = 1; 136 - mt_ctrl.hs_cnt = mtm_hs_ctr; 137 - mt_ctrl.mten = 1; 138 - write_aux_reg(CTOP_AUX_MT_CTRL, mt_ctrl.value); 139 - 140 - /* 141 - * HW scheduling mechanism will start working 142 - * Only after call to instruction "schd.rw". 143 - * cpu_relax() calls "schd.rw" instruction. 144 - */ 145 - cpu_relax(); 146 - } 147 - 148 - /* Verify and set the value of the mtm hs counter */ 149 - static int __init set_mtm_hs_ctr(char *ctr_str) 150 - { 151 - int hs_ctr; 152 - int ret; 153 - 154 - ret = kstrtoint(ctr_str, 0, &hs_ctr); 155 - 156 - if (ret || hs_ctr > MT_HS_CNT_MAX || hs_ctr < MT_HS_CNT_MIN) { 157 - pr_err("** Invalid @nps_mtm_hs_ctr [%d] needs to be [%d:%d] (incl)\n", 158 - hs_ctr, MT_HS_CNT_MIN, MT_HS_CNT_MAX); 159 - return -EINVAL; 160 - } 161 - 162 - mtm_hs_ctr = hs_ctr; 163 - 164 - return 0; 165 - } 166 - early_param("nps_mtm_hs_ctr", set_mtm_hs_ctr);
-91
arch/arc/plat-eznps/platform.c
··· 1 - // SPDX-License-Identifier: GPL-2.0-only 2 - /* 3 - * Copyright(c) 2015 EZchip Technologies. 4 - */ 5 - 6 - #include <linux/init.h> 7 - #include <linux/io.h> 8 - #include <asm/mach_desc.h> 9 - #include <plat/mtm.h> 10 - 11 - static void __init eznps_configure_msu(void) 12 - { 13 - int cpu; 14 - struct nps_host_reg_msu_en_cfg msu_en_cfg = {.value = 0}; 15 - 16 - msu_en_cfg.msu_en = 1; 17 - msu_en_cfg.ipi_en = 1; 18 - msu_en_cfg.gim_0_en = 1; 19 - msu_en_cfg.gim_1_en = 1; 20 - 21 - /* enable IPI and GIM messages on all clusters */ 22 - for (cpu = 0 ; cpu < eznps_max_cpus; cpu += eznps_cpus_per_cluster) 23 - iowrite32be(msu_en_cfg.value, 24 - nps_host_reg(cpu, NPS_MSU_BLKID, NPS_MSU_EN_CFG)); 25 - } 26 - 27 - static void __init eznps_configure_gim(void) 28 - { 29 - u32 reg_value; 30 - u32 gim_int_lines; 31 - struct nps_host_reg_gim_p_int_dst gim_p_int_dst = {.value = 0}; 32 - 33 - gim_int_lines = NPS_GIM_UART_LINE; 34 - gim_int_lines |= NPS_GIM_DBG_LAN_EAST_TX_DONE_LINE; 35 - gim_int_lines |= NPS_GIM_DBG_LAN_EAST_RX_RDY_LINE; 36 - gim_int_lines |= NPS_GIM_DBG_LAN_WEST_TX_DONE_LINE; 37 - gim_int_lines |= NPS_GIM_DBG_LAN_WEST_RX_RDY_LINE; 38 - 39 - /* 40 - * IRQ polarity 41 - * low or high level 42 - * negative or positive edge 43 - */ 44 - reg_value = ioread32be(REG_GIM_P_INT_POL_0); 45 - reg_value &= ~gim_int_lines; 46 - iowrite32be(reg_value, REG_GIM_P_INT_POL_0); 47 - 48 - /* IRQ type level or edge */ 49 - reg_value = ioread32be(REG_GIM_P_INT_SENS_0); 50 - reg_value |= NPS_GIM_DBG_LAN_EAST_TX_DONE_LINE; 51 - reg_value |= NPS_GIM_DBG_LAN_WEST_TX_DONE_LINE; 52 - iowrite32be(reg_value, REG_GIM_P_INT_SENS_0); 53 - 54 - /* 55 - * GIM interrupt select type for 56 - * dbg_lan TX and RX interrupts 57 - * should be type 1 58 - * type 0 = IRQ line 6 59 - * type 1 = IRQ line 7 60 - */ 61 - gim_p_int_dst.is = 1; 62 - iowrite32be(gim_p_int_dst.value, REG_GIM_P_INT_DST_10); 63 - iowrite32be(gim_p_int_dst.value, REG_GIM_P_INT_DST_11); 64 - iowrite32be(gim_p_int_dst.value, REG_GIM_P_INT_DST_25); 65 - iowrite32be(gim_p_int_dst.value, REG_GIM_P_INT_DST_26); 66 - 67 - /* 68 - * CTOP IRQ lines should be defined 69 - * as blocking in GIM 70 - */ 71 - iowrite32be(gim_int_lines, REG_GIM_P_INT_BLK_0); 72 - 73 - /* enable CTOP IRQ lines in GIM */ 74 - iowrite32be(gim_int_lines, REG_GIM_P_INT_EN_0); 75 - } 76 - 77 - static void __init eznps_early_init(void) 78 - { 79 - eznps_configure_msu(); 80 - eznps_configure_gim(); 81 - } 82 - 83 - static const char *eznps_compat[] __initconst = { 84 - "ezchip,arc-nps", 85 - NULL, 86 - }; 87 - 88 - MACHINE_START(NPS, "nps") 89 - .dt_compat = eznps_compat, 90 - .init_early = eznps_early_init, 91 - MACHINE_END
-138
arch/arc/plat-eznps/smp.c
··· 1 - // SPDX-License-Identifier: GPL-2.0-only 2 - /* 3 - * Copyright(c) 2015 EZchip Technologies. 4 - */ 5 - 6 - #include <linux/smp.h> 7 - #include <linux/of_fdt.h> 8 - #include <linux/io.h> 9 - #include <linux/irqdomain.h> 10 - #include <asm/irq.h> 11 - #include <plat/ctop.h> 12 - #include <plat/smp.h> 13 - #include <plat/mtm.h> 14 - 15 - #define NPS_DEFAULT_MSID 0x34 16 - #define NPS_MTM_CPU_CFG 0x90 17 - 18 - static char smp_cpuinfo_buf[128] = {"Extn [EZNPS-SMP]\t: On\n"}; 19 - 20 - /* Get cpu map from device tree */ 21 - static int __init eznps_get_map(const char *name, struct cpumask *cpumask) 22 - { 23 - unsigned long dt_root = of_get_flat_dt_root(); 24 - const char *buf; 25 - 26 - buf = of_get_flat_dt_prop(dt_root, name, NULL); 27 - if (!buf) 28 - return 1; 29 - 30 - cpulist_parse(buf, cpumask); 31 - 32 - return 0; 33 - } 34 - 35 - /* Update board cpu maps */ 36 - static void __init eznps_init_cpumasks(void) 37 - { 38 - struct cpumask cpumask; 39 - 40 - if (eznps_get_map("present-cpus", &cpumask)) { 41 - pr_err("Failed to get present-cpus from dtb"); 42 - return; 43 - } 44 - init_cpu_present(&cpumask); 45 - 46 - if (eznps_get_map("possible-cpus", &cpumask)) { 47 - pr_err("Failed to get possible-cpus from dtb"); 48 - return; 49 - } 50 - init_cpu_possible(&cpumask); 51 - } 52 - 53 - static void eznps_init_core(unsigned int cpu) 54 - { 55 - u32 sync_value; 56 - struct nps_host_reg_aux_hw_comply hw_comply; 57 - struct nps_host_reg_aux_lpc lpc; 58 - 59 - if (NPS_CPU_TO_THREAD_NUM(cpu) != 0) 60 - return; 61 - 62 - hw_comply.value = read_aux_reg(CTOP_AUX_HW_COMPLY); 63 - hw_comply.me = 1; 64 - hw_comply.le = 1; 65 - hw_comply.te = 1; 66 - write_aux_reg(CTOP_AUX_HW_COMPLY, hw_comply.value); 67 - 68 - /* Enable MMU clock */ 69 - lpc.mep = 1; 70 - write_aux_reg(CTOP_AUX_LPC, lpc.value); 71 - 72 - /* Boot CPU only */ 73 - if (!cpu) { 74 - /* Write to general purpose register in CRG */ 75 - sync_value = ioread32be(REG_GEN_PURP_0); 76 - sync_value |= NPS_CRG_SYNC_BIT; 77 - iowrite32be(sync_value, REG_GEN_PURP_0); 78 - } 79 - } 80 - 81 - /* 82 - * Master kick starting another CPU 83 - */ 84 - static void __init eznps_smp_wakeup_cpu(int cpu, unsigned long pc) 85 - { 86 - struct nps_host_reg_mtm_cpu_cfg cpu_cfg; 87 - 88 - if (mtm_enable_thread(cpu) == 0) 89 - return; 90 - 91 - /* set PC, dmsid, and start CPU */ 92 - cpu_cfg.value = (u32)res_service; 93 - cpu_cfg.dmsid = NPS_DEFAULT_MSID; 94 - cpu_cfg.cs = 1; 95 - iowrite32be(cpu_cfg.value, nps_mtm_reg_addr(cpu, NPS_MTM_CPU_CFG)); 96 - } 97 - 98 - static void eznps_ipi_send(int cpu) 99 - { 100 - struct global_id gid; 101 - struct { 102 - union { 103 - struct { 104 - u32 num:8, cluster:8, core:8, thread:8; 105 - }; 106 - u32 value; 107 - }; 108 - } ipi; 109 - 110 - gid.value = cpu; 111 - ipi.thread = get_thread(gid); 112 - ipi.core = gid.core; 113 - ipi.cluster = nps_cluster_logic_to_phys(gid.cluster); 114 - ipi.num = NPS_IPI_IRQ; 115 - 116 - __asm__ __volatile__( 117 - " mov r3, %0\n" 118 - " .word %1\n" 119 - : 120 - : "r"(ipi.value), "i"(CTOP_INST_ASRI_0_R3) 121 - : "r3"); 122 - } 123 - 124 - static void eznps_init_per_cpu(int cpu) 125 - { 126 - smp_ipi_irq_setup(cpu, NPS_IPI_IRQ); 127 - 128 - eznps_init_core(cpu); 129 - mtm_enable_core(cpu); 130 - } 131 - 132 - struct plat_smp_ops plat_smp_ops = { 133 - .info = smp_cpuinfo_buf, 134 - .init_early_smp = eznps_init_cpumasks, 135 - .cpu_kick = eznps_smp_wakeup_cpu, 136 - .ipi_send = eznps_ipi_send, 137 - .init_per_cpu = eznps_init_per_cpu, 138 - };
+1
arch/arc/plat-hsdk/Kconfig
··· 8 8 select ARC_HAS_ACCL_REGS 9 9 select ARC_IRQ_NO_AUTOSAVE 10 10 select CLK_HSDK 11 + select RESET_CONTROLLER 11 12 select RESET_HSDK 12 13 select HAVE_PCI