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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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kernel
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linux
Fix phy_read/write redefinition errors in ucc_geth_phy.c
The local versions of phy_read() and phy_write() in ucc_geth_phy.c conflict
with the prototypes in include/linux/phy.h, so this patch renames them,
moves them to the top of the file (while eliminating the redundant prototype),
and makes them static.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
authored by Timur Tabi and committed by Jeff Garzik 6bf44652 df19b6b0
+66
-68
drivers/net/ucc_geth_phy.c
+66
-68
drivers/net/ucc_geth_phy.c
···
68
static int genmii_config_aneg(struct ugeth_mii_info *mii_info);
69
static int genmii_update_link(struct ugeth_mii_info *mii_info);
70
static int genmii_read_status(struct ugeth_mii_info *mii_info);
71
-
u16 phy_read(struct ugeth_mii_info *mii_info, u16 regnum);
72
-
void phy_write(struct ugeth_mii_info *mii_info, u16 regnum, u16 val);
73
74
/* Write value to the PHY for this device to the register at regnum, */
75
/* waiting until the write is done before it returns. All PHY */
···
207
advertise = mii_info->advertising;
208
209
/* Setup standard advertisement */
210
-
adv = phy_read(mii_info, MII_ADVERTISE);
211
adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
212
if (advertise & ADVERTISED_10baseT_Half)
213
adv |= ADVERTISE_10HALF;
···
217
adv |= ADVERTISE_100HALF;
218
if (advertise & ADVERTISED_100baseT_Full)
219
adv |= ADVERTISE_100FULL;
220
-
phy_write(mii_info, MII_ADVERTISE, adv);
221
}
222
223
static void genmii_setup_forced(struct ugeth_mii_info *mii_info)
···
227
228
ugphy_vdbg("%s: IN", __FUNCTION__);
229
230
-
ctrl = phy_read(mii_info, MII_BMCR);
231
232
ctrl &=
233
~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
···
257
break;
258
}
259
260
-
phy_write(mii_info, MII_BMCR, ctrl);
261
}
262
263
/* Enable and Restart Autonegotiation */
···
267
268
ugphy_vdbg("%s: IN", __FUNCTION__);
269
270
-
ctl = phy_read(mii_info, MII_BMCR);
271
ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
272
-
phy_write(mii_info, MII_BMCR, ctl);
273
}
274
275
static int gbit_config_aneg(struct ugeth_mii_info *mii_info)
···
284
config_genmii_advert(mii_info);
285
advertise = mii_info->advertising;
286
287
-
adv = phy_read(mii_info, MII_1000BASETCONTROL);
288
adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP |
289
MII_1000BASETCONTROL_HALFDUPLEXCAP);
290
if (advertise & SUPPORTED_1000baseT_Half)
291
adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
292
if (advertise & SUPPORTED_1000baseT_Full)
293
adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
294
-
phy_write(mii_info, MII_1000BASETCONTROL, adv);
295
296
/* Start/Restart aneg */
297
genmii_restart_aneg(mii_info);
···
321
ugphy_vdbg("%s: IN", __FUNCTION__);
322
323
/* Do a fake read */
324
-
phy_read(mii_info, MII_BMSR);
325
326
/* Read link and autonegotiation status */
327
-
status = phy_read(mii_info, MII_BMSR);
328
if ((status & BMSR_LSTATUS) == 0)
329
mii_info->link = 0;
330
else
···
352
return err;
353
354
if (mii_info->autoneg) {
355
-
status = phy_read(mii_info, MII_LPA);
356
357
if (status & (LPA_10FULL | LPA_100FULL))
358
mii_info->duplex = DUPLEX_FULL;
···
375
{
376
ugphy_vdbg("%s: IN", __FUNCTION__);
377
378
-
phy_write(mii_info, 0x14, 0x0cd2);
379
-
phy_write(mii_info, MII_BMCR,
380
-
phy_read(mii_info, MII_BMCR) | BMCR_RESET);
381
msleep(4000);
382
383
return 0;
···
390
/* The Marvell PHY has an errata which requires
391
* that certain registers get written in order
392
* to restart autonegotiation */
393
-
phy_write(mii_info, MII_BMCR, BMCR_RESET);
394
395
-
phy_write(mii_info, 0x1d, 0x1f);
396
-
phy_write(mii_info, 0x1e, 0x200c);
397
-
phy_write(mii_info, 0x1d, 0x5);
398
-
phy_write(mii_info, 0x1e, 0);
399
-
phy_write(mii_info, 0x1e, 0x100);
400
401
gbit_config_aneg(mii_info);
402
···
421
* are as set */
422
if (mii_info->autoneg && mii_info->link) {
423
int speed;
424
-
status = phy_read(mii_info, MII_M1011_PHY_SPEC_STATUS);
425
426
/* Get the duplexity */
427
if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX)
···
453
ugphy_vdbg("%s: IN", __FUNCTION__);
454
455
/* Clear the interrupts by reading the reg */
456
-
phy_read(mii_info, MII_M1011_IEVENT);
457
458
return 0;
459
}
···
463
ugphy_vdbg("%s: IN", __FUNCTION__);
464
465
if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
466
-
phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
467
else
468
-
phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
469
470
return 0;
471
}
···
474
{
475
ugphy_vdbg("%s: IN", __FUNCTION__);
476
477
-
phy_write(mii_info, MII_CIS8201_AUX_CONSTAT,
478
MII_CIS8201_AUXCONSTAT_INIT);
479
-
phy_write(mii_info, MII_CIS8201_EXT_CON1, MII_CIS8201_EXTCON1_INIT);
480
481
return 0;
482
}
···
500
if (mii_info->autoneg && mii_info->link) {
501
int speed;
502
503
-
status = phy_read(mii_info, MII_CIS8201_AUX_CONSTAT);
504
if (status & MII_CIS8201_AUXCONSTAT_DUPLEX)
505
mii_info->duplex = DUPLEX_FULL;
506
else
···
528
{
529
ugphy_vdbg("%s: IN", __FUNCTION__);
530
531
-
phy_read(mii_info, MII_CIS8201_ISTAT);
532
533
return 0;
534
}
···
538
ugphy_vdbg("%s: IN", __FUNCTION__);
539
540
if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
541
-
phy_write(mii_info, MII_CIS8201_IMASK, MII_CIS8201_IMASK_MASK);
542
else
543
-
phy_write(mii_info, MII_CIS8201_IMASK, 0);
544
545
return 0;
546
}
···
564
/* If we aren't autonegotiating, assume speeds
565
* are as set */
566
if (mii_info->autoneg && mii_info->link) {
567
-
status = phy_read(mii_info, MII_DM9161_SCSR);
568
if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H))
569
mii_info->speed = SPEED_100;
570
else
···
595
{
596
struct ugeth_mii_info *mii_info = (struct ugeth_mii_info *)data;
597
struct dm9161_private *priv = mii_info->priv;
598
-
u16 status = phy_read(mii_info, MII_BMSR);
599
600
ugphy_vdbg("%s: IN", __FUNCTION__);
601
···
622
/* Reset is not done yet */
623
priv->resetdone = 0;
624
625
-
phy_write(mii_info, MII_BMCR,
626
-
phy_read(mii_info, MII_BMCR) | BMCR_RESET);
627
628
-
phy_write(mii_info, MII_BMCR,
629
-
phy_read(mii_info, MII_BMCR) & ~BMCR_ISOLATE);
630
631
config_genmii_advert(mii_info);
632
/* Start/Restart aneg */
···
657
ugphy_vdbg("%s: IN", __FUNCTION__);
658
659
/* Clear the interrupts by reading the reg */
660
-
phy_read(mii_info, MII_DM9161_INTR);
661
662
663
return 0;
···
668
ugphy_vdbg("%s: IN", __FUNCTION__);
669
670
if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
671
-
phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT);
672
else
673
-
phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP);
674
675
return 0;
676
}
···
741
NULL
742
};
743
744
-
u16 phy_read(struct ugeth_mii_info *mii_info, u16 regnum)
745
-
{
746
-
u16 retval;
747
-
unsigned long flags;
748
-
749
-
ugphy_vdbg("%s: IN", __FUNCTION__);
750
-
751
-
spin_lock_irqsave(&mii_info->mdio_lock, flags);
752
-
retval = mii_info->mdio_read(mii_info->dev, mii_info->mii_id, regnum);
753
-
spin_unlock_irqrestore(&mii_info->mdio_lock, flags);
754
-
755
-
return retval;
756
-
}
757
-
758
-
void phy_write(struct ugeth_mii_info *mii_info, u16 regnum, u16 val)
759
-
{
760
-
unsigned long flags;
761
-
762
-
ugphy_vdbg("%s: IN", __FUNCTION__);
763
-
764
-
spin_lock_irqsave(&mii_info->mdio_lock, flags);
765
-
mii_info->mdio_write(mii_info->dev, mii_info->mii_id, regnum, val);
766
-
spin_unlock_irqrestore(&mii_info->mdio_lock, flags);
767
-
}
768
-
769
/* Use the PHY ID registers to determine what type of PHY is attached
770
* to device dev. return a struct phy_info structure describing that PHY
771
*/
···
755
ugphy_vdbg("%s: IN", __FUNCTION__);
756
757
/* Grab the bits from PHYIR1, and put them in the upper half */
758
-
phy_reg = phy_read(mii_info, MII_PHYSID1);
759
phy_ID = (phy_reg & 0xffff) << 16;
760
761
/* Grab the bits from PHYIR2, and put them in the lower half */
762
-
phy_reg = phy_read(mii_info, MII_PHYSID2);
763
phy_ID |= (phy_reg & 0xffff);
764
765
/* loop through all the known PHY types, and find one that */
···
68
static int genmii_config_aneg(struct ugeth_mii_info *mii_info);
69
static int genmii_update_link(struct ugeth_mii_info *mii_info);
70
static int genmii_read_status(struct ugeth_mii_info *mii_info);
71
+
72
+
static u16 ucc_geth_phy_read(struct ugeth_mii_info *mii_info, u16 regnum)
73
+
{
74
+
u16 retval;
75
+
unsigned long flags;
76
+
77
+
ugphy_vdbg("%s: IN", __FUNCTION__);
78
+
79
+
spin_lock_irqsave(&mii_info->mdio_lock, flags);
80
+
retval = mii_info->mdio_read(mii_info->dev, mii_info->mii_id, regnum);
81
+
spin_unlock_irqrestore(&mii_info->mdio_lock, flags);
82
+
83
+
return retval;
84
+
}
85
+
86
+
static void ucc_geth_phy_write(struct ugeth_mii_info *mii_info, u16 regnum, u16 val)
87
+
{
88
+
unsigned long flags;
89
+
90
+
ugphy_vdbg("%s: IN", __FUNCTION__);
91
+
92
+
spin_lock_irqsave(&mii_info->mdio_lock, flags);
93
+
mii_info->mdio_write(mii_info->dev, mii_info->mii_id, regnum, val);
94
+
spin_unlock_irqrestore(&mii_info->mdio_lock, flags);
95
+
}
96
97
/* Write value to the PHY for this device to the register at regnum, */
98
/* waiting until the write is done before it returns. All PHY */
···
184
advertise = mii_info->advertising;
185
186
/* Setup standard advertisement */
187
+
adv = ucc_geth_phy_read(mii_info, MII_ADVERTISE);
188
adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
189
if (advertise & ADVERTISED_10baseT_Half)
190
adv |= ADVERTISE_10HALF;
···
194
adv |= ADVERTISE_100HALF;
195
if (advertise & ADVERTISED_100baseT_Full)
196
adv |= ADVERTISE_100FULL;
197
+
ucc_geth_phy_write(mii_info, MII_ADVERTISE, adv);
198
}
199
200
static void genmii_setup_forced(struct ugeth_mii_info *mii_info)
···
204
205
ugphy_vdbg("%s: IN", __FUNCTION__);
206
207
+
ctrl = ucc_geth_phy_read(mii_info, MII_BMCR);
208
209
ctrl &=
210
~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
···
234
break;
235
}
236
237
+
ucc_geth_phy_write(mii_info, MII_BMCR, ctrl);
238
}
239
240
/* Enable and Restart Autonegotiation */
···
244
245
ugphy_vdbg("%s: IN", __FUNCTION__);
246
247
+
ctl = ucc_geth_phy_read(mii_info, MII_BMCR);
248
ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
249
+
ucc_geth_phy_write(mii_info, MII_BMCR, ctl);
250
}
251
252
static int gbit_config_aneg(struct ugeth_mii_info *mii_info)
···
261
config_genmii_advert(mii_info);
262
advertise = mii_info->advertising;
263
264
+
adv = ucc_geth_phy_read(mii_info, MII_1000BASETCONTROL);
265
adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP |
266
MII_1000BASETCONTROL_HALFDUPLEXCAP);
267
if (advertise & SUPPORTED_1000baseT_Half)
268
adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
269
if (advertise & SUPPORTED_1000baseT_Full)
270
adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
271
+
ucc_geth_phy_write(mii_info, MII_1000BASETCONTROL, adv);
272
273
/* Start/Restart aneg */
274
genmii_restart_aneg(mii_info);
···
298
ugphy_vdbg("%s: IN", __FUNCTION__);
299
300
/* Do a fake read */
301
+
ucc_geth_phy_read(mii_info, MII_BMSR);
302
303
/* Read link and autonegotiation status */
304
+
status = ucc_geth_phy_read(mii_info, MII_BMSR);
305
if ((status & BMSR_LSTATUS) == 0)
306
mii_info->link = 0;
307
else
···
329
return err;
330
331
if (mii_info->autoneg) {
332
+
status = ucc_geth_phy_read(mii_info, MII_LPA);
333
334
if (status & (LPA_10FULL | LPA_100FULL))
335
mii_info->duplex = DUPLEX_FULL;
···
352
{
353
ugphy_vdbg("%s: IN", __FUNCTION__);
354
355
+
ucc_geth_phy_write(mii_info, 0x14, 0x0cd2);
356
+
ucc_geth_phy_write(mii_info, MII_BMCR,
357
+
ucc_geth_phy_read(mii_info, MII_BMCR) | BMCR_RESET);
358
msleep(4000);
359
360
return 0;
···
367
/* The Marvell PHY has an errata which requires
368
* that certain registers get written in order
369
* to restart autonegotiation */
370
+
ucc_geth_phy_write(mii_info, MII_BMCR, BMCR_RESET);
371
372
+
ucc_geth_phy_write(mii_info, 0x1d, 0x1f);
373
+
ucc_geth_phy_write(mii_info, 0x1e, 0x200c);
374
+
ucc_geth_phy_write(mii_info, 0x1d, 0x5);
375
+
ucc_geth_phy_write(mii_info, 0x1e, 0);
376
+
ucc_geth_phy_write(mii_info, 0x1e, 0x100);
377
378
gbit_config_aneg(mii_info);
379
···
398
* are as set */
399
if (mii_info->autoneg && mii_info->link) {
400
int speed;
401
+
status = ucc_geth_phy_read(mii_info, MII_M1011_PHY_SPEC_STATUS);
402
403
/* Get the duplexity */
404
if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX)
···
430
ugphy_vdbg("%s: IN", __FUNCTION__);
431
432
/* Clear the interrupts by reading the reg */
433
+
ucc_geth_phy_read(mii_info, MII_M1011_IEVENT);
434
435
return 0;
436
}
···
440
ugphy_vdbg("%s: IN", __FUNCTION__);
441
442
if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
443
+
ucc_geth_phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
444
else
445
+
ucc_geth_phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
446
447
return 0;
448
}
···
451
{
452
ugphy_vdbg("%s: IN", __FUNCTION__);
453
454
+
ucc_geth_phy_write(mii_info, MII_CIS8201_AUX_CONSTAT,
455
MII_CIS8201_AUXCONSTAT_INIT);
456
+
ucc_geth_phy_write(mii_info, MII_CIS8201_EXT_CON1, MII_CIS8201_EXTCON1_INIT);
457
458
return 0;
459
}
···
477
if (mii_info->autoneg && mii_info->link) {
478
int speed;
479
480
+
status = ucc_geth_phy_read(mii_info, MII_CIS8201_AUX_CONSTAT);
481
if (status & MII_CIS8201_AUXCONSTAT_DUPLEX)
482
mii_info->duplex = DUPLEX_FULL;
483
else
···
505
{
506
ugphy_vdbg("%s: IN", __FUNCTION__);
507
508
+
ucc_geth_phy_read(mii_info, MII_CIS8201_ISTAT);
509
510
return 0;
511
}
···
515
ugphy_vdbg("%s: IN", __FUNCTION__);
516
517
if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
518
+
ucc_geth_phy_write(mii_info, MII_CIS8201_IMASK, MII_CIS8201_IMASK_MASK);
519
else
520
+
ucc_geth_phy_write(mii_info, MII_CIS8201_IMASK, 0);
521
522
return 0;
523
}
···
541
/* If we aren't autonegotiating, assume speeds
542
* are as set */
543
if (mii_info->autoneg && mii_info->link) {
544
+
status = ucc_geth_phy_read(mii_info, MII_DM9161_SCSR);
545
if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H))
546
mii_info->speed = SPEED_100;
547
else
···
572
{
573
struct ugeth_mii_info *mii_info = (struct ugeth_mii_info *)data;
574
struct dm9161_private *priv = mii_info->priv;
575
+
u16 status = ucc_geth_phy_read(mii_info, MII_BMSR);
576
577
ugphy_vdbg("%s: IN", __FUNCTION__);
578
···
599
/* Reset is not done yet */
600
priv->resetdone = 0;
601
602
+
ucc_geth_phy_write(mii_info, MII_BMCR,
603
+
ucc_geth_phy_read(mii_info, MII_BMCR) | BMCR_RESET);
604
605
+
ucc_geth_phy_write(mii_info, MII_BMCR,
606
+
ucc_geth_phy_read(mii_info, MII_BMCR) & ~BMCR_ISOLATE);
607
608
config_genmii_advert(mii_info);
609
/* Start/Restart aneg */
···
634
ugphy_vdbg("%s: IN", __FUNCTION__);
635
636
/* Clear the interrupts by reading the reg */
637
+
ucc_geth_phy_read(mii_info, MII_DM9161_INTR);
638
639
640
return 0;
···
645
ugphy_vdbg("%s: IN", __FUNCTION__);
646
647
if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
648
+
ucc_geth_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT);
649
else
650
+
ucc_geth_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP);
651
652
return 0;
653
}
···
718
NULL
719
};
720
721
/* Use the PHY ID registers to determine what type of PHY is attached
722
* to device dev. return a struct phy_info structure describing that PHY
723
*/
···
757
ugphy_vdbg("%s: IN", __FUNCTION__);
758
759
/* Grab the bits from PHYIR1, and put them in the upper half */
760
+
phy_reg = ucc_geth_phy_read(mii_info, MII_PHYSID1);
761
phy_ID = (phy_reg & 0xffff) << 16;
762
763
/* Grab the bits from PHYIR2, and put them in the lower half */
764
+
phy_reg = ucc_geth_phy_read(mii_info, MII_PHYSID2);
765
phy_ID |= (phy_reg & 0xffff);
766
767
/* loop through all the known PHY types, and find one that */