commit 6bf446522b246194551cf167f0168792080d6118 · tjh.dev/kernel

tjh.dev / kernel

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Fix phy_read/write redefinition errors in ucc_geth_phy.c

The local versions of phy_read() and phy_write() in ucc_geth_phy.c conflict
with the prototypes in include/linux/phy.h, so this patch renames them,
moves them to the top of the file (while eliminating the redundant prototype),
and makes them static.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>

authored by Timur Tabi and committed by Jeff Garzik 19 years ago 6bf44652 df19b6b0

+66 -68

1 changed file

expand all

unified split

drivers

net

ucc_geth_phy.c

+66 -68

drivers/net/ucc_geth_phy.c

··· 68 68 static int genmii_config_aneg(struct ugeth_mii_info *mii_info); 69 69 static int genmii_update_link(struct ugeth_mii_info *mii_info); 70 70 static int genmii_read_status(struct ugeth_mii_info *mii_info); 71 - u16 phy_read(struct ugeth_mii_info *mii_info, u16 regnum); 72 - void phy_write(struct ugeth_mii_info *mii_info, u16 regnum, u16 val); 71 + 72 + static u16 ucc_geth_phy_read(struct ugeth_mii_info *mii_info, u16 regnum) 73 + { 74 + u16 retval; 75 + unsigned long flags; 76 + 77 + ugphy_vdbg("%s: IN", __FUNCTION__); 78 + 79 + spin_lock_irqsave(&mii_info->mdio_lock, flags); 80 + retval = mii_info->mdio_read(mii_info->dev, mii_info->mii_id, regnum); 81 + spin_unlock_irqrestore(&mii_info->mdio_lock, flags); 82 + 83 + return retval; 84 + } 85 + 86 + static void ucc_geth_phy_write(struct ugeth_mii_info *mii_info, u16 regnum, u16 val) 87 + { 88 + unsigned long flags; 89 + 90 + ugphy_vdbg("%s: IN", __FUNCTION__); 91 + 92 + spin_lock_irqsave(&mii_info->mdio_lock, flags); 93 + mii_info->mdio_write(mii_info->dev, mii_info->mii_id, regnum, val); 94 + spin_unlock_irqrestore(&mii_info->mdio_lock, flags); 95 + } 73 96 74 97 /* Write value to the PHY for this device to the register at regnum, */ 75 98 /* waiting until the write is done before it returns. All PHY */ ··· 207 184 advertise = mii_info->advertising; 208 185 209 186 /* Setup standard advertisement */ 210 - adv = phy_read(mii_info, MII_ADVERTISE); 187 + adv = ucc_geth_phy_read(mii_info, MII_ADVERTISE); 211 188 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4); 212 189 if (advertise & ADVERTISED_10baseT_Half) 213 190 adv |= ADVERTISE_10HALF; ··· 217 194 adv |= ADVERTISE_100HALF; 218 195 if (advertise & ADVERTISED_100baseT_Full) 219 196 adv |= ADVERTISE_100FULL; 220 - phy_write(mii_info, MII_ADVERTISE, adv); 197 + ucc_geth_phy_write(mii_info, MII_ADVERTISE, adv); 221 198 } 222 199 223 200 static void genmii_setup_forced(struct ugeth_mii_info *mii_info) ··· 227 204 228 205 ugphy_vdbg("%s: IN", __FUNCTION__); 229 206 230 - ctrl = phy_read(mii_info, MII_BMCR); 207 + ctrl = ucc_geth_phy_read(mii_info, MII_BMCR); 231 208 232 209 ctrl &= 233 210 ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE); ··· 257 234 break; 258 235 } 259 236 260 - phy_write(mii_info, MII_BMCR, ctrl); 237 + ucc_geth_phy_write(mii_info, MII_BMCR, ctrl); 261 238 } 262 239 263 240 /* Enable and Restart Autonegotiation */ ··· 267 244 268 245 ugphy_vdbg("%s: IN", __FUNCTION__); 269 246 270 - ctl = phy_read(mii_info, MII_BMCR); 247 + ctl = ucc_geth_phy_read(mii_info, MII_BMCR); 271 248 ctl |= (BMCR_ANENABLE | BMCR_ANRESTART); 272 - phy_write(mii_info, MII_BMCR, ctl); 249 + ucc_geth_phy_write(mii_info, MII_BMCR, ctl); 273 250 } 274 251 275 252 static int gbit_config_aneg(struct ugeth_mii_info *mii_info) ··· 284 261 config_genmii_advert(mii_info); 285 262 advertise = mii_info->advertising; 286 263 287 - adv = phy_read(mii_info, MII_1000BASETCONTROL); 264 + adv = ucc_geth_phy_read(mii_info, MII_1000BASETCONTROL); 288 265 adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP | 289 266 MII_1000BASETCONTROL_HALFDUPLEXCAP); 290 267 if (advertise & SUPPORTED_1000baseT_Half) 291 268 adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP; 292 269 if (advertise & SUPPORTED_1000baseT_Full) 293 270 adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP; 294 - phy_write(mii_info, MII_1000BASETCONTROL, adv); 271 + ucc_geth_phy_write(mii_info, MII_1000BASETCONTROL, adv); 295 272 296 273 /* Start/Restart aneg */ 297 274 genmii_restart_aneg(mii_info); ··· 321 298 ugphy_vdbg("%s: IN", __FUNCTION__); 322 299 323 300 /* Do a fake read */ 324 - phy_read(mii_info, MII_BMSR); 301 + ucc_geth_phy_read(mii_info, MII_BMSR); 325 302 326 303 /* Read link and autonegotiation status */ 327 - status = phy_read(mii_info, MII_BMSR); 304 + status = ucc_geth_phy_read(mii_info, MII_BMSR); 328 305 if ((status & BMSR_LSTATUS) == 0) 329 306 mii_info->link = 0; 330 307 else ··· 352 329 return err; 353 330 354 331 if (mii_info->autoneg) { 355 - status = phy_read(mii_info, MII_LPA); 332 + status = ucc_geth_phy_read(mii_info, MII_LPA); 356 333 357 334 if (status & (LPA_10FULL | LPA_100FULL)) 358 335 mii_info->duplex = DUPLEX_FULL; ··· 375 352 { 376 353 ugphy_vdbg("%s: IN", __FUNCTION__); 377 354 378 - phy_write(mii_info, 0x14, 0x0cd2); 379 - phy_write(mii_info, MII_BMCR, 380 - phy_read(mii_info, MII_BMCR) | BMCR_RESET); 355 + ucc_geth_phy_write(mii_info, 0x14, 0x0cd2); 356 + ucc_geth_phy_write(mii_info, MII_BMCR, 357 + ucc_geth_phy_read(mii_info, MII_BMCR) | BMCR_RESET); 381 358 msleep(4000); 382 359 383 360 return 0; ··· 390 367 /* The Marvell PHY has an errata which requires 391 368 * that certain registers get written in order 392 369 * to restart autonegotiation */ 393 - phy_write(mii_info, MII_BMCR, BMCR_RESET); 370 + ucc_geth_phy_write(mii_info, MII_BMCR, BMCR_RESET); 394 371 395 - phy_write(mii_info, 0x1d, 0x1f); 396 - phy_write(mii_info, 0x1e, 0x200c); 397 - phy_write(mii_info, 0x1d, 0x5); 398 - phy_write(mii_info, 0x1e, 0); 399 - phy_write(mii_info, 0x1e, 0x100); 372 + ucc_geth_phy_write(mii_info, 0x1d, 0x1f); 373 + ucc_geth_phy_write(mii_info, 0x1e, 0x200c); 374 + ucc_geth_phy_write(mii_info, 0x1d, 0x5); 375 + ucc_geth_phy_write(mii_info, 0x1e, 0); 376 + ucc_geth_phy_write(mii_info, 0x1e, 0x100); 400 377 401 378 gbit_config_aneg(mii_info); 402 379 ··· 421 398 * are as set */ 422 399 if (mii_info->autoneg && mii_info->link) { 423 400 int speed; 424 - status = phy_read(mii_info, MII_M1011_PHY_SPEC_STATUS); 401 + status = ucc_geth_phy_read(mii_info, MII_M1011_PHY_SPEC_STATUS); 425 402 426 403 /* Get the duplexity */ 427 404 if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX) ··· 453 430 ugphy_vdbg("%s: IN", __FUNCTION__); 454 431 455 432 /* Clear the interrupts by reading the reg */ 456 - phy_read(mii_info, MII_M1011_IEVENT); 433 + ucc_geth_phy_read(mii_info, MII_M1011_IEVENT); 457 434 458 435 return 0; 459 436 } ··· 463 440 ugphy_vdbg("%s: IN", __FUNCTION__); 464 441 465 442 if (mii_info->interrupts == MII_INTERRUPT_ENABLED) 466 - phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT); 443 + ucc_geth_phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT); 467 444 else 468 - phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR); 445 + ucc_geth_phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR); 469 446 470 447 return 0; 471 448 } ··· 474 451 { 475 452 ugphy_vdbg("%s: IN", __FUNCTION__); 476 453 477 - phy_write(mii_info, MII_CIS8201_AUX_CONSTAT, 454 + ucc_geth_phy_write(mii_info, MII_CIS8201_AUX_CONSTAT, 478 455 MII_CIS8201_AUXCONSTAT_INIT); 479 - phy_write(mii_info, MII_CIS8201_EXT_CON1, MII_CIS8201_EXTCON1_INIT); 456 + ucc_geth_phy_write(mii_info, MII_CIS8201_EXT_CON1, MII_CIS8201_EXTCON1_INIT); 480 457 481 458 return 0; 482 459 } ··· 500 477 if (mii_info->autoneg && mii_info->link) { 501 478 int speed; 502 479 503 - status = phy_read(mii_info, MII_CIS8201_AUX_CONSTAT); 480 + status = ucc_geth_phy_read(mii_info, MII_CIS8201_AUX_CONSTAT); 504 481 if (status & MII_CIS8201_AUXCONSTAT_DUPLEX) 505 482 mii_info->duplex = DUPLEX_FULL; 506 483 else ··· 528 505 { 529 506 ugphy_vdbg("%s: IN", __FUNCTION__); 530 507 531 - phy_read(mii_info, MII_CIS8201_ISTAT); 508 + ucc_geth_phy_read(mii_info, MII_CIS8201_ISTAT); 532 509 533 510 return 0; 534 511 } ··· 538 515 ugphy_vdbg("%s: IN", __FUNCTION__); 539 516 540 517 if (mii_info->interrupts == MII_INTERRUPT_ENABLED) 541 - phy_write(mii_info, MII_CIS8201_IMASK, MII_CIS8201_IMASK_MASK); 518 + ucc_geth_phy_write(mii_info, MII_CIS8201_IMASK, MII_CIS8201_IMASK_MASK); 542 519 else 543 - phy_write(mii_info, MII_CIS8201_IMASK, 0); 520 + ucc_geth_phy_write(mii_info, MII_CIS8201_IMASK, 0); 544 521 545 522 return 0; 546 523 } ··· 564 541 /* If we aren't autonegotiating, assume speeds 565 542 * are as set */ 566 543 if (mii_info->autoneg && mii_info->link) { 567 - status = phy_read(mii_info, MII_DM9161_SCSR); 544 + status = ucc_geth_phy_read(mii_info, MII_DM9161_SCSR); 568 545 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H)) 569 546 mii_info->speed = SPEED_100; 570 547 else ··· 595 572 { 596 573 struct ugeth_mii_info *mii_info = (struct ugeth_mii_info *)data; 597 574 struct dm9161_private *priv = mii_info->priv; 598 - u16 status = phy_read(mii_info, MII_BMSR); 575 + u16 status = ucc_geth_phy_read(mii_info, MII_BMSR); 599 576 600 577 ugphy_vdbg("%s: IN", __FUNCTION__); 601 578 ··· 622 599 /* Reset is not done yet */ 623 600 priv->resetdone = 0; 624 601 625 - phy_write(mii_info, MII_BMCR, 626 - phy_read(mii_info, MII_BMCR) | BMCR_RESET); 602 + ucc_geth_phy_write(mii_info, MII_BMCR, 603 + ucc_geth_phy_read(mii_info, MII_BMCR) | BMCR_RESET); 627 604 628 - phy_write(mii_info, MII_BMCR, 629 - phy_read(mii_info, MII_BMCR) & ~BMCR_ISOLATE); 605 + ucc_geth_phy_write(mii_info, MII_BMCR, 606 + ucc_geth_phy_read(mii_info, MII_BMCR) & ~BMCR_ISOLATE); 630 607 631 608 config_genmii_advert(mii_info); 632 609 /* Start/Restart aneg */ ··· 657 634 ugphy_vdbg("%s: IN", __FUNCTION__); 658 635 659 636 /* Clear the interrupts by reading the reg */ 660 - phy_read(mii_info, MII_DM9161_INTR); 637 + ucc_geth_phy_read(mii_info, MII_DM9161_INTR); 661 638 662 639 663 640 return 0; ··· 668 645 ugphy_vdbg("%s: IN", __FUNCTION__); 669 646 670 647 if (mii_info->interrupts == MII_INTERRUPT_ENABLED) 671 - phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT); 648 + ucc_geth_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT); 672 649 else 673 - phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP); 650 + ucc_geth_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP); 674 651 675 652 return 0; 676 653 } ··· 741 718 NULL 742 719 }; 743 720 744 - u16 phy_read(struct ugeth_mii_info *mii_info, u16 regnum) 745 - { 746 - u16 retval; 747 - unsigned long flags; 748 - 749 - ugphy_vdbg("%s: IN", __FUNCTION__); 750 - 751 - spin_lock_irqsave(&mii_info->mdio_lock, flags); 752 - retval = mii_info->mdio_read(mii_info->dev, mii_info->mii_id, regnum); 753 - spin_unlock_irqrestore(&mii_info->mdio_lock, flags); 754 - 755 - return retval; 756 - } 757 - 758 - void phy_write(struct ugeth_mii_info *mii_info, u16 regnum, u16 val) 759 - { 760 - unsigned long flags; 761 - 762 - ugphy_vdbg("%s: IN", __FUNCTION__); 763 - 764 - spin_lock_irqsave(&mii_info->mdio_lock, flags); 765 - mii_info->mdio_write(mii_info->dev, mii_info->mii_id, regnum, val); 766 - spin_unlock_irqrestore(&mii_info->mdio_lock, flags); 767 - } 768 - 769 721 /* Use the PHY ID registers to determine what type of PHY is attached 770 722 * to device dev. return a struct phy_info structure describing that PHY 771 723 */ ··· 755 757 ugphy_vdbg("%s: IN", __FUNCTION__); 756 758 757 759 /* Grab the bits from PHYIR1, and put them in the upper half */ 758 - phy_reg = phy_read(mii_info, MII_PHYSID1); 760 + phy_reg = ucc_geth_phy_read(mii_info, MII_PHYSID1); 759 761 phy_ID = (phy_reg & 0xffff) << 16; 760 762 761 763 /* Grab the bits from PHYIR2, and put them in the lower half */ 762 - phy_reg = phy_read(mii_info, MII_PHYSID2); 764 + phy_reg = ucc_geth_phy_read(mii_info, MII_PHYSID2); 763 765 phy_ID |= (phy_reg & 0xffff); 764 766 765 767 /* loop through all the known PHY types, and find one that */