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dt-bindings: display: amlogic, meson-vpu: convert to yaml
Now that we have the DT validation in place, let's convert the device tree
bindings for the Amlogic Display Controller over to YAML schemas.
The original example has a leftover "dmc" memory cell, that has been
removed in the yaml rewrite.
The port connection table has been dropped in favor of a description
of each port.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20190808085522.21950-3-narmstrong@baylibre.com
+137
-121
-121
Documentation/devicetree/bindings/display/amlogic,meson-vpu.txt
-121
Documentation/devicetree/bindings/display/amlogic,meson-vpu.txt
···
1
-
Amlogic Meson Display Controller
2
-
================================
3
-
4
-
The Amlogic Meson Display controller is composed of several components
5
-
that are going to be documented below:
6
-
7
-
DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
8
-
| vd1 _______ _____________ _________________ | |
9
-
D |-------| |----| | | | | HDMI PLL |
10
-
D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
11
-
R |-------| |----| Processing | | | | |
12
-
| osd2 | | | |---| Enci ----------|----|-----VDAC------|
13
-
R |-------| CSC |----| Scalers | | Encp ----------|----|----HDMI-TX----|
14
-
A | osd1 | | | Blenders | | Encl ----------|----|---------------|
15
-
M |-------|______|----|____________| |________________| | |
16
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___|__________________________________________________________|_______________|
17
-
18
-
19
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VIU: Video Input Unit
20
-
---------------------
21
-
22
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The Video Input Unit is in charge of the pixel scanout from the DDR memory.
23
-
It fetches the frames addresses, stride and parameters from the "Canvas" memory.
24
-
This part is also in charge of the CSC (Colorspace Conversion).
25
-
It can handle 2 OSD Planes and 2 Video Planes.
26
-
27
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VPP: Video Post Processing
28
-
--------------------------
29
-
30
-
The Video Post Processing is in charge of the scaling and blending of the
31
-
various planes into a single pixel stream.
32
-
There is a special "pre-blending" used by the video planes with a dedicated
33
-
scaler and a "post-blending" to merge with the OSD Planes.
34
-
The OSD planes also have a dedicated scaler for one of the OSD.
35
-
36
-
VENC: Video Encoders
37
-
--------------------
38
-
39
-
The VENC is composed of the multiple pixel encoders :
40
-
- ENCI : Interlace Video encoder for CVBS and Interlace HDMI
41
-
- ENCP : Progressive Video Encoder for HDMI
42
-
- ENCL : LCD LVDS Encoder
43
-
The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock
44
-
tree and provides the scanout clock to the VPP and VIU.
45
-
The ENCI is connected to a single VDAC for Composite Output.
46
-
The ENCI and ENCP are connected to an on-chip HDMI Transceiver.
47
-
48
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Device Tree Bindings:
49
-
---------------------
50
-
51
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VPU: Video Processing Unit
52
-
--------------------------
53
-
54
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Required properties:
55
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- compatible: value should be different for each SoC family as :
56
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- GXBB (S905) : "amlogic,meson-gxbb-vpu"
57
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- GXL (S905X, S905D) : "amlogic,meson-gxl-vpu"
58
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- GXM (S912) : "amlogic,meson-gxm-vpu"
59
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followed by the common "amlogic,meson-gx-vpu"
60
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- G12A (S905X2, S905Y2, S905D2) : "amlogic,meson-g12a-vpu"
61
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- reg: base address and size of he following memory-mapped regions :
62
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- vpu
63
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- hhi
64
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- reg-names: should contain the names of the previous memory regions
65
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- interrupts: should contain the VENC Vsync interrupt number
66
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- amlogic,canvas: phandle to canvas provider node as described in the file
67
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../soc/amlogic/amlogic,canvas.txt
68
-
69
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Optional properties:
70
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- power-domains: Optional phandle to associated power domain as described in
71
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the file ../power/power_domain.txt
72
-
73
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Required nodes:
74
-
75
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The connections to the VPU output video ports are modeled using the OF graph
76
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bindings specified in Documentation/devicetree/bindings/graph.txt.
77
-
78
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The following table lists for each supported model the port number
79
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corresponding to each VPU output.
80
-
81
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Port 0 Port 1
82
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-----------------------------------------
83
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S905 (GXBB) CVBS VDAC HDMI-TX
84
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S905X (GXL) CVBS VDAC HDMI-TX
85
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S905D (GXL) CVBS VDAC HDMI-TX
86
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S912 (GXM) CVBS VDAC HDMI-TX
87
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S905X2 (G12A) CVBS VDAC HDMI-TX
88
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S905Y2 (G12A) CVBS VDAC HDMI-TX
89
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S905D2 (G12A) CVBS VDAC HDMI-TX
90
-
91
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Example:
92
-
93
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tv-connector {
94
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compatible = "composite-video-connector";
95
-
96
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port {
97
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tv_connector_in: endpoint {
98
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remote-endpoint = <&cvbs_vdac_out>;
99
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};
100
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};
101
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};
102
-
103
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vpu: vpu@d0100000 {
104
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compatible = "amlogic,meson-gxbb-vpu";
105
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reg = <0x0 0xd0100000 0x0 0x100000>,
106
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<0x0 0xc883c000 0x0 0x1000>,
107
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<0x0 0xc8838000 0x0 0x1000>;
108
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reg-names = "vpu", "hhi", "dmc";
109
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interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
110
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#address-cells = <1>;
111
-
#size-cells = <0>;
112
-
113
-
/* CVBS VDAC output port */
114
-
port@0 {
115
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reg = <0>;
116
-
117
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cvbs_vdac_out: endpoint {
118
-
remote-endpoint = <&tv_connector_in>;
119
-
};
120
-
};
121
-
};
+137
Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
+137
Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
# Copyright 2019 BayLibre, SAS
3
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#"
6
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
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8
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title: Amlogic Meson Display Controller
9
+
10
+
maintainers:
11
+
- Neil Armstrong <narmstrong@baylibre.com>
12
+
13
+
description: |
14
+
The Amlogic Meson Display controller is composed of several components
15
+
that are going to be documented below
16
+
17
+
DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
18
+
| vd1 _______ _____________ _________________ | |
19
+
D |-------| |----| | | | | HDMI PLL |
20
+
D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
21
+
R |-------| |----| Processing | | | | |
22
+
| osd2 | | | |---| Enci ----------|----|-----VDAC------|
23
+
R |-------| CSC |----| Scalers | | Encp ----------|----|----HDMI-TX----|
24
+
A | osd1 | | | Blenders | | Encl ----------|----|---------------|
25
+
M |-------|______|----|____________| |________________| | |
26
+
___|__________________________________________________________|_______________|
27
+
28
+
29
+
VIU: Video Input Unit
30
+
---------------------
31
+
32
+
The Video Input Unit is in charge of the pixel scanout from the DDR memory.
33
+
It fetches the frames addresses, stride and parameters from the "Canvas" memory.
34
+
This part is also in charge of the CSC (Colorspace Conversion).
35
+
It can handle 2 OSD Planes and 2 Video Planes.
36
+
37
+
VPP: Video Post Processing
38
+
--------------------------
39
+
40
+
The Video Post Processing is in charge of the scaling and blending of the
41
+
various planes into a single pixel stream.
42
+
There is a special "pre-blending" used by the video planes with a dedicated
43
+
scaler and a "post-blending" to merge with the OSD Planes.
44
+
The OSD planes also have a dedicated scaler for one of the OSD.
45
+
46
+
VENC: Video Encoders
47
+
--------------------
48
+
49
+
The VENC is composed of the multiple pixel encoders
50
+
- ENCI : Interlace Video encoder for CVBS and Interlace HDMI
51
+
- ENCP : Progressive Video Encoder for HDMI
52
+
- ENCL : LCD LVDS Encoder
53
+
The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock
54
+
tree and provides the scanout clock to the VPP and VIU.
55
+
The ENCI is connected to a single VDAC for Composite Output.
56
+
The ENCI and ENCP are connected to an on-chip HDMI Transceiver.
57
+
58
+
properties:
59
+
compatible:
60
+
oneOf:
61
+
- items:
62
+
- enum:
63
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- amlogic,meson-gxbb-vpu # GXBB (S905)
64
+
- amlogic,meson-gxl-vpu # GXL (S905X, S905D)
65
+
- amlogic,meson-gxm-vpu # GXM (S912)
66
+
- const: amlogic,meson-gx-vpu
67
+
- enum:
68
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- amlogic,meson-g12a-vpu # G12A (S905X2, S905Y2, S905D2)
69
+
70
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reg:
71
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maxItems: 2
72
+
73
+
reg-names:
74
+
items:
75
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- const: vpu
76
+
- const: hhi
77
+
78
+
interrupts:
79
+
maxItems: 1
80
+
81
+
power-domains:
82
+
maxItems: 1
83
+
description: phandle to the associated power domain
84
+
85
+
port@0:
86
+
type: object
87
+
description:
88
+
A port node pointing to the CVBS VDAC port node.
89
+
90
+
port@1:
91
+
type: object
92
+
description:
93
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A port node pointing to the HDMI-TX port node.
94
+
95
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"#address-cells":
96
+
const: 1
97
+
98
+
"#size-cells":
99
+
const: 0
100
+
101
+
required:
102
+
- compatible
103
+
- reg
104
+
- interrupts
105
+
- port@0
106
+
- port@1
107
+
- "#address-cells"
108
+
- "#size-cells"
109
+
110
+
examples:
111
+
- |
112
+
vpu: vpu@d0100000 {
113
+
compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
114
+
reg = <0xd0100000 0x100000>, <0xc883c000 0x1000>;
115
+
reg-names = "vpu", "hhi";
116
+
interrupts = <3>;
117
+
#address-cells = <1>;
118
+
#size-cells = <0>;
119
+
120
+
/* CVBS VDAC output port */
121
+
port@0 {
122
+
reg = <0>;
123
+
124
+
cvbs_vdac_out: endpoint {
125
+
remote-endpoint = <&tv_connector_in>;
126
+
};
127
+
};
128
+
129
+
/* HDMI TX output port */
130
+
port@1 {
131
+
reg = <1>;
132
+
133
+
hdmi_tx_out: endpoint {
134
+
remote-endpoint = <&hdmi_tx_in>;
135
+
};
136
+
};
137
+
};