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dt-bindings: display: amlogic, meson-dw-hdmi: convert to yaml
Now that we have the DT validation in place, let's convert the device tree
bindings for the Amlogic Synopsys DW-HDMI specifics over to YAML schemas.
The original example and usage of clock-names uses a reversed "isfr"
and "iahb" clock-names, the rewritten YAML bindings uses the reversed
instead of fixing the device trees order.
The #sound-dai-cells optional property has been added to match this node
as a sound dai.
The port connection table has been dropped in favor of a description
of each port.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190808085522.21950-2-narmstrong@baylibre.com
+150
-119
-119
Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.txt
-119
Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.txt
···
1
-
Amlogic specific extensions to the Synopsys Designware HDMI Controller
2
-
======================================================================
3
-
4
-
The Amlogic Meson Synopsys Designware Integration is composed of :
5
-
- A Synopsys DesignWare HDMI Controller IP
6
-
- A TOP control block controlling the Clocks and PHY
7
-
- A custom HDMI PHY in order to convert video to TMDS signal
8
-
___________________________________
9
-
| HDMI TOP |<= HPD
10
-
|___________________________________|
11
-
| | |
12
-
| Synopsys HDMI | HDMI PHY |=> TMDS
13
-
| Controller |________________|
14
-
|___________________________________|<=> DDC
15
-
16
-
The HDMI TOP block only supports HPD sensing.
17
-
The Synopsys HDMI Controller interrupt is routed through the
18
-
TOP Block interrupt.
19
-
Communication to the TOP Block and the Synopsys HDMI Controller is done
20
-
via a pair of dedicated addr+read/write registers.
21
-
The HDMI PHY is configured by registers in the HHI register block.
22
-
23
-
Pixel data arrives in 4:4:4 format from the VENC block and the VPU HDMI mux
24
-
selects either the ENCI encoder for the 576i or 480i formats or the ENCP
25
-
encoder for all the other formats including interlaced HD formats.
26
-
27
-
The VENC uses a DVI encoder on top of the ENCI or ENCP encoders to generate
28
-
DVI timings for the HDMI controller.
29
-
30
-
Amlogic Meson GXBB, GXL and GXM SoCs families embeds the Synopsys DesignWare
31
-
HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF
32
-
audio source interfaces.
33
-
34
-
Required properties:
35
-
- compatible: value should be different for each SoC family as :
36
-
- GXBB (S905) : "amlogic,meson-gxbb-dw-hdmi"
37
-
- GXL (S905X, S905D) : "amlogic,meson-gxl-dw-hdmi"
38
-
- GXM (S912) : "amlogic,meson-gxm-dw-hdmi"
39
-
followed by the common "amlogic,meson-gx-dw-hdmi"
40
-
- G12A (S905X2, S905Y2, S905D2) : "amlogic,meson-g12a-dw-hdmi"
41
-
- reg: Physical base address and length of the controller's registers.
42
-
- interrupts: The HDMI interrupt number
43
-
- clocks, clock-names : must have the phandles to the HDMI iahb and isfr clocks,
44
-
and the Amlogic Meson venci clocks as described in
45
-
Documentation/devicetree/bindings/clock/clock-bindings.txt,
46
-
the clocks are soc specific, the clock-names should be "iahb", "isfr", "venci"
47
-
- resets, resets-names: must have the phandles to the HDMI apb, glue and phy
48
-
resets as described in :
49
-
Documentation/devicetree/bindings/reset/reset.txt,
50
-
the reset-names should be "hdmitx_apb", "hdmitx", "hdmitx_phy"
51
-
52
-
Optional properties:
53
-
- hdmi-supply: Optional phandle to an external 5V regulator to power the HDMI
54
-
logic, as described in the file ../regulator/regulator.txt
55
-
56
-
Required nodes:
57
-
58
-
The connections to the HDMI ports are modeled using the OF graph
59
-
bindings specified in Documentation/devicetree/bindings/graph.txt.
60
-
61
-
The following table lists for each supported model the port number
62
-
corresponding to each HDMI output and input.
63
-
64
-
Port 0 Port 1
65
-
-----------------------------------------
66
-
S905 (GXBB) VENC Input TMDS Output
67
-
S905X (GXL) VENC Input TMDS Output
68
-
S905D (GXL) VENC Input TMDS Output
69
-
S912 (GXM) VENC Input TMDS Output
70
-
S905X2 (G12A) VENC Input TMDS Output
71
-
S905Y2 (G12A) VENC Input TMDS Output
72
-
S905D2 (G12A) VENC Input TMDS Output
73
-
74
-
Example:
75
-
76
-
hdmi-connector {
77
-
compatible = "hdmi-connector";
78
-
type = "a";
79
-
80
-
port {
81
-
hdmi_connector_in: endpoint {
82
-
remote-endpoint = <&hdmi_tx_tmds_out>;
83
-
};
84
-
};
85
-
};
86
-
87
-
hdmi_tx: hdmi-tx@c883a000 {
88
-
compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
89
-
reg = <0x0 0xc883a000 0x0 0x1c>;
90
-
interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
91
-
resets = <&reset RESET_HDMITX_CAPB3>,
92
-
<&reset RESET_HDMI_SYSTEM_RESET>,
93
-
<&reset RESET_HDMI_TX>;
94
-
reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
95
-
clocks = <&clkc CLKID_HDMI_PCLK>,
96
-
<&clkc CLKID_CLK81>,
97
-
<&clkc CLKID_GCLK_VENCI_INT0>;
98
-
clock-names = "isfr", "iahb", "venci";
99
-
#address-cells = <1>;
100
-
#size-cells = <0>;
101
-
102
-
/* VPU VENC Input */
103
-
hdmi_tx_venc_port: port@0 {
104
-
reg = <0>;
105
-
106
-
hdmi_tx_in: endpoint {
107
-
remote-endpoint = <&hdmi_tx_out>;
108
-
};
109
-
};
110
-
111
-
/* TMDS Output */
112
-
hdmi_tx_tmds_port: port@1 {
113
-
reg = <1>;
114
-
115
-
hdmi_tx_tmds_out: endpoint {
116
-
remote-endpoint = <&hdmi_connector_in>;
117
-
};
118
-
};
119
-
};
+150
Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml
+150
Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
# Copyright 2019 BayLibre, SAS
3
+
%YAML 1.2
4
+
---
5
+
$id: "http://devicetree.org/schemas/display/amlogic,meson-dw-hdmi.yaml#"
6
+
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
+
8
+
title: Amlogic specific extensions to the Synopsys Designware HDMI Controller
9
+
10
+
maintainers:
11
+
- Neil Armstrong <narmstrong@baylibre.com>
12
+
13
+
description: |
14
+
The Amlogic Meson Synopsys Designware Integration is composed of
15
+
- A Synopsys DesignWare HDMI Controller IP
16
+
- A TOP control block controlling the Clocks and PHY
17
+
- A custom HDMI PHY in order to convert video to TMDS signal
18
+
___________________________________
19
+
| HDMI TOP |<= HPD
20
+
|___________________________________|
21
+
| | |
22
+
| Synopsys HDMI | HDMI PHY |=> TMDS
23
+
| Controller |________________|
24
+
|___________________________________|<=> DDC
25
+
26
+
The HDMI TOP block only supports HPD sensing.
27
+
The Synopsys HDMI Controller interrupt is routed through the
28
+
TOP Block interrupt.
29
+
Communication to the TOP Block and the Synopsys HDMI Controller is done
30
+
via a pair of dedicated addr+read/write registers.
31
+
The HDMI PHY is configured by registers in the HHI register block.
32
+
33
+
Pixel data arrives in "4:4:4" format from the VENC block and the VPU HDMI mux
34
+
selects either the ENCI encoder for the 576i or 480i formats or the ENCP
35
+
encoder for all the other formats including interlaced HD formats.
36
+
37
+
The VENC uses a DVI encoder on top of the ENCI or ENCP encoders to generate
38
+
DVI timings for the HDMI controller.
39
+
40
+
Amlogic Meson GXBB, GXL and GXM SoCs families embeds the Synopsys DesignWare
41
+
HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF
42
+
audio source interfaces.
43
+
44
+
properties:
45
+
compatible:
46
+
oneOf:
47
+
- items:
48
+
- enum:
49
+
- amlogic,meson-gxbb-dw-hdmi # GXBB (S905)
50
+
- amlogic,meson-gxl-dw-hdmi # GXL (S905X, S905D)
51
+
- amlogic,meson-gxm-dw-hdmi # GXM (S912)
52
+
- const: amlogic,meson-gx-dw-hdmi
53
+
- enum:
54
+
- amlogic,meson-g12a-dw-hdmi # G12A (S905X2, S905Y2, S905D2)
55
+
56
+
reg:
57
+
maxItems: 1
58
+
59
+
interrupts:
60
+
maxItems: 1
61
+
62
+
clocks:
63
+
minItems: 3
64
+
65
+
clock-names:
66
+
items:
67
+
- const: isfr
68
+
- const: iahb
69
+
- const: venci
70
+
71
+
resets:
72
+
minItems: 3
73
+
74
+
reset-names:
75
+
items:
76
+
- const: hdmitx_apb
77
+
- const: hdmitx
78
+
- const: hdmitx_phy
79
+
80
+
hdmi-supply:
81
+
description: phandle to an external 5V regulator to power the HDMI logic
82
+
allOf:
83
+
- $ref: /schemas/types.yaml#/definitions/phandle
84
+
85
+
port@0:
86
+
type: object
87
+
description:
88
+
A port node pointing to the VENC Input port node.
89
+
90
+
port@1:
91
+
type: object
92
+
description:
93
+
A port node pointing to the TMDS Output port node.
94
+
95
+
"#address-cells":
96
+
const: 1
97
+
98
+
"#size-cells":
99
+
const: 0
100
+
101
+
"#sound-dai-cells":
102
+
const: 0
103
+
104
+
required:
105
+
- compatible
106
+
- reg
107
+
- interrupts
108
+
- clocks
109
+
- clock-names
110
+
- resets
111
+
- reset-names
112
+
- port@0
113
+
- port@1
114
+
- "#address-cells"
115
+
- "#size-cells"
116
+
117
+
additionalProperties: false
118
+
119
+
examples:
120
+
- |
121
+
hdmi_tx: hdmi-tx@c883a000 {
122
+
compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
123
+
reg = <0xc883a000 0x1c>;
124
+
interrupts = <57>;
125
+
resets = <&reset_apb>, <&reset_hdmitx>, <&reset_hdmitx_phy>;
126
+
reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
127
+
clocks = <&clk_isfr>, <&clk_iahb>, <&clk_venci>;
128
+
clock-names = "isfr", "iahb", "venci";
129
+
#address-cells = <1>;
130
+
#size-cells = <0>;
131
+
132
+
/* VPU VENC Input */
133
+
hdmi_tx_venc_port: port@0 {
134
+
reg = <0>;
135
+
136
+
hdmi_tx_in: endpoint {
137
+
remote-endpoint = <&hdmi_tx_out>;
138
+
};
139
+
};
140
+
141
+
/* TMDS Output */
142
+
hdmi_tx_tmds_port: port@1 {
143
+
reg = <1>;
144
+
145
+
hdmi_tx_tmds_out: endpoint {
146
+
remote-endpoint = <&hdmi_connector_in>;
147
+
};
148
+
};
149
+
};
150
+