Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
Merge branch 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung
* 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: SAMSUNG: Fix on wrong function name for S5PV210 sdhci0
ARM: S5P6442: Fix PLL setting announce message.
ARM: SAMSUNG: Fix build without SDHCI controllers for S3C64XX
ARM: S5PV210: Correct clock register properties
ARM: S5P: Bug fix on external interrupt for S5P SoCs
+1
-1
arch/arm/mach-s5p6442/clock.c
+1
-1
arch/arm/mach-s5p6442/clock.c
+62
-53
arch/arm/mach-s5pv210/clock.c
+62
-53
arch/arm/mach-s5pv210/clock.c
···
183
return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
184
}
185
186
static struct clk clk_sclk_hdmi27m = {
187
.name = "sclk_hdmi27m",
188
.id = -1,
···
411
.id = 0,
412
.parent = &clk_p,
413
.enable = s5pv210_clk_ip3_ctrl,
414
-
.ctrlbit = (1<<4),
415
}, {
416
.name = "i2s_v32",
417
.id = 1,
418
.parent = &clk_p,
419
.enable = s5pv210_clk_ip3_ctrl,
420
-
.ctrlbit = (1<<4),
421
-
}
422
};
423
424
static struct clk init_clocks[] = {
···
434
.id = 0,
435
.parent = &clk_pclk_psys.clk,
436
.enable = s5pv210_clk_ip3_ctrl,
437
-
.ctrlbit = (1<<7),
438
}, {
439
.name = "uart",
440
.id = 1,
441
.parent = &clk_pclk_psys.clk,
442
.enable = s5pv210_clk_ip3_ctrl,
443
-
.ctrlbit = (1<<8),
444
}, {
445
.name = "uart",
446
.id = 2,
447
.parent = &clk_pclk_psys.clk,
448
.enable = s5pv210_clk_ip3_ctrl,
449
-
.ctrlbit = (1<<9),
450
}, {
451
.name = "uart",
452
.id = 3,
453
.parent = &clk_pclk_psys.clk,
454
.enable = s5pv210_clk_ip3_ctrl,
455
-
.ctrlbit = (1<<10),
456
},
457
};
458
···
502
.clk = {
503
.name = "sclk_dac",
504
.id = -1,
505
-
.ctrlbit = (1 << 10),
506
-
.enable = s5pv210_clk_ip1_ctrl,
507
},
508
.sources = &clkset_sclk_dac,
509
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
···
532
.clk = {
533
.name = "sclk_hdmi",
534
.id = -1,
535
-
.enable = s5pv210_clk_ip1_ctrl,
536
-
.ctrlbit = (1 << 11),
537
},
538
.sources = &clkset_sclk_hdmi,
539
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
···
570
.clk = {
571
.name = "sclk_audio",
572
.id = 0,
573
-
.enable = s5pv210_clk_ip3_ctrl,
574
-
.ctrlbit = (1 << 4),
575
},
576
.sources = &clkset_sclk_audio0,
577
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
···
599
.clk = {
600
.name = "sclk_audio",
601
.id = 1,
602
-
.enable = s5pv210_clk_ip3_ctrl,
603
-
.ctrlbit = (1 << 5),
604
},
605
.sources = &clkset_sclk_audio1,
606
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
···
628
.clk = {
629
.name = "sclk_audio",
630
.id = 2,
631
-
.enable = s5pv210_clk_ip3_ctrl,
632
-
.ctrlbit = (1 << 6),
633
},
634
.sources = &clkset_sclk_audio2,
635
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
···
685
.clk = {
686
.name = "uclk1",
687
.id = 0,
688
-
.ctrlbit = (1<<17),
689
-
.enable = s5pv210_clk_ip3_ctrl,
690
},
691
.sources = &clkset_uart,
692
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
···
695
.clk = {
696
.name = "uclk1",
697
.id = 1,
698
-
.enable = s5pv210_clk_ip3_ctrl,
699
-
.ctrlbit = (1 << 18),
700
},
701
.sources = &clkset_uart,
702
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
···
705
.clk = {
706
.name = "uclk1",
707
.id = 2,
708
-
.enable = s5pv210_clk_ip3_ctrl,
709
-
.ctrlbit = (1 << 19),
710
},
711
.sources = &clkset_uart,
712
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
···
715
.clk = {
716
.name = "uclk1",
717
.id = 3,
718
-
.enable = s5pv210_clk_ip3_ctrl,
719
-
.ctrlbit = (1 << 20),
720
},
721
.sources = &clkset_uart,
722
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
···
725
.clk = {
726
.name = "sclk_mixer",
727
.id = -1,
728
-
.enable = s5pv210_clk_ip1_ctrl,
729
-
.ctrlbit = (1 << 9),
730
},
731
.sources = &clkset_sclk_mixer,
732
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
···
743
.clk = {
744
.name = "sclk_fimc",
745
.id = 0,
746
-
.enable = s5pv210_clk_ip0_ctrl,
747
-
.ctrlbit = (1 << 24),
748
},
749
.sources = &clkset_group2,
750
.reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
···
753
.clk = {
754
.name = "sclk_fimc",
755
.id = 1,
756
-
.enable = s5pv210_clk_ip0_ctrl,
757
-
.ctrlbit = (1 << 25),
758
},
759
.sources = &clkset_group2,
760
.reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
···
763
.clk = {
764
.name = "sclk_fimc",
765
.id = 2,
766
-
.enable = s5pv210_clk_ip0_ctrl,
767
-
.ctrlbit = (1 << 26),
768
},
769
.sources = &clkset_group2,
770
.reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
···
773
.clk = {
774
.name = "sclk_cam",
775
.id = 0,
776
},
777
.sources = &clkset_group2,
778
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
···
783
.clk = {
784
.name = "sclk_cam",
785
.id = 1,
786
},
787
.sources = &clkset_group2,
788
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
···
793
.clk = {
794
.name = "sclk_fimd",
795
.id = -1,
796
-
.enable = s5pv210_clk_ip1_ctrl,
797
-
.ctrlbit = (1 << 0),
798
},
799
.sources = &clkset_group2,
800
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
···
803
.clk = {
804
.name = "sclk_mmc",
805
.id = 0,
806
-
.enable = s5pv210_clk_ip2_ctrl,
807
-
.ctrlbit = (1 << 16),
808
},
809
.sources = &clkset_group2,
810
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
···
813
.clk = {
814
.name = "sclk_mmc",
815
.id = 1,
816
-
.enable = s5pv210_clk_ip2_ctrl,
817
-
.ctrlbit = (1 << 17),
818
},
819
.sources = &clkset_group2,
820
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
···
823
.clk = {
824
.name = "sclk_mmc",
825
.id = 2,
826
-
.enable = s5pv210_clk_ip2_ctrl,
827
-
.ctrlbit = (1 << 18),
828
},
829
.sources = &clkset_group2,
830
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
···
833
.clk = {
834
.name = "sclk_mmc",
835
.id = 3,
836
-
.enable = s5pv210_clk_ip2_ctrl,
837
-
.ctrlbit = (1 << 19),
838
},
839
.sources = &clkset_group2,
840
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
···
873
.clk = {
874
.name = "sclk_csis",
875
.id = -1,
876
-
.enable = s5pv210_clk_ip0_ctrl,
877
-
.ctrlbit = (1 << 31),
878
},
879
.sources = &clkset_group2,
880
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
···
883
.clk = {
884
.name = "sclk_spi",
885
.id = 0,
886
-
.enable = s5pv210_clk_ip3_ctrl,
887
-
.ctrlbit = (1 << 12),
888
},
889
.sources = &clkset_group2,
890
.reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
···
893
.clk = {
894
.name = "sclk_spi",
895
.id = 1,
896
-
.enable = s5pv210_clk_ip3_ctrl,
897
-
.ctrlbit = (1 << 13),
898
},
899
.sources = &clkset_group2,
900
.reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
···
903
.clk = {
904
.name = "sclk_pwi",
905
.id = -1,
906
-
.enable = &s5pv210_clk_ip4_ctrl,
907
-
.ctrlbit = (1 << 2),
908
},
909
.sources = &clkset_group2,
910
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
···
913
.clk = {
914
.name = "sclk_pwm",
915
.id = -1,
916
-
.enable = s5pv210_clk_ip3_ctrl,
917
-
.ctrlbit = (1 << 23),
918
},
919
.sources = &clkset_group2,
920
.reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
···
183
return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
184
}
185
186
+
static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
187
+
{
188
+
return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
189
+
}
190
+
191
static struct clk clk_sclk_hdmi27m = {
192
.name = "sclk_hdmi27m",
193
.id = -1,
···
406
.id = 0,
407
.parent = &clk_p,
408
.enable = s5pv210_clk_ip3_ctrl,
409
+
.ctrlbit = (1 << 5),
410
}, {
411
.name = "i2s_v32",
412
.id = 1,
413
.parent = &clk_p,
414
.enable = s5pv210_clk_ip3_ctrl,
415
+
.ctrlbit = (1 << 6),
416
+
},
417
};
418
419
static struct clk init_clocks[] = {
···
429
.id = 0,
430
.parent = &clk_pclk_psys.clk,
431
.enable = s5pv210_clk_ip3_ctrl,
432
+
.ctrlbit = (1 << 17),
433
}, {
434
.name = "uart",
435
.id = 1,
436
.parent = &clk_pclk_psys.clk,
437
.enable = s5pv210_clk_ip3_ctrl,
438
+
.ctrlbit = (1 << 18),
439
}, {
440
.name = "uart",
441
.id = 2,
442
.parent = &clk_pclk_psys.clk,
443
.enable = s5pv210_clk_ip3_ctrl,
444
+
.ctrlbit = (1 << 19),
445
}, {
446
.name = "uart",
447
.id = 3,
448
.parent = &clk_pclk_psys.clk,
449
.enable = s5pv210_clk_ip3_ctrl,
450
+
.ctrlbit = (1 << 20),
451
},
452
};
453
···
497
.clk = {
498
.name = "sclk_dac",
499
.id = -1,
500
+
.enable = s5pv210_clk_mask0_ctrl,
501
+
.ctrlbit = (1 << 2),
502
},
503
.sources = &clkset_sclk_dac,
504
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
···
527
.clk = {
528
.name = "sclk_hdmi",
529
.id = -1,
530
+
.enable = s5pv210_clk_mask0_ctrl,
531
+
.ctrlbit = (1 << 0),
532
},
533
.sources = &clkset_sclk_hdmi,
534
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
···
565
.clk = {
566
.name = "sclk_audio",
567
.id = 0,
568
+
.enable = s5pv210_clk_mask0_ctrl,
569
+
.ctrlbit = (1 << 24),
570
},
571
.sources = &clkset_sclk_audio0,
572
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
···
594
.clk = {
595
.name = "sclk_audio",
596
.id = 1,
597
+
.enable = s5pv210_clk_mask0_ctrl,
598
+
.ctrlbit = (1 << 25),
599
},
600
.sources = &clkset_sclk_audio1,
601
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
···
623
.clk = {
624
.name = "sclk_audio",
625
.id = 2,
626
+
.enable = s5pv210_clk_mask0_ctrl,
627
+
.ctrlbit = (1 << 26),
628
},
629
.sources = &clkset_sclk_audio2,
630
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
···
680
.clk = {
681
.name = "uclk1",
682
.id = 0,
683
+
.enable = s5pv210_clk_mask0_ctrl,
684
+
.ctrlbit = (1 << 12),
685
},
686
.sources = &clkset_uart,
687
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
···
690
.clk = {
691
.name = "uclk1",
692
.id = 1,
693
+
.enable = s5pv210_clk_mask0_ctrl,
694
+
.ctrlbit = (1 << 13),
695
},
696
.sources = &clkset_uart,
697
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
···
700
.clk = {
701
.name = "uclk1",
702
.id = 2,
703
+
.enable = s5pv210_clk_mask0_ctrl,
704
+
.ctrlbit = (1 << 14),
705
},
706
.sources = &clkset_uart,
707
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
···
710
.clk = {
711
.name = "uclk1",
712
.id = 3,
713
+
.enable = s5pv210_clk_mask0_ctrl,
714
+
.ctrlbit = (1 << 15),
715
},
716
.sources = &clkset_uart,
717
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
···
720
.clk = {
721
.name = "sclk_mixer",
722
.id = -1,
723
+
.enable = s5pv210_clk_mask0_ctrl,
724
+
.ctrlbit = (1 << 1),
725
},
726
.sources = &clkset_sclk_mixer,
727
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
···
738
.clk = {
739
.name = "sclk_fimc",
740
.id = 0,
741
+
.enable = s5pv210_clk_mask1_ctrl,
742
+
.ctrlbit = (1 << 2),
743
},
744
.sources = &clkset_group2,
745
.reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
···
748
.clk = {
749
.name = "sclk_fimc",
750
.id = 1,
751
+
.enable = s5pv210_clk_mask1_ctrl,
752
+
.ctrlbit = (1 << 3),
753
},
754
.sources = &clkset_group2,
755
.reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
···
758
.clk = {
759
.name = "sclk_fimc",
760
.id = 2,
761
+
.enable = s5pv210_clk_mask1_ctrl,
762
+
.ctrlbit = (1 << 4),
763
},
764
.sources = &clkset_group2,
765
.reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
···
768
.clk = {
769
.name = "sclk_cam",
770
.id = 0,
771
+
.enable = s5pv210_clk_mask0_ctrl,
772
+
.ctrlbit = (1 << 3),
773
},
774
.sources = &clkset_group2,
775
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
···
776
.clk = {
777
.name = "sclk_cam",
778
.id = 1,
779
+
.enable = s5pv210_clk_mask0_ctrl,
780
+
.ctrlbit = (1 << 4),
781
},
782
.sources = &clkset_group2,
783
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
···
784
.clk = {
785
.name = "sclk_fimd",
786
.id = -1,
787
+
.enable = s5pv210_clk_mask0_ctrl,
788
+
.ctrlbit = (1 << 5),
789
},
790
.sources = &clkset_group2,
791
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
···
794
.clk = {
795
.name = "sclk_mmc",
796
.id = 0,
797
+
.enable = s5pv210_clk_mask0_ctrl,
798
+
.ctrlbit = (1 << 8),
799
},
800
.sources = &clkset_group2,
801
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
···
804
.clk = {
805
.name = "sclk_mmc",
806
.id = 1,
807
+
.enable = s5pv210_clk_mask0_ctrl,
808
+
.ctrlbit = (1 << 9),
809
},
810
.sources = &clkset_group2,
811
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
···
814
.clk = {
815
.name = "sclk_mmc",
816
.id = 2,
817
+
.enable = s5pv210_clk_mask0_ctrl,
818
+
.ctrlbit = (1 << 10),
819
},
820
.sources = &clkset_group2,
821
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
···
824
.clk = {
825
.name = "sclk_mmc",
826
.id = 3,
827
+
.enable = s5pv210_clk_mask0_ctrl,
828
+
.ctrlbit = (1 << 11),
829
},
830
.sources = &clkset_group2,
831
.reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
···
864
.clk = {
865
.name = "sclk_csis",
866
.id = -1,
867
+
.enable = s5pv210_clk_mask0_ctrl,
868
+
.ctrlbit = (1 << 6),
869
},
870
.sources = &clkset_group2,
871
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
···
874
.clk = {
875
.name = "sclk_spi",
876
.id = 0,
877
+
.enable = s5pv210_clk_mask0_ctrl,
878
+
.ctrlbit = (1 << 16),
879
},
880
.sources = &clkset_group2,
881
.reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
···
884
.clk = {
885
.name = "sclk_spi",
886
.id = 1,
887
+
.enable = s5pv210_clk_mask0_ctrl,
888
+
.ctrlbit = (1 << 17),
889
},
890
.sources = &clkset_group2,
891
.reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
···
894
.clk = {
895
.name = "sclk_pwi",
896
.id = -1,
897
+
.enable = s5pv210_clk_mask0_ctrl,
898
+
.ctrlbit = (1 << 29),
899
},
900
.sources = &clkset_group2,
901
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
···
904
.clk = {
905
.name = "sclk_pwm",
906
.id = -1,
907
+
.enable = s5pv210_clk_mask0_ctrl,
908
+
.ctrlbit = (1 << 19),
909
},
910
.sources = &clkset_group2,
911
.reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
+1
-1
arch/arm/plat-s5p/irq-eint.c
+1
-1
arch/arm/plat-s5p/irq-eint.c
+3
-1
arch/arm/plat-samsung/include/plat/sdhci.h
+3
-1
arch/arm/plat-samsung/include/plat/sdhci.h
···
166
#else
167
static inline void s3c6410_default_sdhci0(void) { }
168
static inline void s3c6410_default_sdhci1(void) { }
169
static inline void s3c6400_default_sdhci0(void) { }
170
static inline void s3c6400_default_sdhci1(void) { }
171
172
#endif /* CONFIG_S3C64XX_SETUP_SDHCI */
173
···
241
s3c_hsmmc0_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card;
242
}
243
#else
244
-
static inline void s5pc100_default_sdhci0(void) { }
245
#endif /* CONFIG_S3C_DEV_HSMMC */
246
247
#ifdef CONFIG_S3C_DEV_HSMMC1
···
166
#else
167
static inline void s3c6410_default_sdhci0(void) { }
168
static inline void s3c6410_default_sdhci1(void) { }
169
+
static inline void s3c6410_default_sdhci2(void) { }
170
static inline void s3c6400_default_sdhci0(void) { }
171
static inline void s3c6400_default_sdhci1(void) { }
172
+
static inline void s3c6400_default_sdhci2(void) { }
173
174
#endif /* CONFIG_S3C64XX_SETUP_SDHCI */
175
···
239
s3c_hsmmc0_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card;
240
}
241
#else
242
+
static inline void s5pv210_default_sdhci0(void) { }
243
#endif /* CONFIG_S3C_DEV_HSMMC */
244
245
#ifdef CONFIG_S3C_DEV_HSMMC1