commit 67415020950046e32f520c1447e79ebebbf447ac · tjh.dev/kernel

tjh.dev / kernel

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Merge branch 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung

* 's5p-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: SAMSUNG: Fix on wrong function name for S5PV210 sdhci0
ARM: S5P6442: Fix PLL setting announce message.
ARM: SAMSUNG: Fix build without SDHCI controllers for S3C64XX
ARM: S5PV210: Correct clock register properties
ARM: S5P: Bug fix on external interrupt for S5P SoCs

Linus Torvalds 15 years ago 67415020 2aa72f61

+67 -56

4 changed files

expand all

unified split

arch

arm

mach-s5p6442

clock.c

mach-s5pv210

clock.c

plat-s5p

irq-eint.c

plat-samsung

include

plat

sdhci.h

+1 -1

arch/arm/mach-s5p6442/clock.c

··· 294 294 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); 295 295 epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500); 296 296 297 - printk(KERN_INFO "S5P6440: PLL settings, A=%ld, M=%ld, E=%ld", 297 + printk(KERN_INFO "S5P6442: PLL settings, A=%ld, M=%ld, E=%ld", 298 298 apll, mpll, epll); 299 299 300 300 clk_fout_apll.rate = apll;

+62 -53

arch/arm/mach-s5pv210/clock.c

··· 183 183 return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable); 184 184 } 185 185 186 + static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable) 187 + { 188 + return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable); 189 + } 190 + 186 191 static struct clk clk_sclk_hdmi27m = { 187 192 .name = "sclk_hdmi27m", 188 193 .id = -1, ··· 411 406 .id = 0, 412 407 .parent = &clk_p, 413 408 .enable = s5pv210_clk_ip3_ctrl, 414 - .ctrlbit = (1<<4), 409 + .ctrlbit = (1 << 5), 415 410 }, { 416 411 .name = "i2s_v32", 417 412 .id = 1, 418 413 .parent = &clk_p, 419 414 .enable = s5pv210_clk_ip3_ctrl, 420 - .ctrlbit = (1<<4), 421 - } 415 + .ctrlbit = (1 << 6), 416 + }, 422 417 }; 423 418 424 419 static struct clk init_clocks[] = { ··· 434 429 .id = 0, 435 430 .parent = &clk_pclk_psys.clk, 436 431 .enable = s5pv210_clk_ip3_ctrl, 437 - .ctrlbit = (1<<7), 432 + .ctrlbit = (1 << 17), 438 433 }, { 439 434 .name = "uart", 440 435 .id = 1, 441 436 .parent = &clk_pclk_psys.clk, 442 437 .enable = s5pv210_clk_ip3_ctrl, 443 - .ctrlbit = (1<<8), 438 + .ctrlbit = (1 << 18), 444 439 }, { 445 440 .name = "uart", 446 441 .id = 2, 447 442 .parent = &clk_pclk_psys.clk, 448 443 .enable = s5pv210_clk_ip3_ctrl, 449 - .ctrlbit = (1<<9), 444 + .ctrlbit = (1 << 19), 450 445 }, { 451 446 .name = "uart", 452 447 .id = 3, 453 448 .parent = &clk_pclk_psys.clk, 454 449 .enable = s5pv210_clk_ip3_ctrl, 455 - .ctrlbit = (1<<10), 450 + .ctrlbit = (1 << 20), 456 451 }, 457 452 }; 458 453 ··· 502 497 .clk = { 503 498 .name = "sclk_dac", 504 499 .id = -1, 505 - .ctrlbit = (1 << 10), 506 - .enable = s5pv210_clk_ip1_ctrl, 500 + .enable = s5pv210_clk_mask0_ctrl, 501 + .ctrlbit = (1 << 2), 507 502 }, 508 503 .sources = &clkset_sclk_dac, 509 504 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 }, ··· 532 527 .clk = { 533 528 .name = "sclk_hdmi", 534 529 .id = -1, 535 - .enable = s5pv210_clk_ip1_ctrl, 536 - .ctrlbit = (1 << 11), 530 + .enable = s5pv210_clk_mask0_ctrl, 531 + .ctrlbit = (1 << 0), 537 532 }, 538 533 .sources = &clkset_sclk_hdmi, 539 534 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 }, ··· 570 565 .clk = { 571 566 .name = "sclk_audio", 572 567 .id = 0, 573 - .enable = s5pv210_clk_ip3_ctrl, 574 - .ctrlbit = (1 << 4), 568 + .enable = s5pv210_clk_mask0_ctrl, 569 + .ctrlbit = (1 << 24), 575 570 }, 576 571 .sources = &clkset_sclk_audio0, 577 572 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 }, ··· 599 594 .clk = { 600 595 .name = "sclk_audio", 601 596 .id = 1, 602 - .enable = s5pv210_clk_ip3_ctrl, 603 - .ctrlbit = (1 << 5), 597 + .enable = s5pv210_clk_mask0_ctrl, 598 + .ctrlbit = (1 << 25), 604 599 }, 605 600 .sources = &clkset_sclk_audio1, 606 601 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 }, ··· 628 623 .clk = { 629 624 .name = "sclk_audio", 630 625 .id = 2, 631 - .enable = s5pv210_clk_ip3_ctrl, 632 - .ctrlbit = (1 << 6), 626 + .enable = s5pv210_clk_mask0_ctrl, 627 + .ctrlbit = (1 << 26), 633 628 }, 634 629 .sources = &clkset_sclk_audio2, 635 630 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 }, ··· 685 680 .clk = { 686 681 .name = "uclk1", 687 682 .id = 0, 688 - .ctrlbit = (1<<17), 689 - .enable = s5pv210_clk_ip3_ctrl, 683 + .enable = s5pv210_clk_mask0_ctrl, 684 + .ctrlbit = (1 << 12), 690 685 }, 691 686 .sources = &clkset_uart, 692 687 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 }, ··· 695 690 .clk = { 696 691 .name = "uclk1", 697 692 .id = 1, 698 - .enable = s5pv210_clk_ip3_ctrl, 699 - .ctrlbit = (1 << 18), 693 + .enable = s5pv210_clk_mask0_ctrl, 694 + .ctrlbit = (1 << 13), 700 695 }, 701 696 .sources = &clkset_uart, 702 697 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 }, ··· 705 700 .clk = { 706 701 .name = "uclk1", 707 702 .id = 2, 708 - .enable = s5pv210_clk_ip3_ctrl, 709 - .ctrlbit = (1 << 19), 703 + .enable = s5pv210_clk_mask0_ctrl, 704 + .ctrlbit = (1 << 14), 710 705 }, 711 706 .sources = &clkset_uart, 712 707 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 }, ··· 715 710 .clk = { 716 711 .name = "uclk1", 717 712 .id = 3, 718 - .enable = s5pv210_clk_ip3_ctrl, 719 - .ctrlbit = (1 << 20), 713 + .enable = s5pv210_clk_mask0_ctrl, 714 + .ctrlbit = (1 << 15), 720 715 }, 721 716 .sources = &clkset_uart, 722 717 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 }, ··· 725 720 .clk = { 726 721 .name = "sclk_mixer", 727 722 .id = -1, 728 - .enable = s5pv210_clk_ip1_ctrl, 729 - .ctrlbit = (1 << 9), 723 + .enable = s5pv210_clk_mask0_ctrl, 724 + .ctrlbit = (1 << 1), 730 725 }, 731 726 .sources = &clkset_sclk_mixer, 732 727 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 }, ··· 743 738 .clk = { 744 739 .name = "sclk_fimc", 745 740 .id = 0, 746 - .enable = s5pv210_clk_ip0_ctrl, 747 - .ctrlbit = (1 << 24), 741 + .enable = s5pv210_clk_mask1_ctrl, 742 + .ctrlbit = (1 << 2), 748 743 }, 749 744 .sources = &clkset_group2, 750 745 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 }, ··· 753 748 .clk = { 754 749 .name = "sclk_fimc", 755 750 .id = 1, 756 - .enable = s5pv210_clk_ip0_ctrl, 757 - .ctrlbit = (1 << 25), 751 + .enable = s5pv210_clk_mask1_ctrl, 752 + .ctrlbit = (1 << 3), 758 753 }, 759 754 .sources = &clkset_group2, 760 755 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 }, ··· 763 758 .clk = { 764 759 .name = "sclk_fimc", 765 760 .id = 2, 766 - .enable = s5pv210_clk_ip0_ctrl, 767 - .ctrlbit = (1 << 26), 761 + .enable = s5pv210_clk_mask1_ctrl, 762 + .ctrlbit = (1 << 4), 768 763 }, 769 764 .sources = &clkset_group2, 770 765 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 }, ··· 773 768 .clk = { 774 769 .name = "sclk_cam", 775 770 .id = 0, 771 + .enable = s5pv210_clk_mask0_ctrl, 772 + .ctrlbit = (1 << 3), 776 773 }, 777 774 .sources = &clkset_group2, 778 775 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 }, ··· 783 776 .clk = { 784 777 .name = "sclk_cam", 785 778 .id = 1, 779 + .enable = s5pv210_clk_mask0_ctrl, 780 + .ctrlbit = (1 << 4), 786 781 }, 787 782 .sources = &clkset_group2, 788 783 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 }, ··· 793 784 .clk = { 794 785 .name = "sclk_fimd", 795 786 .id = -1, 796 - .enable = s5pv210_clk_ip1_ctrl, 797 - .ctrlbit = (1 << 0), 787 + .enable = s5pv210_clk_mask0_ctrl, 788 + .ctrlbit = (1 << 5), 798 789 }, 799 790 .sources = &clkset_group2, 800 791 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 }, ··· 803 794 .clk = { 804 795 .name = "sclk_mmc", 805 796 .id = 0, 806 - .enable = s5pv210_clk_ip2_ctrl, 807 - .ctrlbit = (1 << 16), 797 + .enable = s5pv210_clk_mask0_ctrl, 798 + .ctrlbit = (1 << 8), 808 799 }, 809 800 .sources = &clkset_group2, 810 801 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 }, ··· 813 804 .clk = { 814 805 .name = "sclk_mmc", 815 806 .id = 1, 816 - .enable = s5pv210_clk_ip2_ctrl, 817 - .ctrlbit = (1 << 17), 807 + .enable = s5pv210_clk_mask0_ctrl, 808 + .ctrlbit = (1 << 9), 818 809 }, 819 810 .sources = &clkset_group2, 820 811 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 }, ··· 823 814 .clk = { 824 815 .name = "sclk_mmc", 825 816 .id = 2, 826 - .enable = s5pv210_clk_ip2_ctrl, 827 - .ctrlbit = (1 << 18), 817 + .enable = s5pv210_clk_mask0_ctrl, 818 + .ctrlbit = (1 << 10), 828 819 }, 829 820 .sources = &clkset_group2, 830 821 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 }, ··· 833 824 .clk = { 834 825 .name = "sclk_mmc", 835 826 .id = 3, 836 - .enable = s5pv210_clk_ip2_ctrl, 837 - .ctrlbit = (1 << 19), 827 + .enable = s5pv210_clk_mask0_ctrl, 828 + .ctrlbit = (1 << 11), 838 829 }, 839 830 .sources = &clkset_group2, 840 831 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 }, ··· 873 864 .clk = { 874 865 .name = "sclk_csis", 875 866 .id = -1, 876 - .enable = s5pv210_clk_ip0_ctrl, 877 - .ctrlbit = (1 << 31), 867 + .enable = s5pv210_clk_mask0_ctrl, 868 + .ctrlbit = (1 << 6), 878 869 }, 879 870 .sources = &clkset_group2, 880 871 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 }, ··· 883 874 .clk = { 884 875 .name = "sclk_spi", 885 876 .id = 0, 886 - .enable = s5pv210_clk_ip3_ctrl, 887 - .ctrlbit = (1 << 12), 877 + .enable = s5pv210_clk_mask0_ctrl, 878 + .ctrlbit = (1 << 16), 888 879 }, 889 880 .sources = &clkset_group2, 890 881 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 }, ··· 893 884 .clk = { 894 885 .name = "sclk_spi", 895 886 .id = 1, 896 - .enable = s5pv210_clk_ip3_ctrl, 897 - .ctrlbit = (1 << 13), 887 + .enable = s5pv210_clk_mask0_ctrl, 888 + .ctrlbit = (1 << 17), 898 889 }, 899 890 .sources = &clkset_group2, 900 891 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 }, ··· 903 894 .clk = { 904 895 .name = "sclk_pwi", 905 896 .id = -1, 906 - .enable = &s5pv210_clk_ip4_ctrl, 907 - .ctrlbit = (1 << 2), 897 + .enable = s5pv210_clk_mask0_ctrl, 898 + .ctrlbit = (1 << 29), 908 899 }, 909 900 .sources = &clkset_group2, 910 901 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 }, ··· 913 904 .clk = { 914 905 .name = "sclk_pwm", 915 906 .id = -1, 916 - .enable = s5pv210_clk_ip3_ctrl, 917 - .ctrlbit = (1 << 23), 907 + .enable = s5pv210_clk_mask0_ctrl, 908 + .ctrlbit = (1 << 19), 918 909 }, 919 910 .sources = &clkset_group2, 920 911 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },

+1 -1

arch/arm/plat-s5p/irq-eint.c

··· 71 71 break; 72 72 73 73 case IRQ_TYPE_EDGE_FALLING: 74 - newvalue = S5P_EXTINT_RISEEDGE; 74 + newvalue = S5P_EXTINT_FALLEDGE; 75 75 break; 76 76 77 77 case IRQ_TYPE_EDGE_BOTH:

+3 -1

arch/arm/plat-samsung/include/plat/sdhci.h

··· 166 166 #else 167 167 static inline void s3c6410_default_sdhci0(void) { } 168 168 static inline void s3c6410_default_sdhci1(void) { } 169 + static inline void s3c6410_default_sdhci2(void) { } 169 170 static inline void s3c6400_default_sdhci0(void) { } 170 171 static inline void s3c6400_default_sdhci1(void) { } 172 + static inline void s3c6400_default_sdhci2(void) { } 171 173 172 174 #endif /* CONFIG_S3C64XX_SETUP_SDHCI */ 173 175 ··· 241 239 s3c_hsmmc0_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card; 242 240 } 243 241 #else 244 - static inline void s5pc100_default_sdhci0(void) { } 242 + static inline void s5pv210_default_sdhci0(void) { } 245 243 #endif /* CONFIG_S3C_DEV_HSMMC */ 246 244 247 245 #ifdef CONFIG_S3C_DEV_HSMMC1