pinctrl: sophgo: add support for SG2044 SoC

+12

drivers/pinctrl/sophgo/Kconfig

··· 74 74 This pin controller allows selecting the mux function for 75 75 each pin. This driver can also be built as a module called 76 76 pinctrl-sg2042. 77 + 78 + config PINCTRL_SOPHGO_SG2044 79 + tristate "Sophgo SG2044 SoC Pinctrl driver" 80 + depends on ARCH_SOPHGO || COMPILE_TEST 81 + depends on OF 82 + select PINCTRL_SOPHGO_COMMON 83 + select PINCTRL_SOPHGO_SG2042_OPS 84 + help 85 + Say Y to select the pinctrl driver for SG2044 SoC. 86 + This pin controller allows selecting the mux function for 87 + each pin. This driver can also be built as a module called 88 + pinctrl-sg2044.

+1

drivers/pinctrl/sophgo/Makefile

··· 10 10 obj-$(CONFIG_PINCTRL_SOPHGO_SG2000) += pinctrl-sg2000.o 11 11 obj-$(CONFIG_PINCTRL_SOPHGO_SG2002) += pinctrl-sg2002.o 12 12 obj-$(CONFIG_PINCTRL_SOPHGO_SG2042) += pinctrl-sg2042.o 13 + obj-$(CONFIG_PINCTRL_SOPHGO_SG2044) += pinctrl-sg2044.o

+718

drivers/pinctrl/sophgo/pinctrl-sg2044.c

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Sophgo SG2042 SoC pinctrl driver. 4 + * 5 + * Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com> 6 + */ 7 + 8 + #include <linux/module.h> 9 + #include <linux/platform_device.h> 10 + #include <linux/of.h> 11 + 12 + #include <linux/pinctrl/pinctrl.h> 13 + #include <linux/pinctrl/pinmux.h> 14 + 15 + #include <dt-bindings/pinctrl/pinctrl-sg2044.h> 16 + 17 + #include "pinctrl-sg2042.h" 18 + 19 + static int sg2044_get_pull_up(const struct sophgo_pin *sp, const u32 *psmap) 20 + { 21 + return 19500; 22 + } 23 + 24 + static int sg2044_get_pull_down(const struct sophgo_pin *sp, const u32 *psmap) 25 + { 26 + return 23200; 27 + } 28 + 29 + static const u32 sg2044_oc_map[] = { 30 + 3200, 6400, 9600, 12700, 31 + 15900, 19100, 22200, 25300, 32 + 29500, 32700, 35900, 39000, 33 + 42000, 45200, 48300, 51400 34 + }; 35 + 36 + static int sg2044_get_oc_map(const struct sophgo_pin *sp, const u32 *psmap, 37 + const u32 **map) 38 + { 39 + *map = sg2044_oc_map; 40 + return ARRAY_SIZE(sg2044_oc_map); 41 + } 42 + 43 + static const struct sophgo_vddio_cfg_ops sg2044_vddio_cfg_ops = { 44 + .get_pull_up = sg2044_get_pull_up, 45 + .get_pull_down = sg2044_get_pull_down, 46 + .get_oc_map = sg2044_get_oc_map, 47 + }; 48 + 49 + static const struct pinctrl_pin_desc sg2044_pins[] = { 50 + PINCTRL_PIN(PIN_IIC0_SMBSUS_IN, "iic0_smbsus_in"), 51 + PINCTRL_PIN(PIN_IIC0_SMBSUS_OUT, "iic0_smbsus_out"), 52 + PINCTRL_PIN(PIN_IIC0_SMBALERT, "iic0_smbalert"), 53 + PINCTRL_PIN(PIN_IIC1_SMBSUS_IN, "iic1_smbsus_in"), 54 + PINCTRL_PIN(PIN_IIC1_SMBSUS_OUT, "iic1_smbsus_out"), 55 + PINCTRL_PIN(PIN_IIC1_SMBALERT, "iic1_smbalert"), 56 + PINCTRL_PIN(PIN_IIC2_SMBSUS_IN, "iic2_smbsus_in"), 57 + PINCTRL_PIN(PIN_IIC2_SMBSUS_OUT, "iic2_smbsus_out"), 58 + PINCTRL_PIN(PIN_IIC2_SMBALERT, "iic2_smbalert"), 59 + PINCTRL_PIN(PIN_IIC3_SMBSUS_IN, "iic3_smbsus_in"), 60 + PINCTRL_PIN(PIN_IIC3_SMBSUS_OUT, "iic3_smbsus_out"), 61 + PINCTRL_PIN(PIN_IIC3_SMBALERT, "iic3_smbalert"), 62 + PINCTRL_PIN(PIN_PCIE0_L0_RESET, "pcie0_l0_reset"), 63 + PINCTRL_PIN(PIN_PCIE0_L1_RESET, "pcie0_l1_reset"), 64 + PINCTRL_PIN(PIN_PCIE0_L0_WAKEUP, "pcie0_l0_wakeup"), 65 + PINCTRL_PIN(PIN_PCIE0_L1_WAKEUP, "pcie0_l1_wakeup"), 66 + PINCTRL_PIN(PIN_PCIE0_L0_CLKREQ_IN, "pcie0_l0_clkreq_in"), 67 + PINCTRL_PIN(PIN_PCIE0_L1_CLKREQ_IN, "pcie0_l1_clkreq_in"), 68 + PINCTRL_PIN(PIN_PCIE1_L0_RESET, "pcie1_l0_reset"), 69 + PINCTRL_PIN(PIN_PCIE1_L1_RESET, "pcie1_l1_reset"), 70 + PINCTRL_PIN(PIN_PCIE1_L0_WAKEUP, "pcie1_l0_wakeup"), 71 + PINCTRL_PIN(PIN_PCIE1_L1_WAKEUP, "pcie1_l1_wakeup"), 72 + PINCTRL_PIN(PIN_PCIE1_L0_CLKREQ_IN, "pcie1_l0_clkreq_in"), 73 + PINCTRL_PIN(PIN_PCIE1_L1_CLKREQ_IN, "pcie1_l1_clkreq_in"), 74 + PINCTRL_PIN(PIN_PCIE2_L0_RESET, "pcie2_l0_reset"), 75 + PINCTRL_PIN(PIN_PCIE2_L1_RESET, "pcie2_l1_reset"), 76 + PINCTRL_PIN(PIN_PCIE2_L0_WAKEUP, "pcie2_l0_wakeup"), 77 + PINCTRL_PIN(PIN_PCIE2_L1_WAKEUP, "pcie2_l1_wakeup"), 78 + PINCTRL_PIN(PIN_PCIE2_L0_CLKREQ_IN, "pcie2_l0_clkreq_in"), 79 + PINCTRL_PIN(PIN_PCIE2_L1_CLKREQ_IN, "pcie2_l1_clkreq_in"), 80 + PINCTRL_PIN(PIN_PCIE3_L0_RESET, "pcie3_l0_reset"), 81 + PINCTRL_PIN(PIN_PCIE3_L1_RESET, "pcie3_l1_reset"), 82 + PINCTRL_PIN(PIN_PCIE3_L0_WAKEUP, "pcie3_l0_wakeup"), 83 + PINCTRL_PIN(PIN_PCIE3_L1_WAKEUP, "pcie3_l1_wakeup"), 84 + PINCTRL_PIN(PIN_PCIE3_L0_CLKREQ_IN, "pcie3_l0_clkreq_in"), 85 + PINCTRL_PIN(PIN_PCIE3_L1_CLKREQ_IN, "pcie3_l1_clkreq_in"), 86 + PINCTRL_PIN(PIN_PCIE4_L0_RESET, "pcie4_l0_reset"), 87 + PINCTRL_PIN(PIN_PCIE4_L1_RESET, "pcie4_l1_reset"), 88 + PINCTRL_PIN(PIN_PCIE4_L0_WAKEUP, "pcie4_l0_wakeup"), 89 + PINCTRL_PIN(PIN_PCIE4_L1_WAKEUP, "pcie4_l1_wakeup"), 90 + PINCTRL_PIN(PIN_PCIE4_L0_CLKREQ_IN, "pcie4_l0_clkreq_in"), 91 + PINCTRL_PIN(PIN_PCIE4_L1_CLKREQ_IN, "pcie4_l1_clkreq_in"), 92 + PINCTRL_PIN(PIN_SPIF0_CLK_SEL1, "spif0_clk_sel1"), 93 + PINCTRL_PIN(PIN_SPIF0_CLK_SEL0, "spif0_clk_sel0"), 94 + PINCTRL_PIN(PIN_SPIF0_WP, "spif0_wp"), 95 + PINCTRL_PIN(PIN_SPIF0_HOLD, "spif0_hold"), 96 + PINCTRL_PIN(PIN_SPIF0_SDI, "spif0_sdi"), 97 + PINCTRL_PIN(PIN_SPIF0_CS, "spif0_cs"), 98 + PINCTRL_PIN(PIN_SPIF0_SCK, "spif0_sck"), 99 + PINCTRL_PIN(PIN_SPIF0_SDO, "spif0_sdo"), 100 + PINCTRL_PIN(PIN_SPIF1_CLK_SEL1, "spif1_clk_sel1"), 101 + PINCTRL_PIN(PIN_SPIF1_CLK_SEL0, "spif1_clk_sel0"), 102 + PINCTRL_PIN(PIN_SPIF1_WP, "spif1_wp"), 103 + PINCTRL_PIN(PIN_SPIF1_HOLD, "spif1_hold"), 104 + PINCTRL_PIN(PIN_SPIF1_SDI, "spif1_sdi"), 105 + PINCTRL_PIN(PIN_SPIF1_CS, "spif1_cs"), 106 + PINCTRL_PIN(PIN_SPIF1_SCK, "spif1_sck"), 107 + PINCTRL_PIN(PIN_SPIF1_SDO, "spif1_sdo"), 108 + PINCTRL_PIN(PIN_EMMC_WP, "emmc_wp"), 109 + PINCTRL_PIN(PIN_EMMC_CD, "emmc_cd"), 110 + PINCTRL_PIN(PIN_EMMC_RST, "emmc_rst"), 111 + PINCTRL_PIN(PIN_EMMC_PWR_EN, "emmc_pwr_en"), 112 + PINCTRL_PIN(PIN_SDIO_CD, "sdio_cd"), 113 + PINCTRL_PIN(PIN_SDIO_WP, "sdio_wp"), 114 + PINCTRL_PIN(PIN_SDIO_RST, "sdio_rst"), 115 + PINCTRL_PIN(PIN_SDIO_PWR_EN, "sdio_pwr_en"), 116 + PINCTRL_PIN(PIN_RGMII0_TXD0, "rgmii0_txd0"), 117 + PINCTRL_PIN(PIN_RGMII0_TXD1, "rgmii0_txd1"), 118 + PINCTRL_PIN(PIN_RGMII0_TXD2, "rgmii0_txd2"), 119 + PINCTRL_PIN(PIN_RGMII0_TXD3, "rgmii0_txd3"), 120 + PINCTRL_PIN(PIN_RGMII0_TXCTRL, "rgmii0_txctrl"), 121 + PINCTRL_PIN(PIN_RGMII0_RXD0, "rgmii0_rxd0"), 122 + PINCTRL_PIN(PIN_RGMII0_RXD1, "rgmii0_rxd1"), 123 + PINCTRL_PIN(PIN_RGMII0_RXD2, "rgmii0_rxd2"), 124 + PINCTRL_PIN(PIN_RGMII0_RXD3, "rgmii0_rxd3"), 125 + PINCTRL_PIN(PIN_RGMII0_RXCTRL, "rgmii0_rxctrl"), 126 + PINCTRL_PIN(PIN_RGMII0_TXC, "rgmii0_txc"), 127 + PINCTRL_PIN(PIN_RGMII0_RXC, "rgmii0_rxc"), 128 + PINCTRL_PIN(PIN_RGMII0_REFCLKO, "rgmii0_refclko"), 129 + PINCTRL_PIN(PIN_RGMII0_IRQ, "rgmii0_irq"), 130 + PINCTRL_PIN(PIN_RGMII0_MDC, "rgmii0_mdc"), 131 + PINCTRL_PIN(PIN_RGMII0_MDIO, "rgmii0_mdio"), 132 + PINCTRL_PIN(PIN_PWM0, "pwm0"), 133 + PINCTRL_PIN(PIN_PWM1, "pwm1"), 134 + PINCTRL_PIN(PIN_PWM2, "pwm2"), 135 + PINCTRL_PIN(PIN_PWM3, "pwm3"), 136 + PINCTRL_PIN(PIN_FAN0, "fan0"), 137 + PINCTRL_PIN(PIN_FAN1, "fan1"), 138 + PINCTRL_PIN(PIN_FAN2, "fan2"), 139 + PINCTRL_PIN(PIN_FAN3, "fan3"), 140 + PINCTRL_PIN(PIN_IIC0_SDA, "iic0_sda"), 141 + PINCTRL_PIN(PIN_IIC0_SCL, "iic0_scl"), 142 + PINCTRL_PIN(PIN_IIC1_SDA, "iic1_sda"), 143 + PINCTRL_PIN(PIN_IIC1_SCL, "iic1_scl"), 144 + PINCTRL_PIN(PIN_IIC2_SDA, "iic2_sda"), 145 + PINCTRL_PIN(PIN_IIC2_SCL, "iic2_scl"), 146 + PINCTRL_PIN(PIN_IIC3_SDA, "iic3_sda"), 147 + PINCTRL_PIN(PIN_IIC3_SCL, "iic3_scl"), 148 + PINCTRL_PIN(PIN_UART0_TX, "uart0_tx"), 149 + PINCTRL_PIN(PIN_UART0_RX, "uart0_rx"), 150 + PINCTRL_PIN(PIN_UART0_RTS, "uart0_rts"), 151 + PINCTRL_PIN(PIN_UART0_CTS, "uart0_cts"), 152 + PINCTRL_PIN(PIN_UART1_TX, "uart1_tx"), 153 + PINCTRL_PIN(PIN_UART1_RX, "uart1_rx"), 154 + PINCTRL_PIN(PIN_UART1_RTS, "uart1_rts"), 155 + PINCTRL_PIN(PIN_UART1_CTS, "uart1_cts"), 156 + PINCTRL_PIN(PIN_UART2_TX, "uart2_tx"), 157 + PINCTRL_PIN(PIN_UART2_RX, "uart2_rx"), 158 + PINCTRL_PIN(PIN_UART2_RTS, "uart2_rts"), 159 + PINCTRL_PIN(PIN_UART2_CTS, "uart2_cts"), 160 + PINCTRL_PIN(PIN_UART3_TX, "uart3_tx"), 161 + PINCTRL_PIN(PIN_UART3_RX, "uart3_rx"), 162 + PINCTRL_PIN(PIN_UART3_RTS, "uart3_rts"), 163 + PINCTRL_PIN(PIN_UART3_CTS, "uart3_cts"), 164 + PINCTRL_PIN(PIN_SPI0_CS0, "spi0_cs0"), 165 + PINCTRL_PIN(PIN_SPI0_CS1, "spi0_cs1"), 166 + PINCTRL_PIN(PIN_SPI0_SDI, "spi0_sdi"), 167 + PINCTRL_PIN(PIN_SPI0_SDO, "spi0_sdo"), 168 + PINCTRL_PIN(PIN_SPI0_SCK, "spi0_sck"), 169 + PINCTRL_PIN(PIN_SPI1_CS0, "spi1_cs0"), 170 + PINCTRL_PIN(PIN_SPI1_CS1, "spi1_cs1"), 171 + PINCTRL_PIN(PIN_SPI1_SDI, "spi1_sdi"), 172 + PINCTRL_PIN(PIN_SPI1_SDO, "spi1_sdo"), 173 + PINCTRL_PIN(PIN_SPI1_SCK, "spi1_sck"), 174 + PINCTRL_PIN(PIN_JTAG0_TDO, "jtag0_tdo"), 175 + PINCTRL_PIN(PIN_JTAG0_TCK, "jtag0_tck"), 176 + PINCTRL_PIN(PIN_JTAG0_TDI, "jtag0_tdi"), 177 + PINCTRL_PIN(PIN_JTAG0_TMS, "jtag0_tms"), 178 + PINCTRL_PIN(PIN_JTAG0_TRST, "jtag0_trst"), 179 + PINCTRL_PIN(PIN_JTAG0_SRST, "jtag0_srst"), 180 + PINCTRL_PIN(PIN_JTAG1_TDO, "jtag1_tdo"), 181 + PINCTRL_PIN(PIN_JTAG1_TCK, "jtag1_tck"), 182 + PINCTRL_PIN(PIN_JTAG1_TDI, "jtag1_tdi"), 183 + PINCTRL_PIN(PIN_JTAG1_TMS, "jtag1_tms"), 184 + PINCTRL_PIN(PIN_JTAG1_TRST, "jtag1_trst"), 185 + PINCTRL_PIN(PIN_JTAG1_SRST, "jtag1_srst"), 186 + PINCTRL_PIN(PIN_JTAG2_TDO, "jtag2_tdo"), 187 + PINCTRL_PIN(PIN_JTAG2_TCK, "jtag2_tck"), 188 + PINCTRL_PIN(PIN_JTAG2_TDI, "jtag2_tdi"), 189 + PINCTRL_PIN(PIN_JTAG2_TMS, "jtag2_tms"), 190 + PINCTRL_PIN(PIN_JTAG2_TRST, "jtag2_trst"), 191 + PINCTRL_PIN(PIN_JTAG2_SRST, "jtag2_srst"), 192 + PINCTRL_PIN(PIN_JTAG3_TDO, "jtag3_tdo"), 193 + PINCTRL_PIN(PIN_JTAG3_TCK, "jtag3_tck"), 194 + PINCTRL_PIN(PIN_JTAG3_TDI, "jtag3_tdi"), 195 + PINCTRL_PIN(PIN_JTAG3_TMS, "jtag3_tms"), 196 + PINCTRL_PIN(PIN_JTAG3_TRST, "jtag3_trst"), 197 + PINCTRL_PIN(PIN_JTAG3_SRST, "jtag3_srst"), 198 + PINCTRL_PIN(PIN_GPIO0, "gpio0"), 199 + PINCTRL_PIN(PIN_GPIO1, "gpio1"), 200 + PINCTRL_PIN(PIN_GPIO2, "gpio2"), 201 + PINCTRL_PIN(PIN_GPIO3, "gpio3"), 202 + PINCTRL_PIN(PIN_GPIO4, "gpio4"), 203 + PINCTRL_PIN(PIN_GPIO5, "gpio5"), 204 + PINCTRL_PIN(PIN_GPIO6, "gpio6"), 205 + PINCTRL_PIN(PIN_GPIO7, "gpio7"), 206 + PINCTRL_PIN(PIN_GPIO8, "gpio8"), 207 + PINCTRL_PIN(PIN_GPIO9, "gpio9"), 208 + PINCTRL_PIN(PIN_GPIO10, "gpio10"), 209 + PINCTRL_PIN(PIN_GPIO11, "gpio11"), 210 + PINCTRL_PIN(PIN_GPIO12, "gpio12"), 211 + PINCTRL_PIN(PIN_GPIO13, "gpio13"), 212 + PINCTRL_PIN(PIN_GPIO14, "gpio14"), 213 + PINCTRL_PIN(PIN_GPIO15, "gpio15"), 214 + PINCTRL_PIN(PIN_GPIO16, "gpio16"), 215 + PINCTRL_PIN(PIN_GPIO17, "gpio17"), 216 + PINCTRL_PIN(PIN_GPIO18, "gpio18"), 217 + PINCTRL_PIN(PIN_GPIO19, "gpio19"), 218 + PINCTRL_PIN(PIN_GPIO20, "gpio20"), 219 + PINCTRL_PIN(PIN_GPIO21, "gpio21"), 220 + PINCTRL_PIN(PIN_GPIO22, "gpio22"), 221 + PINCTRL_PIN(PIN_GPIO23, "gpio23"), 222 + PINCTRL_PIN(PIN_GPIO24, "gpio24"), 223 + PINCTRL_PIN(PIN_GPIO25, "gpio25"), 224 + PINCTRL_PIN(PIN_GPIO26, "gpio26"), 225 + PINCTRL_PIN(PIN_GPIO27, "gpio27"), 226 + PINCTRL_PIN(PIN_GPIO28, "gpio28"), 227 + PINCTRL_PIN(PIN_GPIO29, "gpio29"), 228 + PINCTRL_PIN(PIN_GPIO30, "gpio30"), 229 + PINCTRL_PIN(PIN_GPIO31, "gpio31"), 230 + PINCTRL_PIN(PIN_MODE_SEL0, "mode_sel0"), 231 + PINCTRL_PIN(PIN_MODE_SEL1, "mode_sel1"), 232 + PINCTRL_PIN(PIN_MODE_SEL2, "mode_sel2"), 233 + PINCTRL_PIN(PIN_BOOT_SEL0, "boot_sel0"), 234 + PINCTRL_PIN(PIN_BOOT_SEL1, "boot_sel1"), 235 + PINCTRL_PIN(PIN_BOOT_SEL2, "boot_sel2"), 236 + PINCTRL_PIN(PIN_BOOT_SEL3, "boot_sel3"), 237 + PINCTRL_PIN(PIN_BOOT_SEL4, "boot_sel4"), 238 + PINCTRL_PIN(PIN_BOOT_SEL5, "boot_sel5"), 239 + PINCTRL_PIN(PIN_BOOT_SEL6, "boot_sel6"), 240 + PINCTRL_PIN(PIN_BOOT_SEL7, "boot_sel7"), 241 + PINCTRL_PIN(PIN_MULTI_SCKT, "multi_sckt"), 242 + PINCTRL_PIN(PIN_SCKT_ID0, "sckt_id0"), 243 + PINCTRL_PIN(PIN_SCKT_ID1, "sckt_id1"), 244 + PINCTRL_PIN(PIN_PLL_CLK_IN_MAIN, "pll_clk_in_main"), 245 + PINCTRL_PIN(PIN_PLL_CLK_IN_DDR_0, "pll_clk_in_ddr_0"), 246 + PINCTRL_PIN(PIN_PLL_CLK_IN_DDR_1, "pll_clk_in_ddr_1"), 247 + PINCTRL_PIN(PIN_PLL_CLK_IN_DDR_2, "pll_clk_in_ddr_2"), 248 + PINCTRL_PIN(PIN_PLL_CLK_IN_DDR_3, "pll_clk_in_ddr_3"), 249 + PINCTRL_PIN(PIN_XTAL_32K, "xtal_32k"), 250 + PINCTRL_PIN(PIN_SYS_RST, "sys_rst"), 251 + PINCTRL_PIN(PIN_PWR_BUTTON, "pwr_button"), 252 + PINCTRL_PIN(PIN_TEST_EN, "test_en"), 253 + PINCTRL_PIN(PIN_TEST_MODE_MBIST, "test_mode_mbist"), 254 + PINCTRL_PIN(PIN_TEST_MODE_SCAN, "test_mode_scan"), 255 + PINCTRL_PIN(PIN_TEST_MODE_BSD, "test_mode_bsd"), 256 + PINCTRL_PIN(PIN_BISR_BYP, "bisr_byp"), 257 + }; 258 + 259 + static const struct sg2042_pin sg2044_pin_data[ARRAY_SIZE(sg2044_pins)] = { 260 + SG2042_GENERAL_PIN(PIN_IIC0_SMBSUS_IN, 0x000, 261 + PIN_FLAG_DEFAULT), 262 + SG2042_GENERAL_PIN(PIN_IIC0_SMBSUS_OUT, 0x000, 263 + PIN_FLAG_WRITE_HIGH), 264 + SG2042_GENERAL_PIN(PIN_IIC0_SMBALERT, 0x004, 265 + PIN_FLAG_DEFAULT), 266 + SG2042_GENERAL_PIN(PIN_IIC1_SMBSUS_IN, 0x004, 267 + PIN_FLAG_WRITE_HIGH), 268 + SG2042_GENERAL_PIN(PIN_IIC1_SMBSUS_OUT, 0x008, 269 + PIN_FLAG_DEFAULT), 270 + SG2042_GENERAL_PIN(PIN_IIC1_SMBALERT, 0x008, 271 + PIN_FLAG_WRITE_HIGH), 272 + SG2042_GENERAL_PIN(PIN_IIC2_SMBSUS_IN, 0x00c, 273 + PIN_FLAG_DEFAULT), 274 + SG2042_GENERAL_PIN(PIN_IIC2_SMBSUS_OUT, 0x00c, 275 + PIN_FLAG_WRITE_HIGH), 276 + SG2042_GENERAL_PIN(PIN_IIC2_SMBALERT, 0x010, 277 + PIN_FLAG_DEFAULT), 278 + SG2042_GENERAL_PIN(PIN_IIC3_SMBSUS_IN, 0x010, 279 + PIN_FLAG_WRITE_HIGH), 280 + SG2042_GENERAL_PIN(PIN_IIC3_SMBSUS_OUT, 0x014, 281 + PIN_FLAG_DEFAULT), 282 + SG2042_GENERAL_PIN(PIN_IIC3_SMBALERT, 0x014, 283 + PIN_FLAG_WRITE_HIGH), 284 + SG2042_GENERAL_PIN(PIN_PCIE0_L0_RESET, 0x018, 285 + PIN_FLAG_DEFAULT), 286 + SG2042_GENERAL_PIN(PIN_PCIE0_L1_RESET, 0x018, 287 + PIN_FLAG_WRITE_HIGH), 288 + SG2042_GENERAL_PIN(PIN_PCIE0_L0_WAKEUP, 0x01c, 289 + PIN_FLAG_DEFAULT), 290 + SG2042_GENERAL_PIN(PIN_PCIE0_L1_WAKEUP, 0x01c, 291 + PIN_FLAG_WRITE_HIGH), 292 + SG2042_GENERAL_PIN(PIN_PCIE0_L0_CLKREQ_IN, 0x020, 293 + PIN_FLAG_DEFAULT), 294 + SG2042_GENERAL_PIN(PIN_PCIE0_L1_CLKREQ_IN, 0x020, 295 + PIN_FLAG_WRITE_HIGH), 296 + SG2042_GENERAL_PIN(PIN_PCIE1_L0_RESET, 0x024, 297 + PIN_FLAG_DEFAULT), 298 + SG2042_GENERAL_PIN(PIN_PCIE1_L1_RESET, 0x024, 299 + PIN_FLAG_WRITE_HIGH), 300 + SG2042_GENERAL_PIN(PIN_PCIE1_L0_WAKEUP, 0x028, 301 + PIN_FLAG_DEFAULT), 302 + SG2042_GENERAL_PIN(PIN_PCIE1_L1_WAKEUP, 0x028, 303 + PIN_FLAG_WRITE_HIGH), 304 + SG2042_GENERAL_PIN(PIN_PCIE1_L0_CLKREQ_IN, 0x02c, 305 + PIN_FLAG_DEFAULT), 306 + SG2042_GENERAL_PIN(PIN_PCIE1_L1_CLKREQ_IN, 0x02c, 307 + PIN_FLAG_WRITE_HIGH), 308 + SG2042_GENERAL_PIN(PIN_PCIE2_L0_RESET, 0x030, 309 + PIN_FLAG_DEFAULT), 310 + SG2042_GENERAL_PIN(PIN_PCIE2_L1_RESET, 0x030, 311 + PIN_FLAG_WRITE_HIGH), 312 + SG2042_GENERAL_PIN(PIN_PCIE2_L0_WAKEUP, 0x034, 313 + PIN_FLAG_DEFAULT), 314 + SG2042_GENERAL_PIN(PIN_PCIE2_L1_WAKEUP, 0x034, 315 + PIN_FLAG_WRITE_HIGH), 316 + SG2042_GENERAL_PIN(PIN_PCIE2_L0_CLKREQ_IN, 0x038, 317 + PIN_FLAG_DEFAULT), 318 + SG2042_GENERAL_PIN(PIN_PCIE2_L1_CLKREQ_IN, 0x038, 319 + PIN_FLAG_WRITE_HIGH), 320 + SG2042_GENERAL_PIN(PIN_PCIE3_L0_RESET, 0x03c, 321 + PIN_FLAG_DEFAULT), 322 + SG2042_GENERAL_PIN(PIN_PCIE3_L1_RESET, 0x03c, 323 + PIN_FLAG_WRITE_HIGH), 324 + SG2042_GENERAL_PIN(PIN_PCIE3_L0_WAKEUP, 0x040, 325 + PIN_FLAG_DEFAULT), 326 + SG2042_GENERAL_PIN(PIN_PCIE3_L1_WAKEUP, 0x040, 327 + PIN_FLAG_WRITE_HIGH), 328 + SG2042_GENERAL_PIN(PIN_PCIE3_L0_CLKREQ_IN, 0x044, 329 + PIN_FLAG_DEFAULT), 330 + SG2042_GENERAL_PIN(PIN_PCIE3_L1_CLKREQ_IN, 0x044, 331 + PIN_FLAG_WRITE_HIGH), 332 + SG2042_GENERAL_PIN(PIN_PCIE4_L0_RESET, 0x048, 333 + PIN_FLAG_DEFAULT), 334 + SG2042_GENERAL_PIN(PIN_PCIE4_L1_RESET, 0x048, 335 + PIN_FLAG_WRITE_HIGH), 336 + SG2042_GENERAL_PIN(PIN_PCIE4_L0_WAKEUP, 0x04c, 337 + PIN_FLAG_DEFAULT), 338 + SG2042_GENERAL_PIN(PIN_PCIE4_L1_WAKEUP, 0x04c, 339 + PIN_FLAG_WRITE_HIGH), 340 + SG2042_GENERAL_PIN(PIN_PCIE4_L0_CLKREQ_IN, 0x050, 341 + PIN_FLAG_DEFAULT), 342 + SG2042_GENERAL_PIN(PIN_PCIE4_L1_CLKREQ_IN, 0x050, 343 + PIN_FLAG_WRITE_HIGH), 344 + SG2042_GENERAL_PIN(PIN_SPIF0_CLK_SEL1, 0x054, 345 + PIN_FLAG_DEFAULT), 346 + SG2042_GENERAL_PIN(PIN_SPIF0_CLK_SEL0, 0x054, 347 + PIN_FLAG_WRITE_HIGH), 348 + SG2042_GENERAL_PIN(PIN_SPIF0_WP, 0x058, 349 + PIN_FLAG_DEFAULT), 350 + SG2042_GENERAL_PIN(PIN_SPIF0_HOLD, 0x058, 351 + PIN_FLAG_WRITE_HIGH), 352 + SG2042_GENERAL_PIN(PIN_SPIF0_SDI, 0x05c, 353 + PIN_FLAG_DEFAULT), 354 + SG2042_GENERAL_PIN(PIN_SPIF0_CS, 0x05c, 355 + PIN_FLAG_WRITE_HIGH), 356 + SG2042_GENERAL_PIN(PIN_SPIF0_SCK, 0x060, 357 + PIN_FLAG_DEFAULT), 358 + SG2042_GENERAL_PIN(PIN_SPIF0_SDO, 0x060, 359 + PIN_FLAG_WRITE_HIGH), 360 + SG2042_GENERAL_PIN(PIN_SPIF1_CLK_SEL1, 0x064, 361 + PIN_FLAG_DEFAULT), 362 + SG2042_GENERAL_PIN(PIN_SPIF1_CLK_SEL0, 0x064, 363 + PIN_FLAG_WRITE_HIGH), 364 + SG2042_GENERAL_PIN(PIN_SPIF1_WP, 0x068, 365 + PIN_FLAG_DEFAULT), 366 + SG2042_GENERAL_PIN(PIN_SPIF1_HOLD, 0x068, 367 + PIN_FLAG_WRITE_HIGH), 368 + SG2042_GENERAL_PIN(PIN_SPIF1_SDI, 0x06c, 369 + PIN_FLAG_DEFAULT), 370 + SG2042_GENERAL_PIN(PIN_SPIF1_CS, 0x06c, 371 + PIN_FLAG_WRITE_HIGH), 372 + SG2042_GENERAL_PIN(PIN_SPIF1_SCK, 0x070, 373 + PIN_FLAG_DEFAULT), 374 + SG2042_GENERAL_PIN(PIN_SPIF1_SDO, 0x070, 375 + PIN_FLAG_WRITE_HIGH), 376 + SG2042_GENERAL_PIN(PIN_EMMC_WP, 0x074, 377 + PIN_FLAG_DEFAULT), 378 + SG2042_GENERAL_PIN(PIN_EMMC_CD, 0x074, 379 + PIN_FLAG_WRITE_HIGH), 380 + SG2042_GENERAL_PIN(PIN_EMMC_RST, 0x078, 381 + PIN_FLAG_DEFAULT), 382 + SG2042_GENERAL_PIN(PIN_EMMC_PWR_EN, 0x078, 383 + PIN_FLAG_WRITE_HIGH), 384 + SG2042_GENERAL_PIN(PIN_SDIO_CD, 0x07c, 385 + PIN_FLAG_DEFAULT), 386 + SG2042_GENERAL_PIN(PIN_SDIO_WP, 0x07c, 387 + PIN_FLAG_WRITE_HIGH), 388 + SG2042_GENERAL_PIN(PIN_SDIO_RST, 0x080, 389 + PIN_FLAG_DEFAULT), 390 + SG2042_GENERAL_PIN(PIN_SDIO_PWR_EN, 0x080, 391 + PIN_FLAG_WRITE_HIGH), 392 + SG2042_GENERAL_PIN(PIN_RGMII0_TXD0, 0x084, 393 + PIN_FLAG_DEFAULT), 394 + SG2042_GENERAL_PIN(PIN_RGMII0_TXD1, 0x084, 395 + PIN_FLAG_WRITE_HIGH), 396 + SG2042_GENERAL_PIN(PIN_RGMII0_TXD2, 0x088, 397 + PIN_FLAG_DEFAULT), 398 + SG2042_GENERAL_PIN(PIN_RGMII0_TXD3, 0x088, 399 + PIN_FLAG_WRITE_HIGH), 400 + SG2042_GENERAL_PIN(PIN_RGMII0_TXCTRL, 0x08c, 401 + PIN_FLAG_DEFAULT), 402 + SG2042_GENERAL_PIN(PIN_RGMII0_RXD0, 0x08c, 403 + PIN_FLAG_WRITE_HIGH), 404 + SG2042_GENERAL_PIN(PIN_RGMII0_RXD1, 0x090, 405 + PIN_FLAG_DEFAULT), 406 + SG2042_GENERAL_PIN(PIN_RGMII0_RXD2, 0x090, 407 + PIN_FLAG_WRITE_HIGH), 408 + SG2042_GENERAL_PIN(PIN_RGMII0_RXD3, 0x094, 409 + PIN_FLAG_DEFAULT), 410 + SG2042_GENERAL_PIN(PIN_RGMII0_RXCTRL, 0x094, 411 + PIN_FLAG_WRITE_HIGH), 412 + SG2042_GENERAL_PIN(PIN_RGMII0_TXC, 0x098, 413 + PIN_FLAG_DEFAULT), 414 + SG2042_GENERAL_PIN(PIN_RGMII0_RXC, 0x098, 415 + PIN_FLAG_WRITE_HIGH), 416 + SG2042_GENERAL_PIN(PIN_RGMII0_REFCLKO, 0x09c, 417 + PIN_FLAG_DEFAULT), 418 + SG2042_GENERAL_PIN(PIN_RGMII0_IRQ, 0x09c, 419 + PIN_FLAG_WRITE_HIGH), 420 + SG2042_GENERAL_PIN(PIN_RGMII0_MDC, 0x0a0, 421 + PIN_FLAG_DEFAULT), 422 + SG2042_GENERAL_PIN(PIN_RGMII0_MDIO, 0x0a0, 423 + PIN_FLAG_WRITE_HIGH), 424 + SG2042_GENERAL_PIN(PIN_PWM0, 0x0a4, 425 + PIN_FLAG_DEFAULT), 426 + SG2042_GENERAL_PIN(PIN_PWM1, 0x0a4, 427 + PIN_FLAG_WRITE_HIGH), 428 + SG2042_GENERAL_PIN(PIN_PWM2, 0x0a8, 429 + PIN_FLAG_DEFAULT), 430 + SG2042_GENERAL_PIN(PIN_PWM3, 0x0a8, 431 + PIN_FLAG_WRITE_HIGH), 432 + SG2042_GENERAL_PIN(PIN_FAN0, 0x0ac, 433 + PIN_FLAG_DEFAULT), 434 + SG2042_GENERAL_PIN(PIN_FAN1, 0x0ac, 435 + PIN_FLAG_WRITE_HIGH), 436 + SG2042_GENERAL_PIN(PIN_FAN2, 0x0b0, 437 + PIN_FLAG_DEFAULT), 438 + SG2042_GENERAL_PIN(PIN_FAN3, 0x0b0, 439 + PIN_FLAG_WRITE_HIGH), 440 + SG2042_GENERAL_PIN(PIN_IIC0_SDA, 0x0b4, 441 + PIN_FLAG_DEFAULT), 442 + SG2042_GENERAL_PIN(PIN_IIC0_SCL, 0x0b4, 443 + PIN_FLAG_WRITE_HIGH), 444 + SG2042_GENERAL_PIN(PIN_IIC1_SDA, 0x0b8, 445 + PIN_FLAG_DEFAULT), 446 + SG2042_GENERAL_PIN(PIN_IIC1_SCL, 0x0b8, 447 + PIN_FLAG_WRITE_HIGH), 448 + SG2042_GENERAL_PIN(PIN_IIC2_SDA, 0x0bc, 449 + PIN_FLAG_DEFAULT), 450 + SG2042_GENERAL_PIN(PIN_IIC2_SCL, 0x0bc, 451 + PIN_FLAG_WRITE_HIGH), 452 + SG2042_GENERAL_PIN(PIN_IIC3_SDA, 0x0c0, 453 + PIN_FLAG_DEFAULT), 454 + SG2042_GENERAL_PIN(PIN_IIC3_SCL, 0x0c0, 455 + PIN_FLAG_WRITE_HIGH), 456 + SG2042_GENERAL_PIN(PIN_UART0_TX, 0x0c4, 457 + PIN_FLAG_DEFAULT), 458 + SG2042_GENERAL_PIN(PIN_UART0_RX, 0x0c4, 459 + PIN_FLAG_WRITE_HIGH), 460 + SG2042_GENERAL_PIN(PIN_UART0_RTS, 0x0c8, 461 + PIN_FLAG_DEFAULT), 462 + SG2042_GENERAL_PIN(PIN_UART0_CTS, 0x0c8, 463 + PIN_FLAG_WRITE_HIGH), 464 + SG2042_GENERAL_PIN(PIN_UART1_TX, 0x0cc, 465 + PIN_FLAG_DEFAULT), 466 + SG2042_GENERAL_PIN(PIN_UART1_RX, 0x0cc, 467 + PIN_FLAG_WRITE_HIGH), 468 + SG2042_GENERAL_PIN(PIN_UART1_RTS, 0x0d0, 469 + PIN_FLAG_DEFAULT), 470 + SG2042_GENERAL_PIN(PIN_UART1_CTS, 0x0d0, 471 + PIN_FLAG_WRITE_HIGH), 472 + SG2042_GENERAL_PIN(PIN_UART2_TX, 0x0d4, 473 + PIN_FLAG_DEFAULT), 474 + SG2042_GENERAL_PIN(PIN_UART2_RX, 0x0d4, 475 + PIN_FLAG_WRITE_HIGH), 476 + SG2042_GENERAL_PIN(PIN_UART2_RTS, 0x0d8, 477 + PIN_FLAG_DEFAULT), 478 + SG2042_GENERAL_PIN(PIN_UART2_CTS, 0x0d8, 479 + PIN_FLAG_WRITE_HIGH), 480 + SG2042_GENERAL_PIN(PIN_UART3_TX, 0x0dc, 481 + PIN_FLAG_DEFAULT), 482 + SG2042_GENERAL_PIN(PIN_UART3_RX, 0x0dc, 483 + PIN_FLAG_WRITE_HIGH), 484 + SG2042_GENERAL_PIN(PIN_UART3_RTS, 0x0e0, 485 + PIN_FLAG_DEFAULT), 486 + SG2042_GENERAL_PIN(PIN_UART3_CTS, 0x0e0, 487 + PIN_FLAG_WRITE_HIGH), 488 + SG2042_GENERAL_PIN(PIN_SPI0_CS0, 0x0e4, 489 + PIN_FLAG_DEFAULT), 490 + SG2042_GENERAL_PIN(PIN_SPI0_CS1, 0x0e4, 491 + PIN_FLAG_WRITE_HIGH), 492 + SG2042_GENERAL_PIN(PIN_SPI0_SDI, 0x0e8, 493 + PIN_FLAG_DEFAULT), 494 + SG2042_GENERAL_PIN(PIN_SPI0_SDO, 0x0e8, 495 + PIN_FLAG_WRITE_HIGH), 496 + SG2042_GENERAL_PIN(PIN_SPI0_SCK, 0x0ec, 497 + PIN_FLAG_DEFAULT), 498 + SG2042_GENERAL_PIN(PIN_SPI1_CS0, 0x0ec, 499 + PIN_FLAG_WRITE_HIGH), 500 + SG2042_GENERAL_PIN(PIN_SPI1_CS1, 0x0f0, 501 + PIN_FLAG_DEFAULT), 502 + SG2042_GENERAL_PIN(PIN_SPI1_SDI, 0x0f0, 503 + PIN_FLAG_WRITE_HIGH), 504 + SG2042_GENERAL_PIN(PIN_SPI1_SDO, 0x0f4, 505 + PIN_FLAG_DEFAULT), 506 + SG2042_GENERAL_PIN(PIN_SPI1_SCK, 0x0f4, 507 + PIN_FLAG_WRITE_HIGH), 508 + SG2042_GENERAL_PIN(PIN_JTAG0_TDO, 0x0f8, 509 + PIN_FLAG_DEFAULT), 510 + SG2042_GENERAL_PIN(PIN_JTAG0_TCK, 0x0f8, 511 + PIN_FLAG_WRITE_HIGH), 512 + SG2042_GENERAL_PIN(PIN_JTAG0_TDI, 0x0fc, 513 + PIN_FLAG_DEFAULT), 514 + SG2042_GENERAL_PIN(PIN_JTAG0_TMS, 0x0fc, 515 + PIN_FLAG_WRITE_HIGH), 516 + SG2042_GENERAL_PIN(PIN_JTAG0_TRST, 0x100, 517 + PIN_FLAG_DEFAULT), 518 + SG2042_GENERAL_PIN(PIN_JTAG0_SRST, 0x100, 519 + PIN_FLAG_WRITE_HIGH), 520 + SG2042_GENERAL_PIN(PIN_JTAG1_TDO, 0x104, 521 + PIN_FLAG_DEFAULT), 522 + SG2042_GENERAL_PIN(PIN_JTAG1_TCK, 0x104, 523 + PIN_FLAG_WRITE_HIGH), 524 + SG2042_GENERAL_PIN(PIN_JTAG1_TDI, 0x108, 525 + PIN_FLAG_DEFAULT), 526 + SG2042_GENERAL_PIN(PIN_JTAG1_TMS, 0x108, 527 + PIN_FLAG_WRITE_HIGH), 528 + SG2042_GENERAL_PIN(PIN_JTAG1_TRST, 0x10c, 529 + PIN_FLAG_DEFAULT), 530 + SG2042_GENERAL_PIN(PIN_JTAG1_SRST, 0x10c, 531 + PIN_FLAG_WRITE_HIGH), 532 + SG2042_GENERAL_PIN(PIN_JTAG2_TDO, 0x110, 533 + PIN_FLAG_DEFAULT), 534 + SG2042_GENERAL_PIN(PIN_JTAG2_TCK, 0x110, 535 + PIN_FLAG_WRITE_HIGH), 536 + SG2042_GENERAL_PIN(PIN_JTAG2_TDI, 0x114, 537 + PIN_FLAG_DEFAULT), 538 + SG2042_GENERAL_PIN(PIN_JTAG2_TMS, 0x114, 539 + PIN_FLAG_WRITE_HIGH), 540 + SG2042_GENERAL_PIN(PIN_JTAG2_TRST, 0x118, 541 + PIN_FLAG_DEFAULT), 542 + SG2042_GENERAL_PIN(PIN_JTAG2_SRST, 0x118, 543 + PIN_FLAG_WRITE_HIGH), 544 + SG2042_GENERAL_PIN(PIN_JTAG3_TDO, 0x11c, 545 + PIN_FLAG_DEFAULT), 546 + SG2042_GENERAL_PIN(PIN_JTAG3_TCK, 0x11c, 547 + PIN_FLAG_WRITE_HIGH), 548 + SG2042_GENERAL_PIN(PIN_JTAG3_TDI, 0x120, 549 + PIN_FLAG_DEFAULT), 550 + SG2042_GENERAL_PIN(PIN_JTAG3_TMS, 0x120, 551 + PIN_FLAG_WRITE_HIGH), 552 + SG2042_GENERAL_PIN(PIN_JTAG3_TRST, 0x124, 553 + PIN_FLAG_DEFAULT), 554 + SG2042_GENERAL_PIN(PIN_JTAG3_SRST, 0x124, 555 + PIN_FLAG_WRITE_HIGH), 556 + SG2042_GENERAL_PIN(PIN_GPIO0, 0x128, 557 + PIN_FLAG_DEFAULT), 558 + SG2042_GENERAL_PIN(PIN_GPIO1, 0x128, 559 + PIN_FLAG_WRITE_HIGH), 560 + SG2042_GENERAL_PIN(PIN_GPIO2, 0x12c, 561 + PIN_FLAG_DEFAULT), 562 + SG2042_GENERAL_PIN(PIN_GPIO3, 0x12c, 563 + PIN_FLAG_WRITE_HIGH), 564 + SG2042_GENERAL_PIN(PIN_GPIO4, 0x130, 565 + PIN_FLAG_DEFAULT), 566 + SG2042_GENERAL_PIN(PIN_GPIO5, 0x130, 567 + PIN_FLAG_WRITE_HIGH), 568 + SG2042_GENERAL_PIN(PIN_GPIO6, 0x134, 569 + PIN_FLAG_DEFAULT), 570 + SG2042_GENERAL_PIN(PIN_GPIO7, 0x134, 571 + PIN_FLAG_WRITE_HIGH), 572 + SG2042_GENERAL_PIN(PIN_GPIO8, 0x138, 573 + PIN_FLAG_DEFAULT), 574 + SG2042_GENERAL_PIN(PIN_GPIO9, 0x138, 575 + PIN_FLAG_WRITE_HIGH), 576 + SG2042_GENERAL_PIN(PIN_GPIO10, 0x13c, 577 + PIN_FLAG_DEFAULT), 578 + SG2042_GENERAL_PIN(PIN_GPIO11, 0x13c, 579 + PIN_FLAG_WRITE_HIGH), 580 + SG2042_GENERAL_PIN(PIN_GPIO12, 0x140, 581 + PIN_FLAG_DEFAULT), 582 + SG2042_GENERAL_PIN(PIN_GPIO13, 0x140, 583 + PIN_FLAG_WRITE_HIGH), 584 + SG2042_GENERAL_PIN(PIN_GPIO14, 0x144, 585 + PIN_FLAG_DEFAULT), 586 + SG2042_GENERAL_PIN(PIN_GPIO15, 0x144, 587 + PIN_FLAG_WRITE_HIGH), 588 + SG2042_GENERAL_PIN(PIN_GPIO16, 0x148, 589 + PIN_FLAG_DEFAULT), 590 + SG2042_GENERAL_PIN(PIN_GPIO17, 0x148, 591 + PIN_FLAG_WRITE_HIGH), 592 + SG2042_GENERAL_PIN(PIN_GPIO18, 0x14c, 593 + PIN_FLAG_DEFAULT), 594 + SG2042_GENERAL_PIN(PIN_GPIO19, 0x14c, 595 + PIN_FLAG_WRITE_HIGH), 596 + SG2042_GENERAL_PIN(PIN_GPIO20, 0x150, 597 + PIN_FLAG_DEFAULT), 598 + SG2042_GENERAL_PIN(PIN_GPIO21, 0x150, 599 + PIN_FLAG_WRITE_HIGH), 600 + SG2042_GENERAL_PIN(PIN_GPIO22, 0x154, 601 + PIN_FLAG_DEFAULT), 602 + SG2042_GENERAL_PIN(PIN_GPIO23, 0x154, 603 + PIN_FLAG_WRITE_HIGH), 604 + SG2042_GENERAL_PIN(PIN_GPIO24, 0x158, 605 + PIN_FLAG_DEFAULT), 606 + SG2042_GENERAL_PIN(PIN_GPIO25, 0x158, 607 + PIN_FLAG_WRITE_HIGH), 608 + SG2042_GENERAL_PIN(PIN_GPIO26, 0x15c, 609 + PIN_FLAG_DEFAULT), 610 + SG2042_GENERAL_PIN(PIN_GPIO27, 0x15c, 611 + PIN_FLAG_WRITE_HIGH), 612 + SG2042_GENERAL_PIN(PIN_GPIO28, 0x160, 613 + PIN_FLAG_DEFAULT), 614 + SG2042_GENERAL_PIN(PIN_GPIO29, 0x160, 615 + PIN_FLAG_WRITE_HIGH), 616 + SG2042_GENERAL_PIN(PIN_GPIO30, 0x164, 617 + PIN_FLAG_DEFAULT), 618 + SG2042_GENERAL_PIN(PIN_GPIO31, 0x164, 619 + PIN_FLAG_WRITE_HIGH), 620 + SG2042_GENERAL_PIN(PIN_MODE_SEL0, 0x168, 621 + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), 622 + SG2042_GENERAL_PIN(PIN_MODE_SEL1, 0x168, 623 + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | 624 + PIN_FLAG_NO_OEX_EN), 625 + SG2042_GENERAL_PIN(PIN_MODE_SEL2, 0x16c, 626 + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), 627 + SG2042_GENERAL_PIN(PIN_BOOT_SEL0, 0x16c, 628 + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | 629 + PIN_FLAG_NO_OEX_EN), 630 + SG2042_GENERAL_PIN(PIN_BOOT_SEL1, 0x170, 631 + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), 632 + SG2042_GENERAL_PIN(PIN_BOOT_SEL2, 0x170, 633 + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | 634 + PIN_FLAG_NO_OEX_EN), 635 + SG2042_GENERAL_PIN(PIN_BOOT_SEL3, 0x174, 636 + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), 637 + SG2042_GENERAL_PIN(PIN_BOOT_SEL4, 0x174, 638 + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | 639 + PIN_FLAG_NO_OEX_EN), 640 + SG2042_GENERAL_PIN(PIN_BOOT_SEL5, 0x178, 641 + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), 642 + SG2042_GENERAL_PIN(PIN_BOOT_SEL6, 0x178, 643 + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | 644 + PIN_FLAG_NO_OEX_EN), 645 + SG2042_GENERAL_PIN(PIN_BOOT_SEL7, 0x17c, 646 + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), 647 + SG2042_GENERAL_PIN(PIN_MULTI_SCKT, 0x17c, 648 + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | 649 + PIN_FLAG_NO_OEX_EN), 650 + SG2042_GENERAL_PIN(PIN_SCKT_ID0, 0x180, 651 + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), 652 + SG2042_GENERAL_PIN(PIN_SCKT_ID1, 0x180, 653 + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | 654 + PIN_FLAG_NO_OEX_EN), 655 + SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_MAIN, 0x184, 656 + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), 657 + SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_DDR_0, 0x184, 658 + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | 659 + PIN_FLAG_NO_OEX_EN), 660 + SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_DDR_1, 0x188, 661 + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), 662 + SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_DDR_2, 0x188, 663 + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | 664 + PIN_FLAG_NO_OEX_EN), 665 + SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_DDR_3, 0x18c, 666 + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), 667 + SG2042_GENERAL_PIN(PIN_XTAL_32K, 0x18c, 668 + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | 669 + PIN_FLAG_NO_OEX_EN), 670 + SG2042_GENERAL_PIN(PIN_SYS_RST, 0x190, 671 + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), 672 + SG2042_GENERAL_PIN(PIN_PWR_BUTTON, 0x190, 673 + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | 674 + PIN_FLAG_NO_OEX_EN), 675 + SG2042_GENERAL_PIN(PIN_TEST_EN, 0x194, 676 + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), 677 + SG2042_GENERAL_PIN(PIN_TEST_MODE_MBIST, 0x194, 678 + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | 679 + PIN_FLAG_NO_OEX_EN), 680 + SG2042_GENERAL_PIN(PIN_TEST_MODE_SCAN, 0x198, 681 + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), 682 + SG2042_GENERAL_PIN(PIN_TEST_MODE_BSD, 0x198, 683 + PIN_FLAG_WRITE_HIGH | PIN_FLAG_NO_PINMUX | 684 + PIN_FLAG_NO_OEX_EN), 685 + SG2042_GENERAL_PIN(PIN_BISR_BYP, 0x19c, 686 + PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN), 687 + }; 688 + 689 + static const struct sophgo_pinctrl_data sg2044_pindata = { 690 + .pins = sg2044_pins, 691 + .pindata = sg2044_pin_data, 692 + .vddio_ops = &sg2044_vddio_cfg_ops, 693 + .cfg_ops = &sg2042_cfg_ops, 694 + .pctl_ops = &sg2042_pctrl_ops, 695 + .pmx_ops = &sg2042_pmx_ops, 696 + .pconf_ops = &sg2042_pconf_ops, 697 + .npins = ARRAY_SIZE(sg2044_pins), 698 + .pinsize = sizeof(struct sg2042_pin), 699 + }; 700 + 701 + static const struct of_device_id sg2044_pinctrl_ids[] = { 702 + { .compatible = "sophgo,sg2044-pinctrl", .data = &sg2044_pindata }, 703 + { } 704 + }; 705 + MODULE_DEVICE_TABLE(of, sg2044_pinctrl_ids); 706 + 707 + static struct platform_driver sg2044_pinctrl_driver = { 708 + .probe = sophgo_pinctrl_probe, 709 + .driver = { 710 + .name = "sg2044-pinctrl", 711 + .suppress_bind_attrs = true, 712 + .of_match_table = sg2044_pinctrl_ids, 713 + }, 714 + }; 715 + module_platform_driver(sg2044_pinctrl_driver); 716 + 717 + MODULE_DESCRIPTION("Pinctrl driver for the SG2002 series SoC"); 718 + MODULE_LICENSE("GPL");