tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
pinctrl: sophgo: add support for SG2042 SoC
Add base driver for SG2042 SoC and pin definition.
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Link: https://lore.kernel.org/20250211051801.470800-7-inochiama@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
authored by
Inochi Amaoto
and committed by
Linus Walleij
1e67465d
68ea8c87
+1017
+15
drivers/pinctrl/sophgo/Kconfig
+15
drivers/pinctrl/sophgo/Kconfig
···
59
59
This pin controller allows selecting the mux function for
60
60
each pin. This driver can also be built as a module called
61
61
pinctrl-sg2002.
62
+
63
+
config PINCTRL_SOPHGO_SG2042_OPS
64
+
bool
65
+
66
+
config PINCTRL_SOPHGO_SG2042
67
+
tristate "Sophgo SG2042 SoC Pinctrl driver"
68
+
depends on ARCH_SOPHGO || COMPILE_TEST
69
+
depends on OF
70
+
select PINCTRL_SOPHGO_COMMON
71
+
select PINCTRL_SOPHGO_SG2042_OPS
72
+
help
73
+
Say Y to select the pinctrl driver for SG2042 SoC.
74
+
This pin controller allows selecting the mux function for
75
+
each pin. This driver can also be built as a module called
76
+
pinctrl-sg2042.
+2
drivers/pinctrl/sophgo/Makefile
+2
drivers/pinctrl/sophgo/Makefile
···
3
3
obj-$(CONFIG_PINCTRL_SOPHGO_COMMON) += pinctrl-sophgo.o
4
4
pinctrl-sophgo-objs += pinctrl-sophgo-common.o
5
5
pinctrl-sophgo-$(CONFIG_PINCTRL_SOPHGO_CV18XX_OPS) += pinctrl-cv18xx.o
6
+
pinctrl-sophgo-$(CONFIG_PINCTRL_SOPHGO_SG2042_OPS) += pinctrl-sg2042-ops.o
6
7
7
8
obj-$(CONFIG_PINCTRL_SOPHGO_CV1800B) += pinctrl-cv1800b.o
8
9
obj-$(CONFIG_PINCTRL_SOPHGO_CV1812H) += pinctrl-cv1812h.o
9
10
obj-$(CONFIG_PINCTRL_SOPHGO_SG2000) += pinctrl-sg2000.o
10
11
obj-$(CONFIG_PINCTRL_SOPHGO_SG2002) += pinctrl-sg2002.o
12
+
obj-$(CONFIG_PINCTRL_SOPHGO_SG2042) += pinctrl-sg2042.o
+296
drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c
+296
drivers/pinctrl/sophgo/pinctrl-sg2042-ops.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Sophgo sg2042 SoCs pinctrl driver.
4
+
*
5
+
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
6
+
*
7
+
*/
8
+
9
+
#include <linux/bitfield.h>
10
+
#include <linux/bits.h>
11
+
#include <linux/cleanup.h>
12
+
#include <linux/export.h>
13
+
#include <linux/io.h>
14
+
#include <linux/of.h>
15
+
#include <linux/platform_device.h>
16
+
#include <linux/seq_file.h>
17
+
#include <linux/spinlock.h>
18
+
19
+
#include <linux/pinctrl/pinconf-generic.h>
20
+
#include <linux/pinctrl/pinconf.h>
21
+
#include <linux/pinctrl/pinctrl.h>
22
+
#include <linux/pinctrl/pinmux.h>
23
+
24
+
#include "../pinctrl-utils.h"
25
+
#include "../pinmux.h"
26
+
27
+
#include "pinctrl-sg2042.h"
28
+
29
+
#define PIN_IO_PULL_ONE_ENABLE BIT(0)
30
+
#define PIN_IO_PULL_DIR_UP (BIT(1) | PIN_IO_PULL_ONE_ENABLE)
31
+
#define PIN_IO_PULL_DIR_DOWN (0 | PIN_IO_PULL_ONE_ENABLE)
32
+
#define PIN_IO_PULL_ONE_MASK GENMASK(1, 0)
33
+
34
+
#define PIN_IO_PULL_UP BIT(2)
35
+
#define PIN_IO_PULL_UP_DONW BIT(3)
36
+
#define PIN_IO_PULL_UP_MASK GENMASK(3, 2)
37
+
38
+
#define PIN_IO_MUX GENMASK(5, 4)
39
+
#define PIN_IO_DRIVE GENMASK(9, 6)
40
+
#define PIN_IO_SCHMITT_ENABLE BIT(10)
41
+
#define PIN_IO_OUTPUT_ENABLE BIT(11)
42
+
43
+
struct sg2042_priv {
44
+
void __iomem *regs;
45
+
};
46
+
47
+
static u8 sg2042_dt_get_pin_mux(u32 value)
48
+
{
49
+
return value >> 16;
50
+
}
51
+
52
+
static inline u32 sg2042_get_pin_reg(struct sophgo_pinctrl *pctrl,
53
+
const struct sophgo_pin *sp)
54
+
{
55
+
struct sg2042_priv *priv = pctrl->priv_ctrl;
56
+
const struct sg2042_pin *pin = sophgo_to_sg2042_pin(sp);
57
+
void __iomem *reg = priv->regs + pin->offset;
58
+
59
+
if (sp->flags & PIN_FLAG_WRITE_HIGH)
60
+
return readl(reg) >> 16;
61
+
else
62
+
return readl(reg) & 0xffff;
63
+
}
64
+
65
+
static int sg2042_set_pin_reg(struct sophgo_pinctrl *pctrl,
66
+
const struct sophgo_pin *sp,
67
+
u32 value, u32 mask)
68
+
{
69
+
struct sg2042_priv *priv = pctrl->priv_ctrl;
70
+
const struct sg2042_pin *pin = sophgo_to_sg2042_pin(sp);
71
+
void __iomem *reg = priv->regs + pin->offset;
72
+
u32 v = readl(reg);
73
+
74
+
if (sp->flags & PIN_FLAG_WRITE_HIGH) {
75
+
v &= ~(mask << 16);
76
+
v |= value << 16;
77
+
} else {
78
+
v &= ~mask;
79
+
v |= value;
80
+
}
81
+
82
+
writel(v, reg);
83
+
84
+
return 0;
85
+
}
86
+
87
+
static void sg2042_pctrl_dbg_show(struct pinctrl_dev *pctldev,
88
+
struct seq_file *seq, unsigned int pin_id)
89
+
{
90
+
struct sophgo_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
91
+
const struct sophgo_pin *sp = sophgo_get_pin(pctrl, pin_id);
92
+
u32 value, mux;
93
+
94
+
value = sg2042_get_pin_reg(pctrl, sp);
95
+
mux = FIELD_GET(PIN_IO_MUX, value);
96
+
seq_printf(seq, "mux:%u reg:0x%04x ", mux, value);
97
+
}
98
+
99
+
const struct pinctrl_ops sg2042_pctrl_ops = {
100
+
.get_groups_count = pinctrl_generic_get_group_count,
101
+
.get_group_name = pinctrl_generic_get_group_name,
102
+
.get_group_pins = pinctrl_generic_get_group_pins,
103
+
.pin_dbg_show = sg2042_pctrl_dbg_show,
104
+
.dt_node_to_map = sophgo_pctrl_dt_node_to_map,
105
+
.dt_free_map = pinctrl_utils_free_map,
106
+
};
107
+
EXPORT_SYMBOL_GPL(sg2042_pctrl_ops);
108
+
109
+
static void sg2042_set_pinmux_config(struct sophgo_pinctrl *pctrl,
110
+
const struct sophgo_pin *sp, u32 config)
111
+
{
112
+
u32 mux = sg2042_dt_get_pin_mux(config);
113
+
114
+
if (!(sp->flags & PIN_FLAG_NO_PINMUX))
115
+
sg2042_set_pin_reg(pctrl, sp, mux, PIN_IO_MUX);
116
+
}
117
+
118
+
const struct pinmux_ops sg2042_pmx_ops = {
119
+
.get_functions_count = pinmux_generic_get_function_count,
120
+
.get_function_name = pinmux_generic_get_function_name,
121
+
.get_function_groups = pinmux_generic_get_function_groups,
122
+
.set_mux = sophgo_pmx_set_mux,
123
+
.strict = true,
124
+
};
125
+
EXPORT_SYMBOL_GPL(sg2042_pmx_ops);
126
+
127
+
static int sg2042_pconf_get(struct pinctrl_dev *pctldev,
128
+
unsigned int pin_id, unsigned long *config)
129
+
{
130
+
struct sophgo_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
131
+
int param = pinconf_to_config_param(*config);
132
+
const struct sophgo_pin *sp = sophgo_get_pin(pctrl, pin_id);
133
+
u32 value;
134
+
u32 arg;
135
+
bool enabled;
136
+
int ret;
137
+
138
+
if (!sp)
139
+
return -EINVAL;
140
+
141
+
value = sg2042_get_pin_reg(pctrl, sp);
142
+
143
+
switch (param) {
144
+
case PIN_CONFIG_BIAS_DISABLE:
145
+
if (sp->flags & PIN_FLAG_ONLY_ONE_PULL)
146
+
arg = FIELD_GET(PIN_IO_PULL_ONE_ENABLE, value);
147
+
else
148
+
arg = FIELD_GET(PIN_IO_PULL_UP_MASK, value);
149
+
enabled = arg == 0;
150
+
break;
151
+
case PIN_CONFIG_BIAS_PULL_DOWN:
152
+
if (sp->flags & PIN_FLAG_ONLY_ONE_PULL) {
153
+
arg = FIELD_GET(PIN_IO_PULL_ONE_MASK, value);
154
+
enabled = arg == PIN_IO_PULL_DIR_DOWN;
155
+
} else {
156
+
enabled = FIELD_GET(PIN_IO_PULL_UP_DONW, value) != 0;
157
+
}
158
+
arg = sophgo_pinctrl_typical_pull_down(pctrl, sp, NULL);
159
+
break;
160
+
case PIN_CONFIG_BIAS_PULL_UP:
161
+
if (sp->flags & PIN_FLAG_ONLY_ONE_PULL) {
162
+
arg = FIELD_GET(PIN_IO_PULL_ONE_MASK, value);
163
+
enabled = arg == PIN_IO_PULL_DIR_UP;
164
+
} else {
165
+
enabled = FIELD_GET(PIN_IO_PULL_UP, value) != 0;
166
+
}
167
+
arg = sophgo_pinctrl_typical_pull_up(pctrl, sp, NULL);
168
+
break;
169
+
case PIN_CONFIG_DRIVE_STRENGTH_UA:
170
+
enabled = FIELD_GET(PIN_IO_OUTPUT_ENABLE, value) != 0;
171
+
arg = FIELD_GET(PIN_IO_DRIVE, value);
172
+
ret = sophgo_pinctrl_reg2oc(pctrl, sp, NULL, arg);
173
+
if (ret < 0)
174
+
return ret;
175
+
arg = ret;
176
+
break;
177
+
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
178
+
arg = FIELD_GET(PIN_IO_SCHMITT_ENABLE, value);
179
+
enabled = arg != 0;
180
+
break;
181
+
default:
182
+
return -ENOTSUPP;
183
+
}
184
+
185
+
*config = pinconf_to_config_packed(param, arg);
186
+
187
+
return enabled ? 0 : -EINVAL;
188
+
}
189
+
190
+
static int sg2042_pinconf_compute_config(struct sophgo_pinctrl *pctrl,
191
+
const struct sophgo_pin *sp,
192
+
unsigned long *configs,
193
+
unsigned int num_configs,
194
+
u32 *value, u32 *mask)
195
+
{
196
+
int i;
197
+
u16 v = 0, m = 0;
198
+
int ret;
199
+
200
+
if (!sp)
201
+
return -EINVAL;
202
+
203
+
for (i = 0; i < num_configs; i++) {
204
+
int param = pinconf_to_config_param(configs[i]);
205
+
u32 arg = pinconf_to_config_argument(configs[i]);
206
+
207
+
switch (param) {
208
+
case PIN_CONFIG_BIAS_DISABLE:
209
+
if (sp->flags & PIN_FLAG_ONLY_ONE_PULL) {
210
+
v &= ~PIN_IO_PULL_ONE_ENABLE;
211
+
m |= PIN_IO_PULL_ONE_ENABLE;
212
+
} else {
213
+
v &= ~PIN_IO_PULL_UP_MASK;
214
+
m |= PIN_IO_PULL_UP_MASK;
215
+
}
216
+
break;
217
+
case PIN_CONFIG_BIAS_PULL_DOWN:
218
+
if (sp->flags & PIN_FLAG_ONLY_ONE_PULL) {
219
+
v &= ~PIN_IO_PULL_ONE_MASK;
220
+
v |= PIN_IO_PULL_DIR_DOWN;
221
+
m |= PIN_IO_PULL_ONE_MASK;
222
+
} else {
223
+
v |= PIN_IO_PULL_UP_DONW;
224
+
m |= PIN_IO_PULL_UP_DONW;
225
+
}
226
+
break;
227
+
case PIN_CONFIG_BIAS_PULL_UP:
228
+
if (sp->flags & PIN_FLAG_ONLY_ONE_PULL) {
229
+
v &= ~PIN_IO_PULL_ONE_MASK;
230
+
v |= PIN_IO_PULL_DIR_UP;
231
+
m |= PIN_IO_PULL_ONE_MASK;
232
+
} else {
233
+
v |= PIN_IO_PULL_UP;
234
+
m |= PIN_IO_PULL_UP;
235
+
}
236
+
break;
237
+
case PIN_CONFIG_DRIVE_STRENGTH_UA:
238
+
v &= ~(PIN_IO_DRIVE | PIN_IO_OUTPUT_ENABLE);
239
+
if (arg != 0) {
240
+
ret = sophgo_pinctrl_oc2reg(pctrl, sp, NULL, arg);
241
+
if (ret < 0)
242
+
return ret;
243
+
if (!(sp->flags & PIN_FLAG_NO_OEX_EN))
244
+
v |= PIN_IO_OUTPUT_ENABLE;
245
+
v |= FIELD_PREP(PIN_IO_DRIVE, ret);
246
+
}
247
+
m |= PIN_IO_DRIVE | PIN_IO_OUTPUT_ENABLE;
248
+
break;
249
+
case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
250
+
v |= PIN_IO_SCHMITT_ENABLE;
251
+
m |= PIN_IO_SCHMITT_ENABLE;
252
+
break;
253
+
default:
254
+
return -ENOTSUPP;
255
+
}
256
+
}
257
+
258
+
*value = v;
259
+
*mask = m;
260
+
261
+
return 0;
262
+
}
263
+
264
+
const struct pinconf_ops sg2042_pconf_ops = {
265
+
.pin_config_get = sg2042_pconf_get,
266
+
.pin_config_set = sophgo_pconf_set,
267
+
.pin_config_group_set = sophgo_pconf_group_set,
268
+
.is_generic = true,
269
+
};
270
+
EXPORT_SYMBOL_GPL(sg2042_pconf_ops);
271
+
272
+
static int sophgo_pinctrl_init(struct platform_device *pdev,
273
+
struct sophgo_pinctrl *pctrl)
274
+
{
275
+
struct sg2042_priv *priv;
276
+
277
+
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
278
+
if (!priv)
279
+
return -ENOMEM;
280
+
281
+
priv->regs = devm_platform_ioremap_resource(pdev, 0);
282
+
if (IS_ERR(priv->regs))
283
+
return PTR_ERR(priv->regs);
284
+
285
+
pctrl->priv_ctrl = priv;
286
+
287
+
return 0;
288
+
}
289
+
290
+
const struct sophgo_cfg_ops sg2042_cfg_ops = {
291
+
.pctrl_init = sophgo_pinctrl_init,
292
+
.compute_pinconf_config = sg2042_pinconf_compute_config,
293
+
.set_pinconf_config = sg2042_set_pin_reg,
294
+
.set_pinmux_config = sg2042_set_pinmux_config,
295
+
};
296
+
EXPORT_SYMBOL_GPL(sg2042_cfg_ops);
+655
drivers/pinctrl/sophgo/pinctrl-sg2042.c
+655
drivers/pinctrl/sophgo/pinctrl-sg2042.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Sophgo SG2042 SoC pinctrl driver.
4
+
*
5
+
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
6
+
*/
7
+
8
+
#include <linux/module.h>
9
+
#include <linux/platform_device.h>
10
+
#include <linux/of.h>
11
+
12
+
#include <linux/pinctrl/pinctrl.h>
13
+
#include <linux/pinctrl/pinmux.h>
14
+
15
+
#include <dt-bindings/pinctrl/pinctrl-sg2042.h>
16
+
17
+
#include "pinctrl-sg2042.h"
18
+
19
+
static int sg2042_get_pull_up(const struct sophgo_pin *sp, const u32 *psmap)
20
+
{
21
+
return 35000;
22
+
}
23
+
24
+
static int sg2042_get_pull_down(const struct sophgo_pin *sp, const u32 *psmap)
25
+
{
26
+
return 28000;
27
+
}
28
+
29
+
static const u32 sg2042_oc_map[] = {
30
+
5400, 8100, 10700, 13400,
31
+
16100, 18800, 21400, 24100,
32
+
26800, 29400, 32100, 34800,
33
+
37400, 40100, 42800, 45400
34
+
};
35
+
36
+
static int sg2042_get_oc_map(const struct sophgo_pin *sp, const u32 *psmap,
37
+
const u32 **map)
38
+
{
39
+
*map = sg2042_oc_map;
40
+
return ARRAY_SIZE(sg2042_oc_map);
41
+
}
42
+
43
+
static const struct sophgo_vddio_cfg_ops sg2042_vddio_cfg_ops = {
44
+
.get_pull_up = sg2042_get_pull_up,
45
+
.get_pull_down = sg2042_get_pull_down,
46
+
.get_oc_map = sg2042_get_oc_map,
47
+
};
48
+
49
+
static const struct pinctrl_pin_desc sg2042_pins[] = {
50
+
PINCTRL_PIN(PIN_LPC_LCLK, "lpc_lclk"),
51
+
PINCTRL_PIN(PIN_LPC_LFRAME, "lpc_lframe"),
52
+
PINCTRL_PIN(PIN_LPC_LAD0, "lpc_lad0"),
53
+
PINCTRL_PIN(PIN_LPC_LAD1, "lpc_lad1"),
54
+
PINCTRL_PIN(PIN_LPC_LAD2, "lpc_lad2"),
55
+
PINCTRL_PIN(PIN_LPC_LAD3, "lpc_lad3"),
56
+
PINCTRL_PIN(PIN_LPC_LDRQ0, "lpc_ldrq0"),
57
+
PINCTRL_PIN(PIN_LPC_LDRQ1, "lpc_ldrq1"),
58
+
PINCTRL_PIN(PIN_LPC_SERIRQ, "lpc_serirq"),
59
+
PINCTRL_PIN(PIN_LPC_CLKRUN, "lpc_clkrun"),
60
+
PINCTRL_PIN(PIN_LPC_LPME, "lpc_lpme"),
61
+
PINCTRL_PIN(PIN_LPC_LPCPD, "lpc_lpcpd"),
62
+
PINCTRL_PIN(PIN_LPC_LSMI, "lpc_lsmi"),
63
+
PINCTRL_PIN(PIN_PCIE0_L0_RESET, "pcie0_l0_reset"),
64
+
PINCTRL_PIN(PIN_PCIE0_L1_RESET, "pcie0_l1_reset"),
65
+
PINCTRL_PIN(PIN_PCIE0_L0_WAKEUP, "pcie0_l0_wakeup"),
66
+
PINCTRL_PIN(PIN_PCIE0_L1_WAKEUP, "pcie0_l1_wakeup"),
67
+
PINCTRL_PIN(PIN_PCIE0_L0_CLKREQ_IN, "pcie0_l0_clkreq_in"),
68
+
PINCTRL_PIN(PIN_PCIE0_L1_CLKREQ_IN, "pcie0_l1_clkreq_in"),
69
+
PINCTRL_PIN(PIN_PCIE1_L0_RESET, "pcie1_l0_reset"),
70
+
PINCTRL_PIN(PIN_PCIE1_L1_RESET, "pcie1_l1_reset"),
71
+
PINCTRL_PIN(PIN_PCIE1_L0_WAKEUP, "pcie1_l0_wakeup"),
72
+
PINCTRL_PIN(PIN_PCIE1_L1_WAKEUP, "pcie1_l1_wakeup"),
73
+
PINCTRL_PIN(PIN_PCIE1_L0_CLKREQ_IN, "pcie1_l0_clkreq_in"),
74
+
PINCTRL_PIN(PIN_PCIE1_L1_CLKREQ_IN, "pcie1_l1_clkreq_in"),
75
+
PINCTRL_PIN(PIN_SPIF0_CLK_SEL1, "spif0_clk_sel1"),
76
+
PINCTRL_PIN(PIN_SPIF0_CLK_SEL0, "spif0_clk_sel0"),
77
+
PINCTRL_PIN(PIN_SPIF0_WP, "spif0_wp"),
78
+
PINCTRL_PIN(PIN_SPIF0_HOLD, "spif0_hold"),
79
+
PINCTRL_PIN(PIN_SPIF0_SDI, "spif0_sdi"),
80
+
PINCTRL_PIN(PIN_SPIF0_CS, "spif0_cs"),
81
+
PINCTRL_PIN(PIN_SPIF0_SCK, "spif0_sck"),
82
+
PINCTRL_PIN(PIN_SPIF0_SDO, "spif0_sdo"),
83
+
PINCTRL_PIN(PIN_SPIF1_CLK_SEL1, "spif1_clk_sel1"),
84
+
PINCTRL_PIN(PIN_SPIF1_CLK_SEL0, "spif1_clk_sel0"),
85
+
PINCTRL_PIN(PIN_SPIF1_WP, "spif1_wp"),
86
+
PINCTRL_PIN(PIN_SPIF1_HOLD, "spif1_hold"),
87
+
PINCTRL_PIN(PIN_SPIF1_SDI, "spif1_sdi"),
88
+
PINCTRL_PIN(PIN_SPIF1_CS, "spif1_cs"),
89
+
PINCTRL_PIN(PIN_SPIF1_SCK, "spif1_sck"),
90
+
PINCTRL_PIN(PIN_SPIF1_SDO, "spif1_sdo"),
91
+
PINCTRL_PIN(PIN_EMMC_WP, "emmc_wp"),
92
+
PINCTRL_PIN(PIN_EMMC_CD, "emmc_cd"),
93
+
PINCTRL_PIN(PIN_EMMC_RST, "emmc_rst"),
94
+
PINCTRL_PIN(PIN_EMMC_PWR_EN, "emmc_pwr_en"),
95
+
PINCTRL_PIN(PIN_SDIO_CD, "sdio_cd"),
96
+
PINCTRL_PIN(PIN_SDIO_WP, "sdio_wp"),
97
+
PINCTRL_PIN(PIN_SDIO_RST, "sdio_rst"),
98
+
PINCTRL_PIN(PIN_SDIO_PWR_EN, "sdio_pwr_en"),
99
+
PINCTRL_PIN(PIN_RGMII0_TXD0, "rgmii0_txd0"),
100
+
PINCTRL_PIN(PIN_RGMII0_TXD1, "rgmii0_txd1"),
101
+
PINCTRL_PIN(PIN_RGMII0_TXD2, "rgmii0_txd2"),
102
+
PINCTRL_PIN(PIN_RGMII0_TXD3, "rgmii0_txd3"),
103
+
PINCTRL_PIN(PIN_RGMII0_TXCTRL, "rgmii0_txctrl"),
104
+
PINCTRL_PIN(PIN_RGMII0_RXD0, "rgmii0_rxd0"),
105
+
PINCTRL_PIN(PIN_RGMII0_RXD1, "rgmii0_rxd1"),
106
+
PINCTRL_PIN(PIN_RGMII0_RXD2, "rgmii0_rxd2"),
107
+
PINCTRL_PIN(PIN_RGMII0_RXD3, "rgmii0_rxd3"),
108
+
PINCTRL_PIN(PIN_RGMII0_RXCTRL, "rgmii0_rxctrl"),
109
+
PINCTRL_PIN(PIN_RGMII0_TXC, "rgmii0_txc"),
110
+
PINCTRL_PIN(PIN_RGMII0_RXC, "rgmii0_rxc"),
111
+
PINCTRL_PIN(PIN_RGMII0_REFCLKO, "rgmii0_refclko"),
112
+
PINCTRL_PIN(PIN_RGMII0_IRQ, "rgmii0_irq"),
113
+
PINCTRL_PIN(PIN_RGMII0_MDC, "rgmii0_mdc"),
114
+
PINCTRL_PIN(PIN_RGMII0_MDIO, "rgmii0_mdio"),
115
+
PINCTRL_PIN(PIN_PWM0, "pwm0"),
116
+
PINCTRL_PIN(PIN_PWM1, "pwm1"),
117
+
PINCTRL_PIN(PIN_PWM2, "pwm2"),
118
+
PINCTRL_PIN(PIN_PWM3, "pwm3"),
119
+
PINCTRL_PIN(PIN_FAN0, "fan0"),
120
+
PINCTRL_PIN(PIN_FAN1, "fan1"),
121
+
PINCTRL_PIN(PIN_FAN2, "fan2"),
122
+
PINCTRL_PIN(PIN_FAN3, "fan3"),
123
+
PINCTRL_PIN(PIN_IIC0_SDA, "iic0_sda"),
124
+
PINCTRL_PIN(PIN_IIC0_SCL, "iic0_scl"),
125
+
PINCTRL_PIN(PIN_IIC1_SDA, "iic1_sda"),
126
+
PINCTRL_PIN(PIN_IIC1_SCL, "iic1_scl"),
127
+
PINCTRL_PIN(PIN_IIC2_SDA, "iic2_sda"),
128
+
PINCTRL_PIN(PIN_IIC2_SCL, "iic2_scl"),
129
+
PINCTRL_PIN(PIN_IIC3_SDA, "iic3_sda"),
130
+
PINCTRL_PIN(PIN_IIC3_SCL, "iic3_scl"),
131
+
PINCTRL_PIN(PIN_UART0_TX, "uart0_tx"),
132
+
PINCTRL_PIN(PIN_UART0_RX, "uart0_rx"),
133
+
PINCTRL_PIN(PIN_UART0_RTS, "uart0_rts"),
134
+
PINCTRL_PIN(PIN_UART0_CTS, "uart0_cts"),
135
+
PINCTRL_PIN(PIN_UART1_TX, "uart1_tx"),
136
+
PINCTRL_PIN(PIN_UART1_RX, "uart1_rx"),
137
+
PINCTRL_PIN(PIN_UART1_RTS, "uart1_rts"),
138
+
PINCTRL_PIN(PIN_UART1_CTS, "uart1_cts"),
139
+
PINCTRL_PIN(PIN_UART2_TX, "uart2_tx"),
140
+
PINCTRL_PIN(PIN_UART2_RX, "uart2_rx"),
141
+
PINCTRL_PIN(PIN_UART2_RTS, "uart2_rts"),
142
+
PINCTRL_PIN(PIN_UART2_CTS, "uart2_cts"),
143
+
PINCTRL_PIN(PIN_UART3_TX, "uart3_tx"),
144
+
PINCTRL_PIN(PIN_UART3_RX, "uart3_rx"),
145
+
PINCTRL_PIN(PIN_UART3_RTS, "uart3_rts"),
146
+
PINCTRL_PIN(PIN_UART3_CTS, "uart3_cts"),
147
+
PINCTRL_PIN(PIN_SPI0_CS0, "spi0_cs0"),
148
+
PINCTRL_PIN(PIN_SPI0_CS1, "spi0_cs1"),
149
+
PINCTRL_PIN(PIN_SPI0_SDI, "spi0_sdi"),
150
+
PINCTRL_PIN(PIN_SPI0_SDO, "spi0_sdo"),
151
+
PINCTRL_PIN(PIN_SPI0_SCK, "spi0_sck"),
152
+
PINCTRL_PIN(PIN_SPI1_CS0, "spi1_cs0"),
153
+
PINCTRL_PIN(PIN_SPI1_CS1, "spi1_cs1"),
154
+
PINCTRL_PIN(PIN_SPI1_SDI, "spi1_sdi"),
155
+
PINCTRL_PIN(PIN_SPI1_SDO, "spi1_sdo"),
156
+
PINCTRL_PIN(PIN_SPI1_SCK, "spi1_sck"),
157
+
PINCTRL_PIN(PIN_JTAG0_TDO, "jtag0_tdo"),
158
+
PINCTRL_PIN(PIN_JTAG0_TCK, "jtag0_tck"),
159
+
PINCTRL_PIN(PIN_JTAG0_TDI, "jtag0_tdi"),
160
+
PINCTRL_PIN(PIN_JTAG0_TMS, "jtag0_tms"),
161
+
PINCTRL_PIN(PIN_JTAG0_TRST, "jtag0_trst"),
162
+
PINCTRL_PIN(PIN_JTAG0_SRST, "jtag0_srst"),
163
+
PINCTRL_PIN(PIN_JTAG1_TDO, "jtag1_tdo"),
164
+
PINCTRL_PIN(PIN_JTAG1_TCK, "jtag1_tck"),
165
+
PINCTRL_PIN(PIN_JTAG1_TDI, "jtag1_tdi"),
166
+
PINCTRL_PIN(PIN_JTAG1_TMS, "jtag1_tms"),
167
+
PINCTRL_PIN(PIN_JTAG1_TRST, "jtag1_trst"),
168
+
PINCTRL_PIN(PIN_JTAG1_SRST, "jtag1_srst"),
169
+
PINCTRL_PIN(PIN_JTAG2_TDO, "jtag2_tdo"),
170
+
PINCTRL_PIN(PIN_JTAG2_TCK, "jtag2_tck"),
171
+
PINCTRL_PIN(PIN_JTAG2_TDI, "jtag2_tdi"),
172
+
PINCTRL_PIN(PIN_JTAG2_TMS, "jtag2_tms"),
173
+
PINCTRL_PIN(PIN_JTAG2_TRST, "jtag2_trst"),
174
+
PINCTRL_PIN(PIN_JTAG2_SRST, "jtag2_srst"),
175
+
PINCTRL_PIN(PIN_GPIO0, "gpio0"),
176
+
PINCTRL_PIN(PIN_GPIO1, "gpio1"),
177
+
PINCTRL_PIN(PIN_GPIO2, "gpio2"),
178
+
PINCTRL_PIN(PIN_GPIO3, "gpio3"),
179
+
PINCTRL_PIN(PIN_GPIO4, "gpio4"),
180
+
PINCTRL_PIN(PIN_GPIO5, "gpio5"),
181
+
PINCTRL_PIN(PIN_GPIO6, "gpio6"),
182
+
PINCTRL_PIN(PIN_GPIO7, "gpio7"),
183
+
PINCTRL_PIN(PIN_GPIO8, "gpio8"),
184
+
PINCTRL_PIN(PIN_GPIO9, "gpio9"),
185
+
PINCTRL_PIN(PIN_GPIO10, "gpio10"),
186
+
PINCTRL_PIN(PIN_GPIO11, "gpio11"),
187
+
PINCTRL_PIN(PIN_GPIO12, "gpio12"),
188
+
PINCTRL_PIN(PIN_GPIO13, "gpio13"),
189
+
PINCTRL_PIN(PIN_GPIO14, "gpio14"),
190
+
PINCTRL_PIN(PIN_GPIO15, "gpio15"),
191
+
PINCTRL_PIN(PIN_GPIO16, "gpio16"),
192
+
PINCTRL_PIN(PIN_GPIO17, "gpio17"),
193
+
PINCTRL_PIN(PIN_GPIO18, "gpio18"),
194
+
PINCTRL_PIN(PIN_GPIO19, "gpio19"),
195
+
PINCTRL_PIN(PIN_GPIO20, "gpio20"),
196
+
PINCTRL_PIN(PIN_GPIO21, "gpio21"),
197
+
PINCTRL_PIN(PIN_GPIO22, "gpio22"),
198
+
PINCTRL_PIN(PIN_GPIO23, "gpio23"),
199
+
PINCTRL_PIN(PIN_GPIO24, "gpio24"),
200
+
PINCTRL_PIN(PIN_GPIO25, "gpio25"),
201
+
PINCTRL_PIN(PIN_GPIO26, "gpio26"),
202
+
PINCTRL_PIN(PIN_GPIO27, "gpio27"),
203
+
PINCTRL_PIN(PIN_GPIO28, "gpio28"),
204
+
PINCTRL_PIN(PIN_GPIO29, "gpio29"),
205
+
PINCTRL_PIN(PIN_GPIO30, "gpio30"),
206
+
PINCTRL_PIN(PIN_GPIO31, "gpio31"),
207
+
PINCTRL_PIN(PIN_MODE_SEL0, "mode_sel0"),
208
+
PINCTRL_PIN(PIN_MODE_SEL1, "mode_sel1"),
209
+
PINCTRL_PIN(PIN_MODE_SEL2, "mode_sel2"),
210
+
PINCTRL_PIN(PIN_BOOT_SEL0, "boot_sel0"),
211
+
PINCTRL_PIN(PIN_BOOT_SEL1, "boot_sel1"),
212
+
PINCTRL_PIN(PIN_BOOT_SEL2, "boot_sel2"),
213
+
PINCTRL_PIN(PIN_BOOT_SEL3, "boot_sel3"),
214
+
PINCTRL_PIN(PIN_BOOT_SEL4, "boot_sel4"),
215
+
PINCTRL_PIN(PIN_BOOT_SEL5, "boot_sel5"),
216
+
PINCTRL_PIN(PIN_BOOT_SEL6, "boot_sel6"),
217
+
PINCTRL_PIN(PIN_BOOT_SEL7, "boot_sel7"),
218
+
PINCTRL_PIN(PIN_MULTI_SCKT, "multi_sckt"),
219
+
PINCTRL_PIN(PIN_SCKT_ID0, "sckt_id0"),
220
+
PINCTRL_PIN(PIN_SCKT_ID1, "sckt_id1"),
221
+
PINCTRL_PIN(PIN_PLL_CLK_IN_MAIN, "pll_clk_in_main"),
222
+
PINCTRL_PIN(PIN_PLL_CLK_IN_DDR_L, "pll_clk_in_ddr_l"),
223
+
PINCTRL_PIN(PIN_PLL_CLK_IN_DDR_R, "pll_clk_in_ddr_r"),
224
+
PINCTRL_PIN(PIN_XTAL_32K, "xtal_32k"),
225
+
PINCTRL_PIN(PIN_SYS_RST, "sys_rst"),
226
+
PINCTRL_PIN(PIN_PWR_BUTTON, "pwr_button"),
227
+
PINCTRL_PIN(PIN_TEST_EN, "test_en"),
228
+
PINCTRL_PIN(PIN_TEST_MODE_MBIST, "test_mode_mbist"),
229
+
PINCTRL_PIN(PIN_TEST_MODE_SCAN, "test_mode_scan"),
230
+
PINCTRL_PIN(PIN_TEST_MODE_BSD, "test_mode_bsd"),
231
+
PINCTRL_PIN(PIN_BISR_BYP, "bisr_byp"),
232
+
};
233
+
234
+
static const struct sg2042_pin sg2042_pin_data[ARRAY_SIZE(sg2042_pins)] = {
235
+
SG2042_GENERAL_PIN(PIN_LPC_LCLK, 0x000,
236
+
PIN_FLAG_ONLY_ONE_PULL),
237
+
SG2042_GENERAL_PIN(PIN_LPC_LFRAME, 0x000,
238
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
239
+
SG2042_GENERAL_PIN(PIN_LPC_LAD0, 0x004,
240
+
PIN_FLAG_ONLY_ONE_PULL),
241
+
SG2042_GENERAL_PIN(PIN_LPC_LAD1, 0x004,
242
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
243
+
SG2042_GENERAL_PIN(PIN_LPC_LAD2, 0x008,
244
+
PIN_FLAG_ONLY_ONE_PULL),
245
+
SG2042_GENERAL_PIN(PIN_LPC_LAD3, 0x008,
246
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
247
+
SG2042_GENERAL_PIN(PIN_LPC_LDRQ0, 0x00c,
248
+
PIN_FLAG_ONLY_ONE_PULL),
249
+
SG2042_GENERAL_PIN(PIN_LPC_LDRQ1, 0x00c,
250
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
251
+
SG2042_GENERAL_PIN(PIN_LPC_SERIRQ, 0x010,
252
+
PIN_FLAG_ONLY_ONE_PULL),
253
+
SG2042_GENERAL_PIN(PIN_LPC_CLKRUN, 0x010,
254
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
255
+
SG2042_GENERAL_PIN(PIN_LPC_LPME, 0x014,
256
+
PIN_FLAG_ONLY_ONE_PULL),
257
+
SG2042_GENERAL_PIN(PIN_LPC_LPCPD, 0x014,
258
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
259
+
SG2042_GENERAL_PIN(PIN_LPC_LSMI, 0x018,
260
+
PIN_FLAG_ONLY_ONE_PULL),
261
+
SG2042_GENERAL_PIN(PIN_PCIE0_L0_RESET, 0x018,
262
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
263
+
SG2042_GENERAL_PIN(PIN_PCIE0_L1_RESET, 0x01c,
264
+
PIN_FLAG_ONLY_ONE_PULL),
265
+
SG2042_GENERAL_PIN(PIN_PCIE0_L0_WAKEUP, 0x01c,
266
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
267
+
SG2042_GENERAL_PIN(PIN_PCIE0_L1_WAKEUP, 0x020,
268
+
PIN_FLAG_ONLY_ONE_PULL),
269
+
SG2042_GENERAL_PIN(PIN_PCIE0_L0_CLKREQ_IN, 0x020,
270
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
271
+
SG2042_GENERAL_PIN(PIN_PCIE0_L1_CLKREQ_IN, 0x024,
272
+
PIN_FLAG_ONLY_ONE_PULL),
273
+
SG2042_GENERAL_PIN(PIN_PCIE1_L0_RESET, 0x024,
274
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
275
+
SG2042_GENERAL_PIN(PIN_PCIE1_L1_RESET, 0x028,
276
+
PIN_FLAG_ONLY_ONE_PULL),
277
+
SG2042_GENERAL_PIN(PIN_PCIE1_L0_WAKEUP, 0x028,
278
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
279
+
SG2042_GENERAL_PIN(PIN_PCIE1_L1_WAKEUP, 0x02c,
280
+
PIN_FLAG_ONLY_ONE_PULL),
281
+
SG2042_GENERAL_PIN(PIN_PCIE1_L0_CLKREQ_IN, 0x02c,
282
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
283
+
SG2042_GENERAL_PIN(PIN_PCIE1_L1_CLKREQ_IN, 0x030,
284
+
PIN_FLAG_ONLY_ONE_PULL),
285
+
SG2042_GENERAL_PIN(PIN_SPIF0_CLK_SEL1, 0x030,
286
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
287
+
SG2042_GENERAL_PIN(PIN_SPIF0_CLK_SEL0, 0x034,
288
+
PIN_FLAG_ONLY_ONE_PULL),
289
+
SG2042_GENERAL_PIN(PIN_SPIF0_WP, 0x034,
290
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
291
+
SG2042_GENERAL_PIN(PIN_SPIF0_HOLD, 0x038,
292
+
PIN_FLAG_ONLY_ONE_PULL),
293
+
SG2042_GENERAL_PIN(PIN_SPIF0_SDI, 0x038,
294
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
295
+
SG2042_GENERAL_PIN(PIN_SPIF0_CS, 0x03c,
296
+
PIN_FLAG_ONLY_ONE_PULL),
297
+
SG2042_GENERAL_PIN(PIN_SPIF0_SCK, 0x03c,
298
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
299
+
SG2042_GENERAL_PIN(PIN_SPIF0_SDO, 0x040,
300
+
PIN_FLAG_ONLY_ONE_PULL),
301
+
SG2042_GENERAL_PIN(PIN_SPIF1_CLK_SEL1, 0x040,
302
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
303
+
SG2042_GENERAL_PIN(PIN_SPIF1_CLK_SEL0, 0x044,
304
+
PIN_FLAG_ONLY_ONE_PULL),
305
+
SG2042_GENERAL_PIN(PIN_SPIF1_WP, 0x044,
306
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
307
+
SG2042_GENERAL_PIN(PIN_SPIF1_HOLD, 0x048,
308
+
PIN_FLAG_ONLY_ONE_PULL),
309
+
SG2042_GENERAL_PIN(PIN_SPIF1_SDI, 0x048,
310
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
311
+
SG2042_GENERAL_PIN(PIN_SPIF1_CS, 0x04c,
312
+
PIN_FLAG_ONLY_ONE_PULL),
313
+
SG2042_GENERAL_PIN(PIN_SPIF1_SCK, 0x04c,
314
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
315
+
SG2042_GENERAL_PIN(PIN_SPIF1_SDO, 0x050,
316
+
PIN_FLAG_ONLY_ONE_PULL),
317
+
SG2042_GENERAL_PIN(PIN_EMMC_WP, 0x050,
318
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
319
+
SG2042_GENERAL_PIN(PIN_EMMC_CD, 0x054,
320
+
PIN_FLAG_ONLY_ONE_PULL),
321
+
SG2042_GENERAL_PIN(PIN_EMMC_RST, 0x054,
322
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
323
+
SG2042_GENERAL_PIN(PIN_EMMC_PWR_EN, 0x058,
324
+
PIN_FLAG_ONLY_ONE_PULL),
325
+
SG2042_GENERAL_PIN(PIN_SDIO_CD, 0x058,
326
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
327
+
SG2042_GENERAL_PIN(PIN_SDIO_WP, 0x05c,
328
+
PIN_FLAG_ONLY_ONE_PULL),
329
+
SG2042_GENERAL_PIN(PIN_SDIO_RST, 0x05c,
330
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
331
+
SG2042_GENERAL_PIN(PIN_SDIO_PWR_EN, 0x060,
332
+
PIN_FLAG_ONLY_ONE_PULL),
333
+
SG2042_GENERAL_PIN(PIN_RGMII0_TXD0, 0x060,
334
+
PIN_FLAG_WRITE_HIGH),
335
+
SG2042_GENERAL_PIN(PIN_RGMII0_TXD1, 0x064,
336
+
PIN_FLAG_DEFAULT),
337
+
SG2042_GENERAL_PIN(PIN_RGMII0_TXD2, 0x064,
338
+
PIN_FLAG_WRITE_HIGH),
339
+
SG2042_GENERAL_PIN(PIN_RGMII0_TXD3, 0x068,
340
+
PIN_FLAG_DEFAULT),
341
+
SG2042_GENERAL_PIN(PIN_RGMII0_TXCTRL, 0x068,
342
+
PIN_FLAG_WRITE_HIGH),
343
+
SG2042_GENERAL_PIN(PIN_RGMII0_RXD0, 0x06c,
344
+
PIN_FLAG_DEFAULT),
345
+
SG2042_GENERAL_PIN(PIN_RGMII0_RXD1, 0x06c,
346
+
PIN_FLAG_WRITE_HIGH),
347
+
SG2042_GENERAL_PIN(PIN_RGMII0_RXD2, 0x070,
348
+
PIN_FLAG_DEFAULT),
349
+
SG2042_GENERAL_PIN(PIN_RGMII0_RXD3, 0x070,
350
+
PIN_FLAG_WRITE_HIGH),
351
+
SG2042_GENERAL_PIN(PIN_RGMII0_RXCTRL, 0x074,
352
+
PIN_FLAG_DEFAULT),
353
+
SG2042_GENERAL_PIN(PIN_RGMII0_TXC, 0x074,
354
+
PIN_FLAG_WRITE_HIGH),
355
+
SG2042_GENERAL_PIN(PIN_RGMII0_RXC, 0x078,
356
+
PIN_FLAG_DEFAULT),
357
+
SG2042_GENERAL_PIN(PIN_RGMII0_REFCLKO, 0x078,
358
+
PIN_FLAG_WRITE_HIGH),
359
+
SG2042_GENERAL_PIN(PIN_RGMII0_IRQ, 0x07c,
360
+
PIN_FLAG_DEFAULT),
361
+
SG2042_GENERAL_PIN(PIN_RGMII0_MDC, 0x07c,
362
+
PIN_FLAG_WRITE_HIGH),
363
+
SG2042_GENERAL_PIN(PIN_RGMII0_MDIO, 0x080,
364
+
PIN_FLAG_DEFAULT),
365
+
SG2042_GENERAL_PIN(PIN_PWM0, 0x080,
366
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
367
+
SG2042_GENERAL_PIN(PIN_PWM1, 0x084,
368
+
PIN_FLAG_ONLY_ONE_PULL),
369
+
SG2042_GENERAL_PIN(PIN_PWM2, 0x084,
370
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
371
+
SG2042_GENERAL_PIN(PIN_PWM3, 0x088,
372
+
PIN_FLAG_ONLY_ONE_PULL),
373
+
SG2042_GENERAL_PIN(PIN_FAN0, 0x088,
374
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
375
+
SG2042_GENERAL_PIN(PIN_FAN1, 0x08c,
376
+
PIN_FLAG_ONLY_ONE_PULL),
377
+
SG2042_GENERAL_PIN(PIN_FAN2, 0x08c,
378
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
379
+
SG2042_GENERAL_PIN(PIN_FAN3, 0x090,
380
+
PIN_FLAG_ONLY_ONE_PULL),
381
+
SG2042_GENERAL_PIN(PIN_IIC0_SDA, 0x090,
382
+
PIN_FLAG_WRITE_HIGH),
383
+
SG2042_GENERAL_PIN(PIN_IIC0_SCL, 0x094,
384
+
PIN_FLAG_DEFAULT),
385
+
SG2042_GENERAL_PIN(PIN_IIC1_SDA, 0x094,
386
+
PIN_FLAG_WRITE_HIGH),
387
+
SG2042_GENERAL_PIN(PIN_IIC1_SCL, 0x098,
388
+
PIN_FLAG_DEFAULT),
389
+
SG2042_GENERAL_PIN(PIN_IIC2_SDA, 0x098,
390
+
PIN_FLAG_WRITE_HIGH),
391
+
SG2042_GENERAL_PIN(PIN_IIC2_SCL, 0x09c,
392
+
PIN_FLAG_DEFAULT),
393
+
SG2042_GENERAL_PIN(PIN_IIC3_SDA, 0x09c,
394
+
PIN_FLAG_WRITE_HIGH),
395
+
SG2042_GENERAL_PIN(PIN_IIC3_SCL, 0x0a0,
396
+
PIN_FLAG_DEFAULT),
397
+
SG2042_GENERAL_PIN(PIN_UART0_TX, 0x0a0,
398
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
399
+
SG2042_GENERAL_PIN(PIN_UART0_RX, 0x0a4,
400
+
PIN_FLAG_ONLY_ONE_PULL),
401
+
SG2042_GENERAL_PIN(PIN_UART0_RTS, 0x0a4,
402
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
403
+
SG2042_GENERAL_PIN(PIN_UART0_CTS, 0x0a8,
404
+
PIN_FLAG_ONLY_ONE_PULL),
405
+
SG2042_GENERAL_PIN(PIN_UART1_TX, 0x0a8,
406
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
407
+
SG2042_GENERAL_PIN(PIN_UART1_RX, 0x0ac,
408
+
PIN_FLAG_ONLY_ONE_PULL),
409
+
SG2042_GENERAL_PIN(PIN_UART1_RTS, 0x0ac,
410
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
411
+
SG2042_GENERAL_PIN(PIN_UART1_CTS, 0x0b0,
412
+
PIN_FLAG_ONLY_ONE_PULL),
413
+
SG2042_GENERAL_PIN(PIN_UART2_TX, 0x0b0,
414
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
415
+
SG2042_GENERAL_PIN(PIN_UART2_RX, 0x0b4,
416
+
PIN_FLAG_ONLY_ONE_PULL),
417
+
SG2042_GENERAL_PIN(PIN_UART2_RTS, 0x0b4,
418
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
419
+
SG2042_GENERAL_PIN(PIN_UART2_CTS, 0x0b8,
420
+
PIN_FLAG_ONLY_ONE_PULL),
421
+
SG2042_GENERAL_PIN(PIN_UART3_TX, 0x0b8,
422
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
423
+
SG2042_GENERAL_PIN(PIN_UART3_RX, 0x0bc,
424
+
PIN_FLAG_ONLY_ONE_PULL),
425
+
SG2042_GENERAL_PIN(PIN_UART3_RTS, 0x0bc,
426
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
427
+
SG2042_GENERAL_PIN(PIN_UART3_CTS, 0x0c0,
428
+
PIN_FLAG_ONLY_ONE_PULL),
429
+
SG2042_GENERAL_PIN(PIN_SPI0_CS0, 0x0c0,
430
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
431
+
SG2042_GENERAL_PIN(PIN_SPI0_CS1, 0x0c4,
432
+
PIN_FLAG_ONLY_ONE_PULL),
433
+
SG2042_GENERAL_PIN(PIN_SPI0_SDI, 0x0c4,
434
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
435
+
SG2042_GENERAL_PIN(PIN_SPI0_SDO, 0x0c8,
436
+
PIN_FLAG_ONLY_ONE_PULL),
437
+
SG2042_GENERAL_PIN(PIN_SPI0_SCK, 0x0c8,
438
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
439
+
SG2042_GENERAL_PIN(PIN_SPI1_CS0, 0x0cc,
440
+
PIN_FLAG_ONLY_ONE_PULL),
441
+
SG2042_GENERAL_PIN(PIN_SPI1_CS1, 0x0cc,
442
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
443
+
SG2042_GENERAL_PIN(PIN_SPI1_SDI, 0x0d0,
444
+
PIN_FLAG_ONLY_ONE_PULL),
445
+
SG2042_GENERAL_PIN(PIN_SPI1_SDO, 0x0d0,
446
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
447
+
SG2042_GENERAL_PIN(PIN_SPI1_SCK, 0x0d4,
448
+
PIN_FLAG_ONLY_ONE_PULL),
449
+
SG2042_GENERAL_PIN(PIN_JTAG0_TDO, 0x0d4,
450
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
451
+
SG2042_GENERAL_PIN(PIN_JTAG0_TCK, 0x0d8,
452
+
PIN_FLAG_ONLY_ONE_PULL),
453
+
SG2042_GENERAL_PIN(PIN_JTAG0_TDI, 0x0d8,
454
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
455
+
SG2042_GENERAL_PIN(PIN_JTAG0_TMS, 0x0dc,
456
+
PIN_FLAG_ONLY_ONE_PULL),
457
+
SG2042_GENERAL_PIN(PIN_JTAG0_TRST, 0x0dc,
458
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
459
+
SG2042_GENERAL_PIN(PIN_JTAG0_SRST, 0x0e0,
460
+
PIN_FLAG_ONLY_ONE_PULL),
461
+
SG2042_GENERAL_PIN(PIN_JTAG1_TDO, 0x0e0,
462
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
463
+
SG2042_GENERAL_PIN(PIN_JTAG1_TCK, 0x0e4,
464
+
PIN_FLAG_ONLY_ONE_PULL),
465
+
SG2042_GENERAL_PIN(PIN_JTAG1_TDI, 0x0e4,
466
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
467
+
SG2042_GENERAL_PIN(PIN_JTAG1_TMS, 0x0e8,
468
+
PIN_FLAG_ONLY_ONE_PULL),
469
+
SG2042_GENERAL_PIN(PIN_JTAG1_TRST, 0x0e8,
470
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
471
+
SG2042_GENERAL_PIN(PIN_JTAG1_SRST, 0x0ec,
472
+
PIN_FLAG_ONLY_ONE_PULL),
473
+
SG2042_GENERAL_PIN(PIN_JTAG2_TDO, 0x0ec,
474
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
475
+
SG2042_GENERAL_PIN(PIN_JTAG2_TCK, 0x0f0,
476
+
PIN_FLAG_ONLY_ONE_PULL),
477
+
SG2042_GENERAL_PIN(PIN_JTAG2_TDI, 0x0f0,
478
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
479
+
SG2042_GENERAL_PIN(PIN_JTAG2_TMS, 0x0f4,
480
+
PIN_FLAG_ONLY_ONE_PULL),
481
+
SG2042_GENERAL_PIN(PIN_JTAG2_TRST, 0x0f4,
482
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
483
+
SG2042_GENERAL_PIN(PIN_JTAG2_SRST, 0x0f8,
484
+
PIN_FLAG_ONLY_ONE_PULL),
485
+
SG2042_GENERAL_PIN(PIN_GPIO0, 0x0f8,
486
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
487
+
SG2042_GENERAL_PIN(PIN_GPIO1, 0x0fc,
488
+
PIN_FLAG_ONLY_ONE_PULL),
489
+
SG2042_GENERAL_PIN(PIN_GPIO2, 0x0fc,
490
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
491
+
SG2042_GENERAL_PIN(PIN_GPIO3, 0x100,
492
+
PIN_FLAG_ONLY_ONE_PULL),
493
+
SG2042_GENERAL_PIN(PIN_GPIO4, 0x100,
494
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
495
+
SG2042_GENERAL_PIN(PIN_GPIO5, 0x104,
496
+
PIN_FLAG_ONLY_ONE_PULL),
497
+
SG2042_GENERAL_PIN(PIN_GPIO6, 0x104,
498
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
499
+
SG2042_GENERAL_PIN(PIN_GPIO7, 0x108,
500
+
PIN_FLAG_ONLY_ONE_PULL),
501
+
SG2042_GENERAL_PIN(PIN_GPIO8, 0x108,
502
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
503
+
SG2042_GENERAL_PIN(PIN_GPIO9, 0x10c,
504
+
PIN_FLAG_ONLY_ONE_PULL),
505
+
SG2042_GENERAL_PIN(PIN_GPIO10, 0x10c,
506
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
507
+
SG2042_GENERAL_PIN(PIN_GPIO11, 0x110,
508
+
PIN_FLAG_ONLY_ONE_PULL),
509
+
SG2042_GENERAL_PIN(PIN_GPIO12, 0x110,
510
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
511
+
SG2042_GENERAL_PIN(PIN_GPIO13, 0x114,
512
+
PIN_FLAG_ONLY_ONE_PULL),
513
+
SG2042_GENERAL_PIN(PIN_GPIO14, 0x114,
514
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
515
+
SG2042_GENERAL_PIN(PIN_GPIO15, 0x118,
516
+
PIN_FLAG_ONLY_ONE_PULL),
517
+
SG2042_GENERAL_PIN(PIN_GPIO16, 0x118,
518
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
519
+
SG2042_GENERAL_PIN(PIN_GPIO17, 0x11c,
520
+
PIN_FLAG_ONLY_ONE_PULL),
521
+
SG2042_GENERAL_PIN(PIN_GPIO18, 0x11c,
522
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
523
+
SG2042_GENERAL_PIN(PIN_GPIO19, 0x120,
524
+
PIN_FLAG_ONLY_ONE_PULL),
525
+
SG2042_GENERAL_PIN(PIN_GPIO20, 0x120,
526
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
527
+
SG2042_GENERAL_PIN(PIN_GPIO21, 0x124,
528
+
PIN_FLAG_ONLY_ONE_PULL),
529
+
SG2042_GENERAL_PIN(PIN_GPIO22, 0x124,
530
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
531
+
SG2042_GENERAL_PIN(PIN_GPIO23, 0x128,
532
+
PIN_FLAG_ONLY_ONE_PULL),
533
+
SG2042_GENERAL_PIN(PIN_GPIO24, 0x128,
534
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
535
+
SG2042_GENERAL_PIN(PIN_GPIO25, 0x12c,
536
+
PIN_FLAG_ONLY_ONE_PULL),
537
+
SG2042_GENERAL_PIN(PIN_GPIO26, 0x12c,
538
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
539
+
SG2042_GENERAL_PIN(PIN_GPIO27, 0x130,
540
+
PIN_FLAG_ONLY_ONE_PULL),
541
+
SG2042_GENERAL_PIN(PIN_GPIO28, 0x130,
542
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
543
+
SG2042_GENERAL_PIN(PIN_GPIO29, 0x134,
544
+
PIN_FLAG_ONLY_ONE_PULL),
545
+
SG2042_GENERAL_PIN(PIN_GPIO30, 0x134,
546
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL),
547
+
SG2042_GENERAL_PIN(PIN_GPIO31, 0x138,
548
+
PIN_FLAG_ONLY_ONE_PULL),
549
+
SG2042_GENERAL_PIN(PIN_MODE_SEL0, 0x138,
550
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL |
551
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
552
+
SG2042_GENERAL_PIN(PIN_MODE_SEL1, 0x13c,
553
+
PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX |
554
+
PIN_FLAG_NO_OEX_EN),
555
+
SG2042_GENERAL_PIN(PIN_MODE_SEL2, 0x13c,
556
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL |
557
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
558
+
SG2042_GENERAL_PIN(PIN_BOOT_SEL0, 0x140,
559
+
PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX |
560
+
PIN_FLAG_NO_OEX_EN),
561
+
SG2042_GENERAL_PIN(PIN_BOOT_SEL1, 0x140,
562
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL |
563
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
564
+
SG2042_GENERAL_PIN(PIN_BOOT_SEL2, 0x144,
565
+
PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX |
566
+
PIN_FLAG_NO_OEX_EN),
567
+
SG2042_GENERAL_PIN(PIN_BOOT_SEL3, 0x144,
568
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL |
569
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
570
+
SG2042_GENERAL_PIN(PIN_BOOT_SEL4, 0x148,
571
+
PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX |
572
+
PIN_FLAG_NO_OEX_EN),
573
+
SG2042_GENERAL_PIN(PIN_BOOT_SEL5, 0x148,
574
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL |
575
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
576
+
SG2042_GENERAL_PIN(PIN_BOOT_SEL6, 0x14c,
577
+
PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX |
578
+
PIN_FLAG_NO_OEX_EN),
579
+
SG2042_GENERAL_PIN(PIN_BOOT_SEL7, 0x14c,
580
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL |
581
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
582
+
SG2042_GENERAL_PIN(PIN_MULTI_SCKT, 0x150,
583
+
PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX |
584
+
PIN_FLAG_NO_OEX_EN),
585
+
SG2042_GENERAL_PIN(PIN_SCKT_ID0, 0x150,
586
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL |
587
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
588
+
SG2042_GENERAL_PIN(PIN_SCKT_ID1, 0x154,
589
+
PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX |
590
+
PIN_FLAG_NO_OEX_EN),
591
+
SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_MAIN, 0x154,
592
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL |
593
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
594
+
SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_DDR_L, 0x158,
595
+
PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX |
596
+
PIN_FLAG_NO_OEX_EN),
597
+
SG2042_GENERAL_PIN(PIN_PLL_CLK_IN_DDR_R, 0x158,
598
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL |
599
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
600
+
SG2042_GENERAL_PIN(PIN_XTAL_32K, 0x15c,
601
+
PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX |
602
+
PIN_FLAG_NO_OEX_EN),
603
+
SG2042_GENERAL_PIN(PIN_SYS_RST, 0x15c,
604
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL |
605
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
606
+
SG2042_GENERAL_PIN(PIN_PWR_BUTTON, 0x160,
607
+
PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX |
608
+
PIN_FLAG_NO_OEX_EN),
609
+
SG2042_GENERAL_PIN(PIN_TEST_EN, 0x160,
610
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL |
611
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
612
+
SG2042_GENERAL_PIN(PIN_TEST_MODE_MBIST, 0x164,
613
+
PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX |
614
+
PIN_FLAG_NO_OEX_EN),
615
+
SG2042_GENERAL_PIN(PIN_TEST_MODE_SCAN, 0x164,
616
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL |
617
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
618
+
SG2042_GENERAL_PIN(PIN_TEST_MODE_BSD, 0x168,
619
+
PIN_FLAG_ONLY_ONE_PULL | PIN_FLAG_NO_PINMUX |
620
+
PIN_FLAG_NO_OEX_EN),
621
+
SG2042_GENERAL_PIN(PIN_BISR_BYP, 0x168,
622
+
PIN_FLAG_WRITE_HIGH | PIN_FLAG_ONLY_ONE_PULL |
623
+
PIN_FLAG_NO_PINMUX | PIN_FLAG_NO_OEX_EN),
624
+
};
625
+
626
+
static const struct sophgo_pinctrl_data sg2042_pindata = {
627
+
.pins = sg2042_pins,
628
+
.pindata = sg2042_pin_data,
629
+
.vddio_ops = &sg2042_vddio_cfg_ops,
630
+
.cfg_ops = &sg2042_cfg_ops,
631
+
.pctl_ops = &sg2042_pctrl_ops,
632
+
.pmx_ops = &sg2042_pmx_ops,
633
+
.pconf_ops = &sg2042_pconf_ops,
634
+
.npins = ARRAY_SIZE(sg2042_pins),
635
+
.pinsize = sizeof(struct sg2042_pin),
636
+
};
637
+
638
+
static const struct of_device_id sg2042_pinctrl_ids[] = {
639
+
{ .compatible = "sophgo,sg2042-pinctrl", .data = &sg2042_pindata },
640
+
{ }
641
+
};
642
+
MODULE_DEVICE_TABLE(of, sg2042_pinctrl_ids);
643
+
644
+
static struct platform_driver sg2042_pinctrl_driver = {
645
+
.probe = sophgo_pinctrl_probe,
646
+
.driver = {
647
+
.name = "sg2042-pinctrl",
648
+
.suppress_bind_attrs = true,
649
+
.of_match_table = sg2042_pinctrl_ids,
650
+
},
651
+
};
652
+
module_platform_driver(sg2042_pinctrl_driver);
653
+
654
+
MODULE_DESCRIPTION("Pinctrl driver for the SG2002 series SoC");
655
+
MODULE_LICENSE("GPL");
+49
drivers/pinctrl/sophgo/pinctrl-sg2042.h
+49
drivers/pinctrl/sophgo/pinctrl-sg2042.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
4
+
*/
5
+
6
+
#ifndef _PINCTRL_SOPHGO_SG2042_H
7
+
#define _PINCTRL_SOPHGO_SG2042_H
8
+
9
+
#include <linux/bits.h>
10
+
#include <linux/bitfield.h>
11
+
#include <linux/device.h>
12
+
#include <linux/mutex.h>
13
+
#include <linux/spinlock.h>
14
+
#include <linux/platform_device.h>
15
+
#include <linux/pinctrl/pinctrl.h>
16
+
#include <linux/pinctrl/pinconf.h>
17
+
18
+
#include "pinctrl-sophgo.h"
19
+
20
+
#define PIN_FLAG_DEFAULT 0
21
+
#define PIN_FLAG_WRITE_HIGH BIT(0)
22
+
#define PIN_FLAG_ONLY_ONE_PULL BIT(1)
23
+
#define PIN_FLAG_NO_PINMUX BIT(2)
24
+
#define PIN_FLAG_NO_OEX_EN BIT(3)
25
+
#define PIN_FLAG_IS_ETH BIT(4)
26
+
27
+
struct sg2042_pin {
28
+
struct sophgo_pin pin;
29
+
u16 offset;
30
+
};
31
+
32
+
#define sophgo_to_sg2042_pin(_pin) \
33
+
container_of((_pin), struct sg2042_pin, pin)
34
+
35
+
extern const struct pinctrl_ops sg2042_pctrl_ops;
36
+
extern const struct pinmux_ops sg2042_pmx_ops;
37
+
extern const struct pinconf_ops sg2042_pconf_ops;
38
+
extern const struct sophgo_cfg_ops sg2042_cfg_ops;
39
+
40
+
#define SG2042_GENERAL_PIN(_id, _offset, _flag) \
41
+
{ \
42
+
.pin = { \
43
+
.id = (_id), \
44
+
.flags = (_flag), \
45
+
}, \
46
+
.offset = (_offset), \
47
+
}
48
+
49
+
#endif