tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

clk: qcom: gcc-sm8150: use ARRAY_SIZE instead of specifying num_parents

Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-32-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

Dmitry Baryshkov and committed by
Stephen Boyd 60ca4670 b6cf77a7

+48 -48
+48 -48
drivers/clk/qcom/gcc-sm8150.c
··· 241 241 .clkr.hw.init = &(struct clk_init_data){ 242 242 .name = "gcc_cpuss_ahb_clk_src", 243 243 .parent_data = gcc_parents_0, 244 - .num_parents = 4, 244 + .num_parents = ARRAY_SIZE(gcc_parents_0), 245 245 .flags = CLK_SET_RATE_PARENT, 246 246 .ops = &clk_rcg2_ops, 247 247 }, ··· 264 264 .clkr.hw.init = &(struct clk_init_data){ 265 265 .name = "gcc_emac_ptp_clk_src", 266 266 .parent_data = gcc_parents_5, 267 - .num_parents = 5, 267 + .num_parents = ARRAY_SIZE(gcc_parents_5), 268 268 .flags = CLK_SET_RATE_PARENT, 269 269 .ops = &clk_rcg2_ops, 270 270 }, ··· 290 290 .clkr.hw.init = &(struct clk_init_data){ 291 291 .name = "gcc_emac_rgmii_clk_src", 292 292 .parent_data = gcc_parents_5, 293 - .num_parents = 5, 293 + .num_parents = ARRAY_SIZE(gcc_parents_5), 294 294 .flags = CLK_SET_RATE_PARENT, 295 295 .ops = &clk_rcg2_ops, 296 296 }, ··· 314 314 .clkr.hw.init = &(struct clk_init_data){ 315 315 .name = "gcc_gp1_clk_src", 316 316 .parent_data = gcc_parents_1, 317 - .num_parents = 5, 317 + .num_parents = ARRAY_SIZE(gcc_parents_1), 318 318 .flags = CLK_SET_RATE_PARENT, 319 319 .ops = &clk_rcg2_ops, 320 320 }, ··· 329 329 .clkr.hw.init = &(struct clk_init_data){ 330 330 .name = "gcc_gp2_clk_src", 331 331 .parent_data = gcc_parents_1, 332 - .num_parents = 5, 332 + .num_parents = ARRAY_SIZE(gcc_parents_1), 333 333 .flags = CLK_SET_RATE_PARENT, 334 334 .ops = &clk_rcg2_ops, 335 335 }, ··· 344 344 .clkr.hw.init = &(struct clk_init_data){ 345 345 .name = "gcc_gp3_clk_src", 346 346 .parent_data = gcc_parents_1, 347 - .num_parents = 5, 347 + .num_parents = ARRAY_SIZE(gcc_parents_1), 348 348 .flags = CLK_SET_RATE_PARENT, 349 349 .ops = &clk_rcg2_ops, 350 350 }, ··· 365 365 .clkr.hw.init = &(struct clk_init_data){ 366 366 .name = "gcc_pcie_0_aux_clk_src", 367 367 .parent_data = gcc_parents_2, 368 - .num_parents = 3, 368 + .num_parents = ARRAY_SIZE(gcc_parents_2), 369 369 .flags = CLK_SET_RATE_PARENT, 370 370 .ops = &clk_rcg2_ops, 371 371 }, ··· 380 380 .clkr.hw.init = &(struct clk_init_data){ 381 381 .name = "gcc_pcie_1_aux_clk_src", 382 382 .parent_data = gcc_parents_2, 383 - .num_parents = 3, 383 + .num_parents = ARRAY_SIZE(gcc_parents_2), 384 384 .flags = CLK_SET_RATE_PARENT, 385 385 .ops = &clk_rcg2_ops, 386 386 }, ··· 401 401 .clkr.hw.init = &(struct clk_init_data){ 402 402 .name = "gcc_pcie_phy_refgen_clk_src", 403 403 .parent_data = gcc_parents_0, 404 - .num_parents = 4, 404 + .num_parents = ARRAY_SIZE(gcc_parents_0), 405 405 .flags = CLK_SET_RATE_PARENT, 406 406 .ops = &clk_rcg2_ops, 407 407 }, ··· 423 423 .clkr.hw.init = &(struct clk_init_data){ 424 424 .name = "gcc_pdm2_clk_src", 425 425 .parent_data = gcc_parents_0, 426 - .num_parents = 4, 426 + .num_parents = ARRAY_SIZE(gcc_parents_0), 427 427 .flags = CLK_SET_RATE_PARENT, 428 428 .ops = &clk_rcg2_ops, 429 429 }, ··· 446 446 .clkr.hw.init = &(struct clk_init_data){ 447 447 .name = "gcc_qspi_core_clk_src", 448 448 .parent_data = gcc_parents_0, 449 - .num_parents = 4, 449 + .num_parents = ARRAY_SIZE(gcc_parents_0), 450 450 .flags = CLK_SET_RATE_PARENT, 451 451 .ops = &clk_rcg2_ops, 452 452 }, ··· 480 480 .clkr.hw.init = &(struct clk_init_data){ 481 481 .name = "gcc_qupv3_wrap0_s0_clk_src", 482 482 .parent_data = gcc_parents_0, 483 - .num_parents = 4, 483 + .num_parents = ARRAY_SIZE(gcc_parents_0), 484 484 .flags = CLK_SET_RATE_PARENT, 485 485 .ops = &clk_rcg2_ops, 486 486 }, ··· 495 495 .clkr.hw.init = &(struct clk_init_data){ 496 496 .name = "gcc_qupv3_wrap0_s1_clk_src", 497 497 .parent_data = gcc_parents_0, 498 - .num_parents = 4, 498 + .num_parents = ARRAY_SIZE(gcc_parents_0), 499 499 .flags = CLK_SET_RATE_PARENT, 500 500 .ops = &clk_rcg2_ops, 501 501 }, ··· 510 510 .clkr.hw.init = &(struct clk_init_data){ 511 511 .name = "gcc_qupv3_wrap0_s2_clk_src", 512 512 .parent_data = gcc_parents_0, 513 - .num_parents = 4, 513 + .num_parents = ARRAY_SIZE(gcc_parents_0), 514 514 .flags = CLK_SET_RATE_PARENT, 515 515 .ops = &clk_rcg2_ops, 516 516 }, ··· 525 525 .clkr.hw.init = &(struct clk_init_data){ 526 526 .name = "gcc_qupv3_wrap0_s3_clk_src", 527 527 .parent_data = gcc_parents_0, 528 - .num_parents = 4, 528 + .num_parents = ARRAY_SIZE(gcc_parents_0), 529 529 .flags = CLK_SET_RATE_PARENT, 530 530 .ops = &clk_rcg2_ops, 531 531 }, ··· 540 540 .clkr.hw.init = &(struct clk_init_data){ 541 541 .name = "gcc_qupv3_wrap0_s4_clk_src", 542 542 .parent_data = gcc_parents_0, 543 - .num_parents = 4, 543 + .num_parents = ARRAY_SIZE(gcc_parents_0), 544 544 .flags = CLK_SET_RATE_PARENT, 545 545 .ops = &clk_rcg2_ops, 546 546 }, ··· 555 555 .clkr.hw.init = &(struct clk_init_data){ 556 556 .name = "gcc_qupv3_wrap0_s5_clk_src", 557 557 .parent_data = gcc_parents_0, 558 - .num_parents = 4, 558 + .num_parents = ARRAY_SIZE(gcc_parents_0), 559 559 .flags = CLK_SET_RATE_PARENT, 560 560 .ops = &clk_rcg2_ops, 561 561 }, ··· 570 570 .clkr.hw.init = &(struct clk_init_data){ 571 571 .name = "gcc_qupv3_wrap0_s6_clk_src", 572 572 .parent_data = gcc_parents_0, 573 - .num_parents = 4, 573 + .num_parents = ARRAY_SIZE(gcc_parents_0), 574 574 .flags = CLK_SET_RATE_PARENT, 575 575 .ops = &clk_rcg2_ops, 576 576 }, ··· 585 585 .clkr.hw.init = &(struct clk_init_data){ 586 586 .name = "gcc_qupv3_wrap0_s7_clk_src", 587 587 .parent_data = gcc_parents_0, 588 - .num_parents = 4, 588 + .num_parents = ARRAY_SIZE(gcc_parents_0), 589 589 .flags = CLK_SET_RATE_PARENT, 590 590 .ops = &clk_rcg2_ops, 591 591 }, ··· 600 600 .clkr.hw.init = &(struct clk_init_data){ 601 601 .name = "gcc_qupv3_wrap1_s0_clk_src", 602 602 .parent_data = gcc_parents_0, 603 - .num_parents = 4, 603 + .num_parents = ARRAY_SIZE(gcc_parents_0), 604 604 .flags = CLK_SET_RATE_PARENT, 605 605 .ops = &clk_rcg2_ops, 606 606 }, ··· 615 615 .clkr.hw.init = &(struct clk_init_data){ 616 616 .name = "gcc_qupv3_wrap1_s1_clk_src", 617 617 .parent_data = gcc_parents_0, 618 - .num_parents = 4, 618 + .num_parents = ARRAY_SIZE(gcc_parents_0), 619 619 .flags = CLK_SET_RATE_PARENT, 620 620 .ops = &clk_rcg2_ops, 621 621 }, ··· 630 630 .clkr.hw.init = &(struct clk_init_data){ 631 631 .name = "gcc_qupv3_wrap1_s2_clk_src", 632 632 .parent_data = gcc_parents_0, 633 - .num_parents = 4, 633 + .num_parents = ARRAY_SIZE(gcc_parents_0), 634 634 .flags = CLK_SET_RATE_PARENT, 635 635 .ops = &clk_rcg2_ops, 636 636 }, ··· 645 645 .clkr.hw.init = &(struct clk_init_data){ 646 646 .name = "gcc_qupv3_wrap1_s3_clk_src", 647 647 .parent_data = gcc_parents_0, 648 - .num_parents = 4, 648 + .num_parents = ARRAY_SIZE(gcc_parents_0), 649 649 .flags = CLK_SET_RATE_PARENT, 650 650 .ops = &clk_rcg2_ops, 651 651 }, ··· 660 660 .clkr.hw.init = &(struct clk_init_data){ 661 661 .name = "gcc_qupv3_wrap1_s4_clk_src", 662 662 .parent_data = gcc_parents_0, 663 - .num_parents = 4, 663 + .num_parents = ARRAY_SIZE(gcc_parents_0), 664 664 .flags = CLK_SET_RATE_PARENT, 665 665 .ops = &clk_rcg2_ops, 666 666 }, ··· 675 675 .clkr.hw.init = &(struct clk_init_data){ 676 676 .name = "gcc_qupv3_wrap1_s5_clk_src", 677 677 .parent_data = gcc_parents_0, 678 - .num_parents = 4, 678 + .num_parents = ARRAY_SIZE(gcc_parents_0), 679 679 .flags = CLK_SET_RATE_PARENT, 680 680 .ops = &clk_rcg2_ops, 681 681 }, ··· 690 690 .clkr.hw.init = &(struct clk_init_data){ 691 691 .name = "gcc_qupv3_wrap2_s0_clk_src", 692 692 .parent_data = gcc_parents_0, 693 - .num_parents = 4, 693 + .num_parents = ARRAY_SIZE(gcc_parents_0), 694 694 .flags = CLK_SET_RATE_PARENT, 695 695 .ops = &clk_rcg2_ops, 696 696 }, ··· 705 705 .clkr.hw.init = &(struct clk_init_data){ 706 706 .name = "gcc_qupv3_wrap2_s1_clk_src", 707 707 .parent_data = gcc_parents_0, 708 - .num_parents = 4, 708 + .num_parents = ARRAY_SIZE(gcc_parents_0), 709 709 .flags = CLK_SET_RATE_PARENT, 710 710 .ops = &clk_rcg2_ops, 711 711 }, ··· 720 720 .clkr.hw.init = &(struct clk_init_data){ 721 721 .name = "gcc_qupv3_wrap2_s2_clk_src", 722 722 .parent_data = gcc_parents_0, 723 - .num_parents = 4, 723 + .num_parents = ARRAY_SIZE(gcc_parents_0), 724 724 .flags = CLK_SET_RATE_PARENT, 725 725 .ops = &clk_rcg2_ops, 726 726 }, ··· 735 735 .clkr.hw.init = &(struct clk_init_data){ 736 736 .name = "gcc_qupv3_wrap2_s3_clk_src", 737 737 .parent_data = gcc_parents_0, 738 - .num_parents = 4, 738 + .num_parents = ARRAY_SIZE(gcc_parents_0), 739 739 .flags = CLK_SET_RATE_PARENT, 740 740 .ops = &clk_rcg2_ops, 741 741 }, ··· 750 750 .clkr.hw.init = &(struct clk_init_data){ 751 751 .name = "gcc_qupv3_wrap2_s4_clk_src", 752 752 .parent_data = gcc_parents_0, 753 - .num_parents = 4, 753 + .num_parents = ARRAY_SIZE(gcc_parents_0), 754 754 .flags = CLK_SET_RATE_PARENT, 755 755 .ops = &clk_rcg2_ops, 756 756 }, ··· 765 765 .clkr.hw.init = &(struct clk_init_data){ 766 766 .name = "gcc_qupv3_wrap2_s5_clk_src", 767 767 .parent_data = gcc_parents_0, 768 - .num_parents = 4, 768 + .num_parents = ARRAY_SIZE(gcc_parents_0), 769 769 .flags = CLK_SET_RATE_PARENT, 770 770 .ops = &clk_rcg2_ops, 771 771 }, ··· 791 791 .clkr.hw.init = &(struct clk_init_data){ 792 792 .name = "gcc_sdcc2_apps_clk_src", 793 793 .parent_data = gcc_parents_6, 794 - .num_parents = 5, 794 + .num_parents = ARRAY_SIZE(gcc_parents_6), 795 795 .flags = CLK_SET_RATE_PARENT, 796 796 .ops = &clk_rcg2_floor_ops, 797 797 }, ··· 816 816 .clkr.hw.init = &(struct clk_init_data){ 817 817 .name = "gcc_sdcc4_apps_clk_src", 818 818 .parent_data = gcc_parents_3, 819 - .num_parents = 3, 819 + .num_parents = ARRAY_SIZE(gcc_parents_3), 820 820 .flags = CLK_SET_RATE_PARENT, 821 821 .ops = &clk_rcg2_floor_ops, 822 822 }, ··· 836 836 .clkr.hw.init = &(struct clk_init_data){ 837 837 .name = "gcc_tsif_ref_clk_src", 838 838 .parent_data = gcc_parents_7, 839 - .num_parents = 5, 839 + .num_parents = ARRAY_SIZE(gcc_parents_7), 840 840 .flags = CLK_SET_RATE_PARENT, 841 841 .ops = &clk_rcg2_ops, 842 842 }, ··· 860 860 .clkr.hw.init = &(struct clk_init_data){ 861 861 .name = "gcc_ufs_card_axi_clk_src", 862 862 .parent_data = gcc_parents_0, 863 - .num_parents = 4, 863 + .num_parents = ARRAY_SIZE(gcc_parents_0), 864 864 .flags = CLK_SET_RATE_PARENT, 865 865 .ops = &clk_rcg2_ops, 866 866 }, ··· 883 883 .clkr.hw.init = &(struct clk_init_data){ 884 884 .name = "gcc_ufs_card_ice_core_clk_src", 885 885 .parent_data = gcc_parents_0, 886 - .num_parents = 4, 886 + .num_parents = ARRAY_SIZE(gcc_parents_0), 887 887 .flags = CLK_SET_RATE_PARENT, 888 888 .ops = &clk_rcg2_ops, 889 889 }, ··· 903 903 .clkr.hw.init = &(struct clk_init_data){ 904 904 .name = "gcc_ufs_card_phy_aux_clk_src", 905 905 .parent_data = gcc_parents_4, 906 - .num_parents = 2, 906 + .num_parents = ARRAY_SIZE(gcc_parents_4), 907 907 .flags = CLK_SET_RATE_PARENT, 908 908 .ops = &clk_rcg2_ops, 909 909 }, ··· 925 925 .clkr.hw.init = &(struct clk_init_data){ 926 926 .name = "gcc_ufs_card_unipro_core_clk_src", 927 927 .parent_data = gcc_parents_0, 928 - .num_parents = 4, 928 + .num_parents = ARRAY_SIZE(gcc_parents_0), 929 929 .flags = CLK_SET_RATE_PARENT, 930 930 .ops = &clk_rcg2_ops, 931 931 }, ··· 949 949 .clkr.hw.init = &(struct clk_init_data){ 950 950 .name = "gcc_ufs_phy_axi_clk_src", 951 951 .parent_data = gcc_parents_0, 952 - .num_parents = 4, 952 + .num_parents = ARRAY_SIZE(gcc_parents_0), 953 953 .flags = CLK_SET_RATE_PARENT, 954 954 .ops = &clk_rcg2_ops, 955 955 }, ··· 964 964 .clkr.hw.init = &(struct clk_init_data){ 965 965 .name = "gcc_ufs_phy_ice_core_clk_src", 966 966 .parent_data = gcc_parents_0, 967 - .num_parents = 4, 967 + .num_parents = ARRAY_SIZE(gcc_parents_0), 968 968 .flags = CLK_SET_RATE_PARENT, 969 969 .ops = &clk_rcg2_ops, 970 970 }, ··· 979 979 .clkr.hw.init = &(struct clk_init_data){ 980 980 .name = "gcc_ufs_phy_phy_aux_clk_src", 981 981 .parent_data = gcc_parents_4, 982 - .num_parents = 2, 982 + .num_parents = ARRAY_SIZE(gcc_parents_4), 983 983 .flags = CLK_SET_RATE_PARENT, 984 984 .ops = &clk_rcg2_ops, 985 985 }, ··· 994 994 .clkr.hw.init = &(struct clk_init_data){ 995 995 .name = "gcc_ufs_phy_unipro_core_clk_src", 996 996 .parent_data = gcc_parents_0, 997 - .num_parents = 4, 997 + .num_parents = ARRAY_SIZE(gcc_parents_0), 998 998 .flags = CLK_SET_RATE_PARENT, 999 999 .ops = &clk_rcg2_ops, 1000 1000 }, ··· 1018 1018 .clkr.hw.init = &(struct clk_init_data){ 1019 1019 .name = "gcc_usb30_prim_master_clk_src", 1020 1020 .parent_data = gcc_parents_0, 1021 - .num_parents = 4, 1021 + .num_parents = ARRAY_SIZE(gcc_parents_0), 1022 1022 .flags = CLK_SET_RATE_PARENT, 1023 1023 .ops = &clk_rcg2_ops, 1024 1024 }, ··· 1040 1040 .clkr.hw.init = &(struct clk_init_data){ 1041 1041 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1042 1042 .parent_data = gcc_parents_0, 1043 - .num_parents = 4, 1043 + .num_parents = ARRAY_SIZE(gcc_parents_0), 1044 1044 .flags = CLK_SET_RATE_PARENT, 1045 1045 .ops = &clk_rcg2_ops, 1046 1046 }, ··· 1055 1055 .clkr.hw.init = &(struct clk_init_data){ 1056 1056 .name = "gcc_usb30_sec_master_clk_src", 1057 1057 .parent_data = gcc_parents_0, 1058 - .num_parents = 4, 1058 + .num_parents = ARRAY_SIZE(gcc_parents_0), 1059 1059 .flags = CLK_SET_RATE_PARENT, 1060 1060 .ops = &clk_rcg2_ops, 1061 1061 }, ··· 1070 1070 .clkr.hw.init = &(struct clk_init_data){ 1071 1071 .name = "gcc_usb30_sec_mock_utmi_clk_src", 1072 1072 .parent_data = gcc_parents_0, 1073 - .num_parents = 4, 1073 + .num_parents = ARRAY_SIZE(gcc_parents_0), 1074 1074 .flags = CLK_SET_RATE_PARENT, 1075 1075 .ops = &clk_rcg2_ops, 1076 1076 }, ··· 1085 1085 .clkr.hw.init = &(struct clk_init_data){ 1086 1086 .name = "gcc_usb3_prim_phy_aux_clk_src", 1087 1087 .parent_data = gcc_parents_2, 1088 - .num_parents = 3, 1088 + .num_parents = ARRAY_SIZE(gcc_parents_2), 1089 1089 .flags = CLK_SET_RATE_PARENT, 1090 1090 .ops = &clk_rcg2_ops, 1091 1091 }, ··· 1100 1100 .clkr.hw.init = &(struct clk_init_data){ 1101 1101 .name = "gcc_usb3_sec_phy_aux_clk_src", 1102 1102 .parent_data = gcc_parents_2, 1103 - .num_parents = 3, 1103 + .num_parents = ARRAY_SIZE(gcc_parents_2), 1104 1104 .flags = CLK_SET_RATE_PARENT, 1105 1105 .ops = &clk_rcg2_ops, 1106 1106 },