clk: qcom: gcc-sc8180x: use ARRAY_SIZE instead of specifying num_parents

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210405224743.590029-31-dmitry.baryshkov@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

Dmitry Baryshkov and committed by

Stephen Boyd 5 years ago b6cf77a7 e957ca2a

+61 -61

1 changed file

expand all

drivers

clk

qcom

gcc-sc8180x.c

+61 -61

drivers/clk/qcom/gcc-sc8180x.c

··· 277 277 .clkr.hw.init = &(struct clk_init_data){ 278 278 .name = "gcc_cpuss_ahb_clk_src", 279 279 .parent_data = gcc_parents_0, 280 - .num_parents = 3, 280 + .num_parents = ARRAY_SIZE(gcc_parents_0), 281 281 .flags = CLK_SET_RATE_PARENT, 282 282 .ops = &clk_rcg2_ops, 283 283 }, ··· 300 300 .clkr.hw.init = &(struct clk_init_data){ 301 301 .name = "gcc_emac_ptp_clk_src", 302 302 .parent_data = gcc_parents_6, 303 - .num_parents = 4, 303 + .num_parents = ARRAY_SIZE(gcc_parents_6), 304 304 .flags = CLK_SET_RATE_PARENT, 305 305 .ops = &clk_rcg2_ops, 306 306 }, ··· 326 326 .clkr.hw.init = &(struct clk_init_data){ 327 327 .name = "gcc_emac_rgmii_clk_src", 328 328 .parent_data = gcc_parents_6, 329 - .num_parents = 4, 329 + .num_parents = ARRAY_SIZE(gcc_parents_6), 330 330 .flags = CLK_SET_RATE_PARENT, 331 331 .ops = &clk_rcg2_ops, 332 332 }, ··· 350 350 .clkr.hw.init = &(struct clk_init_data){ 351 351 .name = "gcc_gp1_clk_src", 352 352 .parent_data = gcc_parents_1, 353 - .num_parents = 4, 353 + .num_parents = ARRAY_SIZE(gcc_parents_1), 354 354 .flags = CLK_SET_RATE_PARENT, 355 355 .ops = &clk_rcg2_ops, 356 356 }, ··· 365 365 .clkr.hw.init = &(struct clk_init_data){ 366 366 .name = "gcc_gp2_clk_src", 367 367 .parent_data = gcc_parents_1, 368 - .num_parents = 4, 368 + .num_parents = ARRAY_SIZE(gcc_parents_1), 369 369 .flags = CLK_SET_RATE_PARENT, 370 370 .ops = &clk_rcg2_ops, 371 371 }, ··· 380 380 .clkr.hw.init = &(struct clk_init_data){ 381 381 .name = "gcc_gp3_clk_src", 382 382 .parent_data = gcc_parents_1, 383 - .num_parents = 4, 383 + .num_parents = ARRAY_SIZE(gcc_parents_1), 384 384 .flags = CLK_SET_RATE_PARENT, 385 385 .ops = &clk_rcg2_ops, 386 386 }, ··· 395 395 .clkr.hw.init = &(struct clk_init_data){ 396 396 .name = "gcc_gp4_clk_src", 397 397 .parent_data = gcc_parents_1, 398 - .num_parents = 4, 398 + .num_parents = ARRAY_SIZE(gcc_parents_1), 399 399 .flags = CLK_SET_RATE_PARENT, 400 400 .ops = &clk_rcg2_ops, 401 401 }, ··· 410 410 .clkr.hw.init = &(struct clk_init_data){ 411 411 .name = "gcc_gp5_clk_src", 412 412 .parent_data = gcc_parents_1, 413 - .num_parents = 4, 413 + .num_parents = ARRAY_SIZE(gcc_parents_1), 414 414 .flags = CLK_SET_RATE_PARENT, 415 415 .ops = &clk_rcg2_ops, 416 416 }, ··· 436 436 .clkr.hw.init = &(struct clk_init_data){ 437 437 .name = "gcc_npu_axi_clk_src", 438 438 .parent_data = gcc_parents_3, 439 - .num_parents = 7, 439 + .num_parents = ARRAY_SIZE(gcc_parents_3), 440 440 .flags = CLK_SET_RATE_PARENT, 441 441 .ops = &clk_rcg2_ops, 442 442 }, ··· 457 457 .clkr.hw.init = &(struct clk_init_data){ 458 458 .name = "gcc_pcie_0_aux_clk_src", 459 459 .parent_data = gcc_parents_2, 460 - .num_parents = 2, 460 + .num_parents = ARRAY_SIZE(gcc_parents_2), 461 461 .flags = CLK_SET_RATE_PARENT, 462 462 .ops = &clk_rcg2_ops, 463 463 }, ··· 472 472 .clkr.hw.init = &(struct clk_init_data){ 473 473 .name = "gcc_pcie_1_aux_clk_src", 474 474 .parent_data = gcc_parents_2, 475 - .num_parents = 2, 475 + .num_parents = ARRAY_SIZE(gcc_parents_2), 476 476 .flags = CLK_SET_RATE_PARENT, 477 477 .ops = &clk_rcg2_ops, 478 478 }, ··· 487 487 .clkr.hw.init = &(struct clk_init_data){ 488 488 .name = "gcc_pcie_2_aux_clk_src", 489 489 .parent_data = gcc_parents_2, 490 - .num_parents = 2, 490 + .num_parents = ARRAY_SIZE(gcc_parents_2), 491 491 .flags = CLK_SET_RATE_PARENT, 492 492 .ops = &clk_rcg2_ops, 493 493 }, ··· 502 502 .clkr.hw.init = &(struct clk_init_data){ 503 503 .name = "gcc_pcie_3_aux_clk_src", 504 504 .parent_data = gcc_parents_2, 505 - .num_parents = 2, 505 + .num_parents = ARRAY_SIZE(gcc_parents_2), 506 506 .flags = CLK_SET_RATE_PARENT, 507 507 .ops = &clk_rcg2_ops, 508 508 }, ··· 523 523 .clkr.hw.init = &(struct clk_init_data){ 524 524 .name = "gcc_pcie_phy_refgen_clk_src", 525 525 .parent_data = gcc_parents_0, 526 - .num_parents = 3, 526 + .num_parents = ARRAY_SIZE(gcc_parents_0), 527 527 .flags = CLK_SET_RATE_PARENT, 528 528 .ops = &clk_rcg2_ops, 529 529 }, ··· 545 545 .clkr.hw.init = &(struct clk_init_data){ 546 546 .name = "gcc_pdm2_clk_src", 547 547 .parent_data = gcc_parents_0, 548 - .num_parents = 3, 548 + .num_parents = ARRAY_SIZE(gcc_parents_0), 549 549 .flags = CLK_SET_RATE_PARENT, 550 550 .ops = &clk_rcg2_ops, 551 551 }, ··· 568 568 .clkr.hw.init = &(struct clk_init_data){ 569 569 .name = "gcc_qspi_1_core_clk_src", 570 570 .parent_data = gcc_parents_0, 571 - .num_parents = 3, 571 + .num_parents = ARRAY_SIZE(gcc_parents_0), 572 572 .flags = CLK_SET_RATE_PARENT, 573 573 .ops = &clk_rcg2_ops, 574 574 }, ··· 583 583 .clkr.hw.init = &(struct clk_init_data){ 584 584 .name = "gcc_qspi_core_clk_src", 585 585 .parent_data = gcc_parents_0, 586 - .num_parents = 3, 586 + .num_parents = ARRAY_SIZE(gcc_parents_0), 587 587 .flags = CLK_SET_RATE_PARENT, 588 588 .ops = &clk_rcg2_ops, 589 589 }, ··· 619 619 .clkr.hw.init = &(struct clk_init_data){ 620 620 .name = "gcc_qupv3_wrap0_s0_clk_src", 621 621 .parent_data = gcc_parents_0, 622 - .num_parents = 3, 622 + .num_parents = ARRAY_SIZE(gcc_parents_0), 623 623 .flags = CLK_SET_RATE_PARENT, 624 624 .ops = &clk_rcg2_ops, 625 625 }, ··· 634 634 .clkr.hw.init = &(struct clk_init_data){ 635 635 .name = "gcc_qupv3_wrap0_s1_clk_src", 636 636 .parent_data = gcc_parents_0, 637 - .num_parents = 3, 637 + .num_parents = ARRAY_SIZE(gcc_parents_0), 638 638 .flags = CLK_SET_RATE_PARENT, 639 639 .ops = &clk_rcg2_ops, 640 640 }, ··· 649 649 .clkr.hw.init = &(struct clk_init_data){ 650 650 .name = "gcc_qupv3_wrap0_s2_clk_src", 651 651 .parent_data = gcc_parents_0, 652 - .num_parents = 3, 652 + .num_parents = ARRAY_SIZE(gcc_parents_0), 653 653 .flags = CLK_SET_RATE_PARENT, 654 654 .ops = &clk_rcg2_ops, 655 655 }, ··· 664 664 .clkr.hw.init = &(struct clk_init_data){ 665 665 .name = "gcc_qupv3_wrap0_s3_clk_src", 666 666 .parent_data = gcc_parents_0, 667 - .num_parents = 3, 667 + .num_parents = ARRAY_SIZE(gcc_parents_0), 668 668 .flags = CLK_SET_RATE_PARENT, 669 669 .ops = &clk_rcg2_ops, 670 670 }, ··· 679 679 .clkr.hw.init = &(struct clk_init_data){ 680 680 .name = "gcc_qupv3_wrap0_s4_clk_src", 681 681 .parent_data = gcc_parents_0, 682 - .num_parents = 3, 682 + .num_parents = ARRAY_SIZE(gcc_parents_0), 683 683 .flags = CLK_SET_RATE_PARENT, 684 684 .ops = &clk_rcg2_ops, 685 685 }, ··· 694 694 .clkr.hw.init = &(struct clk_init_data){ 695 695 .name = "gcc_qupv3_wrap0_s5_clk_src", 696 696 .parent_data = gcc_parents_0, 697 - .num_parents = 3, 697 + .num_parents = ARRAY_SIZE(gcc_parents_0), 698 698 .flags = CLK_SET_RATE_PARENT, 699 699 .ops = &clk_rcg2_ops, 700 700 }, ··· 709 709 .clkr.hw.init = &(struct clk_init_data){ 710 710 .name = "gcc_qupv3_wrap0_s6_clk_src", 711 711 .parent_data = gcc_parents_0, 712 - .num_parents = 3, 712 + .num_parents = ARRAY_SIZE(gcc_parents_0), 713 713 .flags = CLK_SET_RATE_PARENT, 714 714 .ops = &clk_rcg2_ops, 715 715 }, ··· 724 724 .clkr.hw.init = &(struct clk_init_data){ 725 725 .name = "gcc_qupv3_wrap0_s7_clk_src", 726 726 .parent_data = gcc_parents_0, 727 - .num_parents = 3, 727 + .num_parents = ARRAY_SIZE(gcc_parents_0), 728 728 .flags = CLK_SET_RATE_PARENT, 729 729 .ops = &clk_rcg2_ops, 730 730 }, ··· 739 739 .clkr.hw.init = &(struct clk_init_data){ 740 740 .name = "gcc_qupv3_wrap1_s0_clk_src", 741 741 .parent_data = gcc_parents_0, 742 - .num_parents = 3, 742 + .num_parents = ARRAY_SIZE(gcc_parents_0), 743 743 .flags = CLK_SET_RATE_PARENT, 744 744 .ops = &clk_rcg2_ops, 745 745 }, ··· 754 754 .clkr.hw.init = &(struct clk_init_data){ 755 755 .name = "gcc_qupv3_wrap1_s1_clk_src", 756 756 .parent_data = gcc_parents_0, 757 - .num_parents = 3, 757 + .num_parents = ARRAY_SIZE(gcc_parents_0), 758 758 .flags = CLK_SET_RATE_PARENT, 759 759 .ops = &clk_rcg2_ops, 760 760 }, ··· 769 769 .clkr.hw.init = &(struct clk_init_data){ 770 770 .name = "gcc_qupv3_wrap1_s2_clk_src", 771 771 .parent_data = gcc_parents_0, 772 - .num_parents = 3, 772 + .num_parents = ARRAY_SIZE(gcc_parents_0), 773 773 .flags = CLK_SET_RATE_PARENT, 774 774 .ops = &clk_rcg2_ops, 775 775 }, ··· 784 784 .clkr.hw.init = &(struct clk_init_data){ 785 785 .name = "gcc_qupv3_wrap1_s3_clk_src", 786 786 .parent_data = gcc_parents_0, 787 - .num_parents = 3, 787 + .num_parents = ARRAY_SIZE(gcc_parents_0), 788 788 .flags = CLK_SET_RATE_PARENT, 789 789 .ops = &clk_rcg2_ops, 790 790 }, ··· 799 799 .clkr.hw.init = &(struct clk_init_data){ 800 800 .name = "gcc_qupv3_wrap1_s4_clk_src", 801 801 .parent_data = gcc_parents_0, 802 - .num_parents = 3, 802 + .num_parents = ARRAY_SIZE(gcc_parents_0), 803 803 .flags = CLK_SET_RATE_PARENT, 804 804 .ops = &clk_rcg2_ops, 805 805 }, ··· 814 814 .clkr.hw.init = &(struct clk_init_data){ 815 815 .name = "gcc_qupv3_wrap1_s5_clk_src", 816 816 .parent_data = gcc_parents_0, 817 - .num_parents = 3, 817 + .num_parents = ARRAY_SIZE(gcc_parents_0), 818 818 .flags = CLK_SET_RATE_PARENT, 819 819 .ops = &clk_rcg2_ops, 820 820 }, ··· 829 829 .clkr.hw.init = &(struct clk_init_data){ 830 830 .name = "gcc_qupv3_wrap2_s0_clk_src", 831 831 .parent_data = gcc_parents_0, 832 - .num_parents = 3, 832 + .num_parents = ARRAY_SIZE(gcc_parents_0), 833 833 .flags = CLK_SET_RATE_PARENT, 834 834 .ops = &clk_rcg2_ops, 835 835 }, ··· 844 844 .clkr.hw.init = &(struct clk_init_data){ 845 845 .name = "gcc_qupv3_wrap2_s1_clk_src", 846 846 .parent_data = gcc_parents_0, 847 - .num_parents = 3, 847 + .num_parents = ARRAY_SIZE(gcc_parents_0), 848 848 .flags = CLK_SET_RATE_PARENT, 849 849 .ops = &clk_rcg2_ops, 850 850 }, ··· 859 859 .clkr.hw.init = &(struct clk_init_data){ 860 860 .name = "gcc_qupv3_wrap2_s2_clk_src", 861 861 .parent_data = gcc_parents_0, 862 - .num_parents = 3, 862 + .num_parents = ARRAY_SIZE(gcc_parents_0), 863 863 .flags = CLK_SET_RATE_PARENT, 864 864 .ops = &clk_rcg2_ops, 865 865 }, ··· 874 874 .clkr.hw.init = &(struct clk_init_data){ 875 875 .name = "gcc_qupv3_wrap2_s3_clk_src", 876 876 .parent_data = gcc_parents_0, 877 - .num_parents = 3, 877 + .num_parents = ARRAY_SIZE(gcc_parents_0), 878 878 .flags = CLK_SET_RATE_PARENT, 879 879 .ops = &clk_rcg2_ops, 880 880 }, ··· 889 889 .clkr.hw.init = &(struct clk_init_data){ 890 890 .name = "gcc_qupv3_wrap2_s4_clk_src", 891 891 .parent_data = gcc_parents_0, 892 - .num_parents = 3, 892 + .num_parents = ARRAY_SIZE(gcc_parents_0), 893 893 .flags = CLK_SET_RATE_PARENT, 894 894 .ops = &clk_rcg2_ops, 895 895 }, ··· 904 904 .clkr.hw.init = &(struct clk_init_data){ 905 905 .name = "gcc_qupv3_wrap2_s5_clk_src", 906 906 .parent_data = gcc_parents_0, 907 - .num_parents = 3, 907 + .num_parents = ARRAY_SIZE(gcc_parents_0), 908 908 .flags = CLK_SET_RATE_PARENT, 909 909 .ops = &clk_rcg2_ops, 910 910 }, ··· 930 930 .clkr.hw.init = &(struct clk_init_data){ 931 931 .name = "gcc_sdcc2_apps_clk_src", 932 932 .parent_data = gcc_parents_7, 933 - .num_parents = 5, 933 + .num_parents = ARRAY_SIZE(gcc_parents_7), 934 934 .flags = CLK_SET_RATE_PARENT, 935 935 .ops = &clk_rcg2_floor_ops, 936 936 }, ··· 955 955 .clkr.hw.init = &(struct clk_init_data){ 956 956 .name = "gcc_sdcc4_apps_clk_src", 957 957 .parent_data = gcc_parents_5, 958 - .num_parents = 3, 958 + .num_parents = ARRAY_SIZE(gcc_parents_5), 959 959 .flags = CLK_SET_RATE_PARENT, 960 960 .ops = &clk_rcg2_floor_ops, 961 961 }, ··· 975 975 .clkr.hw.init = &(struct clk_init_data){ 976 976 .name = "gcc_tsif_ref_clk_src", 977 977 .parent_data = gcc_parents_8, 978 - .num_parents = 4, 978 + .num_parents = ARRAY_SIZE(gcc_parents_8), 979 979 .flags = CLK_SET_RATE_PARENT, 980 980 .ops = &clk_rcg2_ops, 981 981 }, ··· 998 998 .clkr.hw.init = &(struct clk_init_data){ 999 999 .name = "gcc_ufs_card_2_axi_clk_src", 1000 1000 .parent_data = gcc_parents_0, 1001 - .num_parents = 3, 1001 + .num_parents = ARRAY_SIZE(gcc_parents_0), 1002 1002 .flags = CLK_SET_RATE_PARENT, 1003 1003 .ops = &clk_rcg2_ops, 1004 1004 }, ··· 1013 1013 .clkr.hw.init = &(struct clk_init_data){ 1014 1014 .name = "gcc_ufs_card_2_ice_core_clk_src", 1015 1015 .parent_data = gcc_parents_0, 1016 - .num_parents = 3, 1016 + .num_parents = ARRAY_SIZE(gcc_parents_0), 1017 1017 .flags = CLK_SET_RATE_PARENT, 1018 1018 .ops = &clk_rcg2_ops, 1019 1019 }, ··· 1033 1033 .clkr.hw.init = &(struct clk_init_data){ 1034 1034 .name = "gcc_ufs_card_2_phy_aux_clk_src", 1035 1035 .parent_data = gcc_parents_4, 1036 - .num_parents = 1, 1036 + .num_parents = ARRAY_SIZE(gcc_parents_4), 1037 1037 .flags = CLK_SET_RATE_PARENT, 1038 1038 .ops = &clk_rcg2_ops, 1039 1039 }, ··· 1048 1048 .clkr.hw.init = &(struct clk_init_data){ 1049 1049 .name = "gcc_ufs_card_2_unipro_core_clk_src", 1050 1050 .parent_data = gcc_parents_0, 1051 - .num_parents = 3, 1051 + .num_parents = ARRAY_SIZE(gcc_parents_0), 1052 1052 .flags = CLK_SET_RATE_PARENT, 1053 1053 .ops = &clk_rcg2_ops, 1054 1054 }, ··· 1072 1072 .clkr.hw.init = &(struct clk_init_data){ 1073 1073 .name = "gcc_ufs_card_axi_clk_src", 1074 1074 .parent_data = gcc_parents_0, 1075 - .num_parents = 3, 1075 + .num_parents = ARRAY_SIZE(gcc_parents_0), 1076 1076 .flags = CLK_SET_RATE_PARENT, 1077 1077 .ops = &clk_rcg2_ops, 1078 1078 }, ··· 1094 1094 .clkr.hw.init = &(struct clk_init_data){ 1095 1095 .name = "gcc_ufs_card_ice_core_clk_src", 1096 1096 .parent_data = gcc_parents_0, 1097 - .num_parents = 3, 1097 + .num_parents = ARRAY_SIZE(gcc_parents_0), 1098 1098 .flags = CLK_SET_RATE_PARENT, 1099 1099 .ops = &clk_rcg2_ops, 1100 1100 }, ··· 1109 1109 .clkr.hw.init = &(struct clk_init_data){ 1110 1110 .name = "gcc_ufs_card_phy_aux_clk_src", 1111 1111 .parent_data = gcc_parents_4, 1112 - .num_parents = 1, 1112 + .num_parents = ARRAY_SIZE(gcc_parents_4), 1113 1113 .flags = CLK_SET_RATE_PARENT, 1114 1114 .ops = &clk_rcg2_ops, 1115 1115 }, ··· 1131 1131 .clkr.hw.init = &(struct clk_init_data){ 1132 1132 .name = "gcc_ufs_card_unipro_core_clk_src", 1133 1133 .parent_data = gcc_parents_0, 1134 - .num_parents = 3, 1134 + .num_parents = ARRAY_SIZE(gcc_parents_0), 1135 1135 .flags = CLK_SET_RATE_PARENT, 1136 1136 .ops = &clk_rcg2_ops, 1137 1137 }, ··· 1155 1155 .clkr.hw.init = &(struct clk_init_data){ 1156 1156 .name = "gcc_ufs_phy_axi_clk_src", 1157 1157 .parent_data = gcc_parents_0, 1158 - .num_parents = 3, 1158 + .num_parents = ARRAY_SIZE(gcc_parents_0), 1159 1159 .flags = CLK_SET_RATE_PARENT, 1160 1160 .ops = &clk_rcg2_ops, 1161 1161 }, ··· 1170 1170 .clkr.hw.init = &(struct clk_init_data){ 1171 1171 .name = "gcc_ufs_phy_ice_core_clk_src", 1172 1172 .parent_data = gcc_parents_0, 1173 - .num_parents = 3, 1173 + .num_parents = ARRAY_SIZE(gcc_parents_0), 1174 1174 .flags = CLK_SET_RATE_PARENT, 1175 1175 .ops = &clk_rcg2_ops, 1176 1176 }, ··· 1185 1185 .clkr.hw.init = &(struct clk_init_data){ 1186 1186 .name = "gcc_ufs_phy_phy_aux_clk_src", 1187 1187 .parent_data = gcc_parents_4, 1188 - .num_parents = 1, 1188 + .num_parents = ARRAY_SIZE(gcc_parents_4), 1189 1189 .flags = CLK_SET_RATE_PARENT, 1190 1190 .ops = &clk_rcg2_ops, 1191 1191 }, ··· 1200 1200 .clkr.hw.init = &(struct clk_init_data){ 1201 1201 .name = "gcc_ufs_phy_unipro_core_clk_src", 1202 1202 .parent_data = gcc_parents_0, 1203 - .num_parents = 3, 1203 + .num_parents = ARRAY_SIZE(gcc_parents_0), 1204 1204 .flags = CLK_SET_RATE_PARENT, 1205 1205 .ops = &clk_rcg2_ops, 1206 1206 }, ··· 1224 1224 .clkr.hw.init = &(struct clk_init_data){ 1225 1225 .name = "gcc_usb30_mp_master_clk_src", 1226 1226 .parent_data = gcc_parents_0, 1227 - .num_parents = 3, 1227 + .num_parents = ARRAY_SIZE(gcc_parents_0), 1228 1228 .flags = CLK_SET_RATE_PARENT, 1229 1229 .ops = &clk_rcg2_ops, 1230 1230 }, ··· 1247 1247 .clkr.hw.init = &(struct clk_init_data){ 1248 1248 .name = "gcc_usb30_mp_mock_utmi_clk_src", 1249 1249 .parent_data = gcc_parents_0, 1250 - .num_parents = 3, 1250 + .num_parents = ARRAY_SIZE(gcc_parents_0), 1251 1251 .flags = CLK_SET_RATE_PARENT, 1252 1252 .ops = &clk_rcg2_ops, 1253 1253 }, ··· 1262 1262 .clkr.hw.init = &(struct clk_init_data){ 1263 1263 .name = "gcc_usb30_prim_master_clk_src", 1264 1264 .parent_data = gcc_parents_0, 1265 - .num_parents = 3, 1265 + .num_parents = ARRAY_SIZE(gcc_parents_0), 1266 1266 .flags = CLK_SET_RATE_PARENT, 1267 1267 .ops = &clk_rcg2_ops, 1268 1268 }, ··· 1277 1277 .clkr.hw.init = &(struct clk_init_data){ 1278 1278 .name = "gcc_usb30_prim_mock_utmi_clk_src", 1279 1279 .parent_data = gcc_parents_0, 1280 - .num_parents = 3, 1280 + .num_parents = ARRAY_SIZE(gcc_parents_0), 1281 1281 .flags = CLK_SET_RATE_PARENT, 1282 1282 .ops = &clk_rcg2_ops, 1283 1283 }, ··· 1292 1292 .clkr.hw.init = &(struct clk_init_data){ 1293 1293 .name = "gcc_usb30_sec_master_clk_src", 1294 1294 .parent_data = gcc_parents_0, 1295 - .num_parents = 3, 1295 + .num_parents = ARRAY_SIZE(gcc_parents_0), 1296 1296 .flags = CLK_SET_RATE_PARENT, 1297 1297 .ops = &clk_rcg2_ops, 1298 1298 }, ··· 1307 1307 .clkr.hw.init = &(struct clk_init_data){ 1308 1308 .name = "gcc_usb30_sec_mock_utmi_clk_src", 1309 1309 .parent_data = gcc_parents_0, 1310 - .num_parents = 3, 1310 + .num_parents = ARRAY_SIZE(gcc_parents_0), 1311 1311 .flags = CLK_SET_RATE_PARENT, 1312 1312 .ops = &clk_rcg2_ops, 1313 1313 }, ··· 1322 1322 .clkr.hw.init = &(struct clk_init_data){ 1323 1323 .name = "gcc_usb3_mp_phy_aux_clk_src", 1324 1324 .parent_data = gcc_parents_2, 1325 - .num_parents = 2, 1325 + .num_parents = ARRAY_SIZE(gcc_parents_2), 1326 1326 .flags = CLK_SET_RATE_PARENT, 1327 1327 .ops = &clk_rcg2_ops, 1328 1328 }, ··· 1337 1337 .clkr.hw.init = &(struct clk_init_data){ 1338 1338 .name = "gcc_usb3_prim_phy_aux_clk_src", 1339 1339 .parent_data = gcc_parents_2, 1340 - .num_parents = 2, 1340 + .num_parents = ARRAY_SIZE(gcc_parents_2), 1341 1341 .flags = CLK_SET_RATE_PARENT, 1342 1342 .ops = &clk_rcg2_ops, 1343 1343 }, ··· 1352 1352 .clkr.hw.init = &(struct clk_init_data){ 1353 1353 .name = "gcc_usb3_sec_phy_aux_clk_src", 1354 1354 .parent_data = gcc_parents_2, 1355 - .num_parents = 2, 1355 + .num_parents = ARRAY_SIZE(gcc_parents_2), 1356 1356 .flags = CLK_SET_RATE_PARENT, 1357 1357 .ops = &clk_rcg2_ops, 1358 1358 },