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kernel
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linux
phy: qcom-qmp: move PCS V2 registers to separate header
Move PCS V2 registers to the separate header.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220705094320.1313312-14-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Dmitry Baryshkov
and committed by
Vinod Koul
5ae11aa4
147924ff
+39
-28
+38
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h
+38
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v2.h
···
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_PCS_V2_H_
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#define QCOM_PHY_QMP_PCS_V2_H_
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/* Only for QMP V2 PHY - PCS registers */
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#define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x004
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#define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x024
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#define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x028
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#define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL 0x034
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#define QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL 0x038
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#define QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL 0x03c
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#define QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL 0x040
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#define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x054
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#define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x058
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#define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x060
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#define QPHY_V2_PCS_POWER_STATE_CONFIG2 0x064
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#define QPHY_V2_PCS_POWER_STATE_CONFIG4 0x06c
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#define QPHY_V2_PCS_LOCK_DETECT_CONFIG1 0x080
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#define QPHY_V2_PCS_LOCK_DETECT_CONFIG2 0x084
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#define QPHY_V2_PCS_LOCK_DETECT_CONFIG3 0x088
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#define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0
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#define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4
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#define QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0x0cc
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#define QPHY_V2_PCS_RX_SYM_RESYNC_CTRL 0x13c
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#define QPHY_V2_PCS_RX_MIN_HIBERN8_TIME 0x140
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#define QPHY_V2_PCS_RX_SIGDET_CTRL2 0x148
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#define QPHY_V2_PCS_RX_PWM_GEAR_BAND 0x154
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#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8
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#define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac
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#define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8
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#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
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#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
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#endif
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drivers/phy/qualcomm/phy-qcom-qmp.h
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drivers/phy/qualcomm/phy-qcom-qmp.h
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#include "phy-qcom-qmp-qserdes-pll.h"
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/* Only for QMP V2 PHY - PCS registers */
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#define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x04
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#define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x24
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#define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x28
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#define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL 0x34
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#define QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL 0x38
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#define QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL 0x3c
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#define QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL 0x40
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#define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x54
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#define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x58
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#define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x60
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#define QPHY_V2_PCS_POWER_STATE_CONFIG2 0x64
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#define QPHY_V2_PCS_POWER_STATE_CONFIG4 0x6c
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#define QPHY_V2_PCS_LOCK_DETECT_CONFIG1 0x80
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#define QPHY_V2_PCS_LOCK_DETECT_CONFIG2 0x84
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#define QPHY_V2_PCS_LOCK_DETECT_CONFIG3 0x88
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#define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0
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#define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4
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#define QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0xcc
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#define QPHY_V2_PCS_RX_SYM_RESYNC_CTRL 0x13c
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#define QPHY_V2_PCS_RX_MIN_HIBERN8_TIME 0x140
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#define QPHY_V2_PCS_RX_SIGDET_CTRL2 0x148
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#define QPHY_V2_PCS_RX_PWM_GEAR_BAND 0x154
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#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8
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#define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac
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#define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8
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#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
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#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
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#include "phy-qcom-qmp-pcs-v2.h"
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/* Only for QMP V3 & V4 PHY - DP COM registers */
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#define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00