tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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phy: qcom-qmp: move QSERDES PLL registers to separate header

Move QSERDES PLL registers to the separate header. This register set is
unique for the IPQ PCIe Gen3 PHYs.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220705094320.1313312-13-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Dmitry Baryshkov and committed by
Vinod Koul 147924ff f1f923ad

+67 -57
+66
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-pll.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 + */ 5 + 6 + #ifndef QCOM_PHY_QMP_QSERDES_PLL_H_ 7 + #define QCOM_PHY_QMP_QSERDES_PLL_H_ 8 + 9 + /* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */ 10 + #define QSERDES_PLL_BG_TIMER 0x00c 11 + #define QSERDES_PLL_SSC_PER1 0x01c 12 + #define QSERDES_PLL_SSC_PER2 0x020 13 + #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024 14 + #define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028 15 + #define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c 16 + #define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030 17 + #define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c 18 + #define QSERDES_PLL_CLK_ENABLE1 0x040 19 + #define QSERDES_PLL_SYS_CLK_CTRL 0x044 20 + #define QSERDES_PLL_SYSCLK_BUF_ENABLE 0x048 21 + #define QSERDES_PLL_PLL_IVCO 0x050 22 + #define QSERDES_PLL_LOCK_CMP1_MODE0 0x054 23 + #define QSERDES_PLL_LOCK_CMP2_MODE0 0x058 24 + #define QSERDES_PLL_LOCK_CMP1_MODE1 0x060 25 + #define QSERDES_PLL_LOCK_CMP2_MODE1 0x064 26 + #define QSERDES_PLL_BG_TRIM 0x074 27 + #define QSERDES_PLL_CLK_EP_DIV_MODE0 0x078 28 + #define QSERDES_PLL_CLK_EP_DIV_MODE1 0x07c 29 + #define QSERDES_PLL_CP_CTRL_MODE0 0x080 30 + #define QSERDES_PLL_CP_CTRL_MODE1 0x084 31 + #define QSERDES_PLL_PLL_RCTRL_MODE0 0x088 32 + #define QSERDES_PLL_PLL_RCTRL_MODE1 0x08c 33 + #define QSERDES_PLL_PLL_CCTRL_MODE0 0x090 34 + #define QSERDES_PLL_PLL_CCTRL_MODE1 0x094 35 + #define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x0a4 36 + #define QSERDES_PLL_SYSCLK_EN_SEL 0x0a8 37 + #define QSERDES_PLL_RESETSM_CNTRL 0x0b0 38 + #define QSERDES_PLL_LOCK_CMP_EN 0x0c4 39 + #define QSERDES_PLL_DEC_START_MODE0 0x0cc 40 + #define QSERDES_PLL_DEC_START_MODE1 0x0d0 41 + #define QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0d8 42 + #define QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0dc 43 + #define QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0e0 44 + #define QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0e4 45 + #define QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0e8 46 + #define QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0ec 47 + #define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x100 48 + #define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x104 49 + #define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x108 50 + #define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x10c 51 + #define QSERDES_PLL_VCO_TUNE_MAP 0x120 52 + #define QSERDES_PLL_VCO_TUNE1_MODE0 0x124 53 + #define QSERDES_PLL_VCO_TUNE2_MODE0 0x128 54 + #define QSERDES_PLL_VCO_TUNE1_MODE1 0x12c 55 + #define QSERDES_PLL_VCO_TUNE2_MODE1 0x130 56 + #define QSERDES_PLL_VCO_TUNE_TIMER1 0x13c 57 + #define QSERDES_PLL_VCO_TUNE_TIMER2 0x140 58 + #define QSERDES_PLL_CLK_SELECT 0x16c 59 + #define QSERDES_PLL_HSCLK_SEL 0x170 60 + #define QSERDES_PLL_CORECLK_DIV 0x17c 61 + #define QSERDES_PLL_CORE_CLK_EN 0x184 62 + #define QSERDES_PLL_CMN_CONFIG 0x18c 63 + #define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194 64 + #define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4 65 + 66 + #endif
+1 -57
drivers/phy/qualcomm/phy-qcom-qmp.h
··· 18 18 #include "phy-qcom-qmp-qserdes-com-v5.h" 19 19 #include "phy-qcom-qmp-qserdes-txrx-v5.h" 20 20 21 - /* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */ 22 - 23 - #define QSERDES_PLL_BG_TIMER 0x00c 24 - #define QSERDES_PLL_SSC_PER1 0x01c 25 - #define QSERDES_PLL_SSC_PER2 0x020 26 - #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024 27 - #define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028 28 - #define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c 29 - #define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030 30 - #define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c 31 - #define QSERDES_PLL_CLK_ENABLE1 0x040 32 - #define QSERDES_PLL_SYS_CLK_CTRL 0x044 33 - #define QSERDES_PLL_SYSCLK_BUF_ENABLE 0x048 34 - #define QSERDES_PLL_PLL_IVCO 0x050 35 - #define QSERDES_PLL_LOCK_CMP1_MODE0 0x054 36 - #define QSERDES_PLL_LOCK_CMP2_MODE0 0x058 37 - #define QSERDES_PLL_LOCK_CMP1_MODE1 0x060 38 - #define QSERDES_PLL_LOCK_CMP2_MODE1 0x064 39 - #define QSERDES_PLL_BG_TRIM 0x074 40 - #define QSERDES_PLL_CLK_EP_DIV_MODE0 0x078 41 - #define QSERDES_PLL_CLK_EP_DIV_MODE1 0x07c 42 - #define QSERDES_PLL_CP_CTRL_MODE0 0x080 43 - #define QSERDES_PLL_CP_CTRL_MODE1 0x084 44 - #define QSERDES_PLL_PLL_RCTRL_MODE0 0x088 45 - #define QSERDES_PLL_PLL_RCTRL_MODE1 0x08c 46 - #define QSERDES_PLL_PLL_CCTRL_MODE0 0x090 47 - #define QSERDES_PLL_PLL_CCTRL_MODE1 0x094 48 - #define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x0a4 49 - #define QSERDES_PLL_SYSCLK_EN_SEL 0x0a8 50 - #define QSERDES_PLL_RESETSM_CNTRL 0x0b0 51 - #define QSERDES_PLL_LOCK_CMP_EN 0x0c4 52 - #define QSERDES_PLL_DEC_START_MODE0 0x0cc 53 - #define QSERDES_PLL_DEC_START_MODE1 0x0d0 54 - #define QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0d8 55 - #define QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0dc 56 - #define QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0e0 57 - #define QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0e4 58 - #define QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0e8 59 - #define QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0ec 60 - #define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x100 61 - #define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x104 62 - #define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x108 63 - #define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x10c 64 - #define QSERDES_PLL_VCO_TUNE_MAP 0x120 65 - #define QSERDES_PLL_VCO_TUNE1_MODE0 0x124 66 - #define QSERDES_PLL_VCO_TUNE2_MODE0 0x128 67 - #define QSERDES_PLL_VCO_TUNE1_MODE1 0x12c 68 - #define QSERDES_PLL_VCO_TUNE2_MODE1 0x130 69 - #define QSERDES_PLL_VCO_TUNE_TIMER1 0x13c 70 - #define QSERDES_PLL_VCO_TUNE_TIMER2 0x140 71 - #define QSERDES_PLL_CLK_SELECT 0x16c 72 - #define QSERDES_PLL_HSCLK_SEL 0x170 73 - #define QSERDES_PLL_CORECLK_DIV 0x17c 74 - #define QSERDES_PLL_CORE_CLK_EN 0x184 75 - #define QSERDES_PLL_CMN_CONFIG 0x18c 76 - #define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194 77 - #define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4 21 + #include "phy-qcom-qmp-qserdes-pll.h" 78 22 79 23 /* Only for QMP V2 PHY - PCS registers */ 80 24 #define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x04