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ARM: dts: rockchip: Add Ethernet GMAC node for RV1126

Rockchip RV1126 has GMAC 10/100/1000M ethernet controller

Co-Developed-by: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Anand Moon <anand@edgeble.ai>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Link: https://lore.kernel.org/r/20230111172437.5295-3-anand@edgeble.ai
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

authored by

Anand Moon and committed by
Heiko Stuebner
594a76a4 bdcb1f4e

+49
+49
arch/arm/boot/dts/rv1126.dtsi
··· 332 332 clock-names = "pclk", "timer"; 333 333 }; 334 334 335 + gmac: ethernet@ffc40000 { 336 + compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a"; 337 + reg = <0xffc40000 0x4000>; 338 + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 339 + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 340 + interrupt-names = "macirq", "eth_wake_irq"; 341 + rockchip,grf = <&grf>; 342 + clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, 343 + <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>, 344 + <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, 345 + <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>; 346 + clock-names = "stmmaceth", "mac_clk_rx", 347 + "mac_clk_tx", "clk_mac_ref", 348 + "aclk_mac", "pclk_mac", 349 + "clk_mac_speed", "ptp_ref"; 350 + resets = <&cru SRST_GMAC_A>; 351 + reset-names = "stmmaceth"; 352 + 353 + snps,mixed-burst; 354 + snps,tso; 355 + 356 + snps,axi-config = <&stmmac_axi_setup>; 357 + snps,mtl-rx-config = <&mtl_rx_setup>; 358 + snps,mtl-tx-config = <&mtl_tx_setup>; 359 + status = "disabled"; 360 + 361 + mdio: mdio { 362 + compatible = "snps,dwmac-mdio"; 363 + #address-cells = <0x1>; 364 + #size-cells = <0x0>; 365 + }; 366 + 367 + stmmac_axi_setup: stmmac-axi-config { 368 + snps,wr_osr_lmt = <4>; 369 + snps,rd_osr_lmt = <8>; 370 + snps,blen = <0 0 0 0 16 8 4>; 371 + }; 372 + 373 + mtl_rx_setup: rx-queues-config { 374 + snps,rx-queues-to-use = <1>; 375 + queue0 {}; 376 + }; 377 + 378 + mtl_tx_setup: tx-queues-config { 379 + snps,tx-queues-to-use = <1>; 380 + queue0 {}; 381 + }; 382 + }; 383 + 335 384 emmc: mmc@ffc50000 { 336 385 compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; 337 386 reg = <0xffc50000 0x4000>;