tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: qcom-qmp: move PCS V3 registers to separate headers
Move PCS V3 registers to the separate headers.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20220705094320.1313312-15-dmitry.baryshkov@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Dmitry Baryshkov
and committed by
Vinod Koul
56a1fa09
5ae11aa4
+91
-70
+17
drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v3.h
+17
drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v3.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
4
+
*/
5
+
6
+
#ifndef QCOM_PHY_QMP_PCS_MISC_V3_H_
7
+
#define QCOM_PHY_QMP_PCS_MISC_V3_H_
8
+
9
+
/* Only for QMP V3 PHY - PCS_MISC registers */
10
+
#define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c
11
+
#define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c
12
+
#define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44
13
+
#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54
14
+
#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c
15
+
#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60
16
+
17
+
#endif
+71
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h
+71
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v3.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/*
3
+
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
4
+
*/
5
+
6
+
#ifndef QCOM_PHY_QMP_PCS_V3_H_
7
+
#define QCOM_PHY_QMP_PCS_V3_H_
8
+
9
+
/* Only for QMP V3 PHY - PCS registers */
10
+
#define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004
11
+
#define QPHY_V3_PCS_TXMGN_V0 0x00c
12
+
#define QPHY_V3_PCS_TXMGN_V1 0x010
13
+
#define QPHY_V3_PCS_TXMGN_V2 0x014
14
+
#define QPHY_V3_PCS_TXMGN_V3 0x018
15
+
#define QPHY_V3_PCS_TXMGN_V4 0x01c
16
+
#define QPHY_V3_PCS_TXMGN_LS 0x020
17
+
#define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c
18
+
#define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034
19
+
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024
20
+
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028
21
+
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c
22
+
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030
23
+
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034
24
+
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038
25
+
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c
26
+
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040
27
+
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044
28
+
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048
29
+
#define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c
30
+
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050
31
+
#define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054
32
+
#define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058
33
+
#define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c
34
+
#define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060
35
+
#define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064
36
+
#define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c
37
+
#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070
38
+
#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074
39
+
#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078
40
+
#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c
41
+
#define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080
42
+
#define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084
43
+
#define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088
44
+
#define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c
45
+
#define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0
46
+
#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4
47
+
#define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8
48
+
#define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0
49
+
#define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8
50
+
#define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc
51
+
#define QPHY_V3_PCS_FLL_CNTRL1 0x0c4
52
+
#define QPHY_V3_PCS_FLL_CNTRL2 0x0c8
53
+
#define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc
54
+
#define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0
55
+
#define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4
56
+
#define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134
57
+
#define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138
58
+
#define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c
59
+
#define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140
60
+
#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8
61
+
#define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac
62
+
#define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0
63
+
#define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc
64
+
#define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4
65
+
#define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8
66
+
#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
67
+
#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
68
+
#define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c
69
+
#define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210
70
+
71
+
#endif
+3
-70
drivers/phy/qualcomm/phy-qcom-qmp.h
+3
-70
drivers/phy/qualcomm/phy-qcom-qmp.h
···
22
22
23
23
#include "phy-qcom-qmp-pcs-v2.h"
24
24
25
+
#include "phy-qcom-qmp-pcs-v3.h"
26
+
#include "phy-qcom-qmp-pcs-misc-v3.h"
27
+
25
28
/* Only for QMP V3 & V4 PHY - DP COM registers */
26
29
#define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
27
30
#define QPHY_V3_DP_COM_SW_RESET 0x04
···
48
45
# define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020
49
46
# define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f
50
47
# define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020
51
-
52
-
/* Only for QMP V3 PHY - PCS registers */
53
-
#define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004
54
-
#define QPHY_V3_PCS_TXMGN_V0 0x00c
55
-
#define QPHY_V3_PCS_TXMGN_V1 0x010
56
-
#define QPHY_V3_PCS_TXMGN_V2 0x014
57
-
#define QPHY_V3_PCS_TXMGN_V3 0x018
58
-
#define QPHY_V3_PCS_TXMGN_V4 0x01c
59
-
#define QPHY_V3_PCS_TXMGN_LS 0x020
60
-
#define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c
61
-
#define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034
62
-
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024
63
-
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028
64
-
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c
65
-
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030
66
-
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034
67
-
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038
68
-
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c
69
-
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040
70
-
#define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044
71
-
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048
72
-
#define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c
73
-
#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050
74
-
#define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054
75
-
#define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058
76
-
#define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c
77
-
#define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060
78
-
#define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064
79
-
#define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c
80
-
#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070
81
-
#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074
82
-
#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078
83
-
#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c
84
-
#define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080
85
-
#define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084
86
-
#define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088
87
-
#define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c
88
-
#define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0
89
-
#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4
90
-
#define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8
91
-
#define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0
92
-
#define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8
93
-
#define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc
94
-
#define QPHY_V3_PCS_FLL_CNTRL1 0x0c4
95
-
#define QPHY_V3_PCS_FLL_CNTRL2 0x0c8
96
-
#define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc
97
-
#define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0
98
-
#define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4
99
-
#define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134
100
-
#define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138
101
-
#define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c
102
-
#define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140
103
-
#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8
104
-
#define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac
105
-
#define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0
106
-
#define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc
107
-
#define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4
108
-
#define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8
109
-
#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc
110
-
#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0
111
-
#define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c
112
-
#define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210
113
-
114
-
/* Only for QMP V3 PHY - PCS_MISC registers */
115
-
#define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c
116
-
#define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c
117
-
#define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44
118
-
#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54
119
-
#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c
120
-
#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60
121
48
122
49
/* QMP PHY - DP PHY registers */
123
50
#define QSERDES_DP_PHY_REVISION_ID0 0x000