tjh.dev / kernel
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staging: rtl8723bs: Remove unused macros in Hal8723BReg.h

Remove unused macros.

Signed-off-by: Philipp Hortmann <philipp.g.hortmann@gmail.com>
Link: https://lore.kernel.org/r/e01262b91c33d7f0b8370f74d95d688d7c813655.1720245061.git.philipp.g.hortmann@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Philipp Hortmann and committed by
Greg Kroah-Hartman 551977b7 319ce38b

-373
-373
drivers/staging/rtl8723bs/hal/Hal8723BReg.h
··· 21 21 22 22 /* */ 23 23 /* */ 24 - /* */ 25 - 26 - /* */ 27 - /* */ 28 - /* 0x0000h ~ 0x00FFh System Configuration */ 29 - /* */ 30 - /* */ 31 - #define REG_SYS_ISO_CTRL_8723B 0x0000 /* 2 Byte */ 32 - #define REG_SYS_FUNC_EN_8723B 0x0002 /* 2 Byte */ 33 - #define REG_APS_FSMCO_8723B 0x0004 /* 4 Byte */ 34 - #define REG_SYS_CLKR_8723B 0x0008 /* 2 Byte */ 35 - #define REG_9346CR_8723B 0x000A /* 2 Byte */ 36 - #define REG_EE_VPD_8723B 0x000C /* 2 Byte */ 37 - #define REG_AFE_MISC_8723B 0x0010 /* 1 Byte */ 38 - #define REG_SPS0_CTRL_8723B 0x0011 /* 7 Byte */ 39 - #define REG_SPS_OCP_CFG_8723B 0x0018 /* 4 Byte */ 40 - #define REG_RSV_CTRL_8723B 0x001C /* 3 Byte */ 41 - #define REG_RF_CTRL_8723B 0x001F /* 1 Byte */ 42 - #define REG_LPLDO_CTRL_8723B 0x0023 /* 1 Byte */ 43 - #define REG_AFE_XTAL_CTRL_8723B 0x0024 /* 4 Byte */ 44 - #define REG_AFE_PLL_CTRL_8723B 0x0028 /* 4 Byte */ 45 - #define REG_MAC_PLL_CTRL_EXT_8723B 0x002c /* 4 Byte */ 46 - #define REG_EFUSE_CTRL_8723B 0x0030 47 - #define REG_EFUSE_TEST_8723B 0x0034 48 - #define REG_PWR_DATA_8723B 0x0038 49 - #define REG_CAL_TIMER_8723B 0x003C 50 - #define REG_ACLK_MON_8723B 0x003E 51 - #define REG_GPIO_MUXCFG_8723B 0x0040 52 - #define REG_GPIO_IO_SEL_8723B 0x0042 53 - #define REG_MAC_PINMUX_CFG_8723B 0x0043 54 - #define REG_GPIO_PIN_CTRL_8723B 0x0044 55 - #define REG_GPIO_INTM_8723B 0x0048 56 - #define REG_LEDCFG0_8723B 0x004C 57 - #define REG_LEDCFG1_8723B 0x004D 58 - #define REG_LEDCFG2_8723B 0x004E 59 - #define REG_LEDCFG3_8723B 0x004F 60 - #define REG_FSIMR_8723B 0x0050 61 - #define REG_FSISR_8723B 0x0054 62 - #define REG_HSIMR_8723B 0x0058 63 - #define REG_HSISR_8723B 0x005c 64 - #define REG_GPIO_EXT_CTRL 0x0060 65 - #define REG_MULTI_FUNC_CTRL_8723B 0x0068 66 - #define REG_GPIO_STATUS_8723B 0x006C 67 - #define REG_SDIO_CTRL_8723B 0x0070 68 - #define REG_OPT_CTRL_8723B 0x0074 69 - #define REG_AFE_XTAL_CTRL_EXT_8723B 0x0078 70 - #define REG_MCUFWDL_8723B 0x0080 71 - #define REG_BT_PATCH_STATUS_8723B 0x0088 72 - #define REG_HIMR0_8723B 0x00B0 73 - #define REG_HISR0_8723B 0x00B4 74 - #define REG_HIMR1_8723B 0x00B8 75 - #define REG_HISR1_8723B 0x00BC 76 - #define REG_PMC_DBG_CTRL2_8723B 0x00CC 77 - #define REG_EFUSE_BURN_GNT_8723B 0x00CF 78 - #define REG_HPON_FSM_8723B 0x00EC 79 - #define REG_SYS_CFG_8723B 0x00F0 80 - #define REG_SYS_CFG1_8723B 0x00FC 81 - #define REG_ROM_VERSION 0x00FD 82 - 83 - /* */ 84 - /* */ 85 24 /* 0x0100h ~ 0x01FFh MACTOP General Configuration */ 86 25 /* */ 87 26 /* */ 88 - #define REG_CR_8723B 0x0100 89 - #define REG_PBP_8723B 0x0104 90 - #define REG_PKT_BUFF_ACCESS_CTRL_8723B 0x0106 91 - #define REG_TRXDMA_CTRL_8723B 0x010C 92 - #define REG_TRXFF_BNDY_8723B 0x0114 93 - #define REG_TRXFF_STATUS_8723B 0x0118 94 - #define REG_RXFF_PTR_8723B 0x011C 95 - #define REG_CPWM_8723B 0x012F 96 - #define REG_FWIMR_8723B 0x0130 97 - #define REG_FWISR_8723B 0x0134 98 - #define REG_FTIMR_8723B 0x0138 99 - #define REG_PKTBUF_DBG_CTRL_8723B 0x0140 100 - #define REG_RXPKTBUF_CTRL_8723B 0x0142 101 - #define REG_PKTBUF_DBG_DATA_L_8723B 0x0144 102 - #define REG_PKTBUF_DBG_DATA_H_8723B 0x0148 103 - 104 - #define REG_TC0_CTRL_8723B 0x0150 105 - #define REG_TC1_CTRL_8723B 0x0154 106 - #define REG_TC2_CTRL_8723B 0x0158 107 - #define REG_TC3_CTRL_8723B 0x015C 108 - #define REG_TC4_CTRL_8723B 0x0160 109 - #define REG_TCUNIT_BASE_8723B 0x0164 110 - #define REG_RSVD3_8723B 0x0168 111 - #define REG_C2HEVT_MSG_NORMAL_8723B 0x01A0 112 27 #define REG_C2HEVT_CMD_SEQ_88XX 0x01A1 113 - #define REG_C2HEVT_CMD_CONTENT_88XX 0x01A2 114 28 #define REG_C2HEVT_CMD_LEN_88XX 0x01AE 115 - #define REG_C2HEVT_CLEAR_8723B 0x01AF 116 - #define REG_MCUTST_1_8723B 0x01C0 117 - #define REG_MCUTST_WOWLAN_8723B 0x01C7 118 - #define REG_FMETHR_8723B 0x01C8 119 - #define REG_HMETFR_8723B 0x01CC 120 - #define REG_HMEBOX_0_8723B 0x01D0 121 - #define REG_HMEBOX_1_8723B 0x01D4 122 - #define REG_HMEBOX_2_8723B 0x01D8 123 - #define REG_HMEBOX_3_8723B 0x01DC 124 - #define REG_LLT_INIT_8723B 0x01E0 125 - #define REG_HMEBOX_EXT0_8723B 0x01F0 126 - #define REG_HMEBOX_EXT1_8723B 0x01F4 127 - #define REG_HMEBOX_EXT2_8723B 0x01F8 128 - #define REG_HMEBOX_EXT3_8723B 0x01FC 129 29 130 30 /* */ 131 31 /* */ 132 32 /* 0x0200h ~ 0x027Fh TXDMA Configuration */ 133 33 /* */ 134 34 /* */ 135 - #define REG_RQPN_8723B 0x0200 136 - #define REG_FIFOPAGE_8723B 0x0204 137 - #define REG_DWBCN0_CTRL_8723B REG_TDECTRL 138 - #define REG_TXDMA_OFFSET_CHK_8723B 0x020C 139 - #define REG_TXDMA_STATUS_8723B 0x0210 140 - #define REG_RQPN_NPQ_8723B 0x0214 141 35 #define REG_DWBCN1_CTRL_8723B 0x0228 142 - 143 - /* */ 144 - /* */ 145 - /* 0x0280h ~ 0x02FFh RXDMA Configuration */ 146 - /* */ 147 - /* */ 148 - #define REG_RXDMA_AGG_PG_TH_8723B 0x0280 149 - #define REG_FW_UPD_RDPTR_8723B 0x0284 /* FW shall update this register before FW write RXPKT_RELEASE_POLL to 1 */ 150 - #define REG_RXDMA_CONTROL_8723B 0x0286 /* Control the RX DMA. */ 151 - #define REG_RXPKT_NUM_8723B 0x0287 /* The number of packets in RXPKTBUF. */ 152 - #define REG_RXDMA_STATUS_8723B 0x0288 153 - #define REG_RXDMA_PRO_8723B 0x0290 154 - #define REG_EARLY_MODE_CONTROL_8723B 0x02BC 155 - #define REG_RSVD5_8723B 0x02F0 156 - #define REG_RSVD6_8723B 0x02F4 157 - 158 - /* */ 159 - /* */ 160 - /* 0x0300h ~ 0x03FFh PCIe */ 161 - /* */ 162 - /* */ 163 - #define REG_PCIE_CTRL_REG_8723B 0x0300 164 - #define REG_INT_MIG_8723B 0x0304 /* Interrupt Migration */ 165 - #define REG_BCNQ_DESA_8723B 0x0308 /* TX Beacon Descriptor Address */ 166 - #define REG_HQ_DESA_8723B 0x0310 /* TX High Queue Descriptor Address */ 167 - #define REG_MGQ_DESA_8723B 0x0318 /* TX Manage Queue Descriptor Address */ 168 - #define REG_VOQ_DESA_8723B 0x0320 /* TX VO Queue Descriptor Address */ 169 - #define REG_VIQ_DESA_8723B 0x0328 /* TX VI Queue Descriptor Address */ 170 - #define REG_BEQ_DESA_8723B 0x0330 /* TX BE Queue Descriptor Address */ 171 - #define REG_BKQ_DESA_8723B 0x0338 /* TX BK Queue Descriptor Address */ 172 - #define REG_RX_DESA_8723B 0x0340 /* RX Queue Descriptor Address */ 173 - #define REG_DBI_WDATA_8723B 0x0348 /* DBI Write Data */ 174 - #define REG_DBI_RDATA_8723B 0x034C /* DBI Read Data */ 175 - #define REG_DBI_ADDR_8723B 0x0350 /* DBI Address */ 176 - #define REG_DBI_FLAG_8723B 0x0352 /* DBI Read/Write Flag */ 177 - #define REG_MDIO_WDATA_8723B 0x0354 /* MDIO for Write PCIE PHY */ 178 - #define REG_MDIO_RDATA_8723B 0x0356 /* MDIO for Reads PCIE PHY */ 179 - #define REG_MDIO_CTL_8723B 0x0358 /* MDIO for Control */ 180 - #define REG_DBG_SEL_8723B 0x0360 /* Debug Selection Register */ 181 - #define REG_PCIE_HRPWM_8723B 0x0361 /* PCIe RPWM */ 182 - #define REG_PCIE_HCPWM_8723B 0x0363 /* PCIe CPWM */ 183 - #define REG_PCIE_MULTIFET_CTRL_8723B 0x036A /* PCIE Multi-Fethc Control */ 184 36 185 37 /* spec version 11 */ 186 38 /* */ ··· 40 188 /* 0x0400h ~ 0x047Fh Protocol Configuration */ 41 189 /* */ 42 190 /* */ 43 - #define REG_VOQ_INFORMATION_8723B 0x0400 44 - #define REG_VIQ_INFORMATION_8723B 0x0404 45 - #define REG_BEQ_INFORMATION_8723B 0x0408 46 - #define REG_BKQ_INFORMATION_8723B 0x040C 47 - #define REG_MGQ_INFORMATION_8723B 0x0410 48 - #define REG_HGQ_INFORMATION_8723B 0x0414 49 - #define REG_BCNQ_INFORMATION_8723B 0x0418 50 - #define REG_TXPKT_EMPTY_8723B 0x041A 51 - 52 191 #define REG_FWHW_TXQ_CTRL_8723B 0x0420 53 - #define REG_HWSEQ_CTRL_8723B 0x0423 54 - #define REG_TXPKTBUF_BCNQ_BDNY_8723B 0x0424 55 - #define REG_TXPKTBUF_MGQ_BDNY_8723B 0x0425 56 - #define REG_LIFECTRL_CTRL_8723B 0x0426 57 - #define REG_MULTI_BCNQ_OFFSET_8723B 0x0427 58 - #define REG_SPEC_SIFS_8723B 0x0428 59 - #define REG_RL_8723B 0x042A 60 - #define REG_TXBF_CTRL_8723B 0x042C 61 - #define REG_DARFRC_8723B 0x0430 62 - #define REG_RARFRC_8723B 0x0438 63 - #define REG_RRSR_8723B 0x0440 64 192 #define REG_ARFR0_8723B 0x0444 65 193 #define REG_ARFR1_8723B 0x044C 66 194 #define REG_CCK_CHECK_8723B 0x0454 67 195 #define REG_AMPDU_MAX_TIME_8723B 0x0456 68 - #define REG_TXPKTBUF_BCNQ_BDNY1_8723B 0x0457 69 196 70 197 #define REG_AMPDU_MAX_LENGTH_8723B 0x0458 71 - #define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B 0x045D 72 - #define REG_NDPA_OPT_CTRL_8723B 0x045F 73 - #define REG_FAST_EDCA_CTRL_8723B 0x0460 74 - #define REG_RD_RESP_PKT_TH_8723B 0x0463 75 198 #define REG_DATA_SC_8723B 0x0483 76 - #define REG_TXRPT_START_OFFSET 0x04AC 77 - #define REG_POWER_STAGE1_8723B 0x04B4 78 - #define REG_POWER_STAGE2_8723B 0x04B8 79 - #define REG_AMPDU_BURST_MODE_8723B 0x04BC 80 - #define REG_PKT_VO_VI_LIFE_TIME_8723B 0x04C0 81 - #define REG_PKT_BE_BK_LIFE_TIME_8723B 0x04C2 82 - #define REG_STBC_SETTING_8723B 0x04C4 83 - #define REG_HT_SINGLE_AMPDU_8723B 0x04C7 84 - #define REG_PROT_MODE_CTRL_8723B 0x04C8 85 199 #define REG_MAX_AGGR_NUM_8723B 0x04CA 86 - #define REG_RTS_MAX_AGGR_NUM_8723B 0x04CB 87 - #define REG_BAR_MODE_CTRL_8723B 0x04CC 88 - #define REG_RA_TRY_RATE_AGG_LMT_8723B 0x04CF 89 - #define REG_MACID_PKT_DROP0_8723B 0x04D0 90 - #define REG_MACID_PKT_SLEEP_8723B 0x04D4 91 200 92 201 /* */ 93 202 /* */ 94 203 /* 0x0500h ~ 0x05FFh EDCA Configuration */ 95 204 /* */ 96 205 /* */ 97 - #define REG_EDCA_VO_PARAM_8723B 0x0500 98 - #define REG_EDCA_VI_PARAM_8723B 0x0504 99 - #define REG_EDCA_BE_PARAM_8723B 0x0508 100 - #define REG_EDCA_BK_PARAM_8723B 0x050C 101 - #define REG_BCNTCFG_8723B 0x0510 102 206 #define REG_PIFS_8723B 0x0512 103 - #define REG_RDG_PIFS_8723B 0x0513 104 - #define REG_SIFS_CTX_8723B 0x0514 105 - #define REG_SIFS_TRX_8723B 0x0516 106 - #define REG_AGGR_BREAK_TIME_8723B 0x051A 107 - #define REG_SLOT_8723B 0x051B 108 - #define REG_TX_PTCL_CTRL_8723B 0x0520 109 - #define REG_TXPAUSE_8723B 0x0522 110 - #define REG_DIS_TXREQ_CLR_8723B 0x0523 111 - #define REG_RD_CTRL_8723B 0x0524 112 - /* */ 113 - /* Format for offset 540h-542h: */ 114 - /* [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. */ 115 - /* [7:4]: Reserved. */ 116 - /* [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. */ 117 - /* [23:20]: Reserved */ 118 - /* Description: */ 119 - /* | */ 120 - /* |<--Setup--|--Hold------------>| */ 121 - /* --------------|---------------------- */ 122 - /* | */ 123 - /* TBTT */ 124 - /* Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. */ 125 - /* Described by Designer Tim and Bruce, 2011-01-14. */ 126 - /* */ 127 - #define REG_TBTT_PROHIBIT_8723B 0x0540 128 - #define REG_RD_NAV_NXT_8723B 0x0544 129 - #define REG_NAV_PROT_LEN_8723B 0x0546 130 - #define REG_BCN_CTRL_8723B 0x0550 131 - #define REG_BCN_CTRL_1_8723B 0x0551 132 - #define REG_MBID_NUM_8723B 0x0552 133 - #define REG_DUAL_TSF_RST_8723B 0x0553 134 - #define REG_BCN_INTERVAL_8723B 0x0554 135 - #define REG_DRVERLYINT_8723B 0x0558 136 - #define REG_BCNDMATIM_8723B 0x0559 137 - #define REG_ATIMWND_8723B 0x055A 138 - #define REG_USTIME_TSF_8723B 0x055C 139 - #define REG_BCN_MAX_ERR_8723B 0x055D 140 - #define REG_RXTSF_OFFSET_CCK_8723B 0x055E 141 - #define REG_RXTSF_OFFSET_OFDM_8723B 0x055F 142 - #define REG_TSFTR_8723B 0x0560 143 - #define REG_CTWND_8723B 0x0572 144 - #define REG_SECONDARY_CCA_CTRL_8723B 0x0577 145 - #define REG_PSTIMER_8723B 0x0580 146 - #define REG_TIMER0_8723B 0x0584 147 - #define REG_TIMER1_8723B 0x0588 148 - #define REG_ACMHWCTRL_8723B 0x05C0 149 - #define REG_SCH_TXCMD_8723B 0x05F8 150 207 151 208 /* 0x0600h ~ 0x07FFh WMAC Configuration */ 152 - #define REG_MAC_CR_8723B 0x0600 153 - #define REG_TCR_8723B 0x0604 154 - #define REG_RCR_8723B 0x0608 155 209 #define REG_RX_PKT_LIMIT_8723B 0x060C 156 - #define REG_RX_DLK_TIME_8723B 0x060D 157 - #define REG_RX_DRVINFO_SZ_8723B 0x060F 158 210 159 - #define REG_MACID_8723B 0x0610 160 - #define REG_BSSID_8723B 0x0618 161 - #define REG_MAR_8723B 0x0620 162 - #define REG_MBIDCAMCFG_8723B 0x0628 163 - 164 - #define REG_USTIME_EDCA_8723B 0x0638 165 - #define REG_MAC_SPEC_SIFS_8723B 0x063A 166 - #define REG_RESP_SIFP_CCK_8723B 0x063C 167 - #define REG_RESP_SIFS_OFDM_8723B 0x063E 168 - #define REG_ACKTO_8723B 0x0640 169 - #define REG_CTS2TO_8723B 0x0641 170 - #define REG_EIFS_8723B 0x0642 171 - 172 - #define REG_NAV_UPPER_8723B 0x0652 /* unit of 128 */ 173 211 #define REG_TRXPTCL_CTL_8723B 0x0668 174 - 175 - /* Security */ 176 - #define REG_CAMCMD_8723B 0x0670 177 - #define REG_CAMWRITE_8723B 0x0674 178 - #define REG_CAMREAD_8723B 0x0678 179 - #define REG_CAMDBG_8723B 0x067C 180 - #define REG_SECCFG_8723B 0x0680 181 - 182 - /* Power */ 183 - #define REG_WOW_CTRL_8723B 0x0690 184 - #define REG_PS_RX_INFO_8723B 0x0692 185 - #define REG_UAPSD_TID_8723B 0x0693 186 - #define REG_WKFMCAM_CMD_8723B 0x0698 187 - #define REG_WKFMCAM_NUM_8723B 0x0698 188 - #define REG_WKFMCAM_RWD_8723B 0x069C 189 - #define REG_RXFLTMAP0_8723B 0x06A0 190 - #define REG_RXFLTMAP1_8723B 0x06A2 191 - #define REG_RXFLTMAP2_8723B 0x06A4 192 - #define REG_BCN_PSR_RPT_8723B 0x06A8 193 - #define REG_BT_COEX_TABLE_8723B 0x06C0 194 - #define REG_BFMER0_INFO_8723B 0x06E4 195 - #define REG_BFMER1_INFO_8723B 0x06EC 196 - #define REG_CSI_RPT_PARAM_BW20_8723B 0x06F4 197 - #define REG_CSI_RPT_PARAM_BW40_8723B 0x06F8 198 - #define REG_CSI_RPT_PARAM_BW80_8723B 0x06FC 199 - 200 - /* Hardware Port 2 */ 201 - #define REG_MACID1_8723B 0x0700 202 - #define REG_BSSID1_8723B 0x0708 203 - #define REG_BFMEE_SEL_8723B 0x0714 204 - #define REG_SND_PTCL_CTRL_8723B 0x0718 205 - 206 - /* Redifine 8192C register definition for compatibility */ 207 - 208 - /* TODO: use these definition when using REG_xxx naming rule. */ 209 - /* NOTE: DO NOT Remove these definition. Use later. */ 210 - #define EFUSE_CTRL_8723B REG_EFUSE_CTRL_8723B /* E-Fuse Control. */ 211 - #define EFUSE_TEST_8723B REG_EFUSE_TEST_8723B /* E-Fuse Test. */ 212 - #define MSR_8723B (REG_CR_8723B + 2) /* Media Status register */ 213 - #define ISR_8723B REG_HISR0_8723B 214 - #define TSFR_8723B REG_TSFTR_8723B /* Timing Sync Function Timer Register. */ 215 - 216 - #define PBP_8723B REG_PBP_8723B 217 - 218 - /* Redifine MACID register, to compatible prior ICs. */ 219 - #define IDR0_8723B REG_MACID_8723B /* MAC ID Register, Offset 0x0050-0x0053 */ 220 - #define IDR4_8723B (REG_MACID_8723B + 4) /* MAC ID Register, Offset 0x0054-0x0055 */ 221 - 222 - /* 9. Security Control Registers (Offset:) */ 223 - #define RWCAM_8723B REG_CAMCMD_8723B /* IN 8190 Data Sheet is called CAMcmd */ 224 - #define WCAMI_8723B REG_CAMWRITE_8723B /* Software write CAM input content */ 225 - #define RCAMO_8723B REG_CAMREAD_8723B /* Software read/write CAM config */ 226 - #define CAMDBG_8723B REG_CAMDBG_8723B 227 - #define SECR_8723B REG_SECCFG_8723B /* Security Configuration Register */ 228 - 229 - /* 8195 IMR/ISR bits (offset 0xB0, 8bits) */ 230 - #define IMR_DISABLED_8723B 0 231 - /* IMR DW0(0x00B0-00B3) Bit 0-31 */ 232 - #define IMR_TIMER2_8723B BIT31 /* Timeout interrupt 2 */ 233 - #define IMR_TIMER1_8723B BIT30 /* Timeout interrupt 1 */ 234 - #define IMR_PSTIMEOUT_8723B BIT29 /* Power Save Time Out Interrupt */ 235 - #define IMR_GTINT4_8723B BIT28 /* When GTIMER4 expires, this bit is set to 1 */ 236 - #define IMR_GTINT3_8723B BIT27 /* When GTIMER3 expires, this bit is set to 1 */ 237 - #define IMR_TXBCN0ERR_8723B BIT26 /* Transmit Beacon0 Error */ 238 - #define IMR_TXBCN0OK_8723B BIT25 /* Transmit Beacon0 OK */ 239 - #define IMR_TSF_BIT32_TOGGLE_8723B BIT24 /* TSF Timer BIT32 toggle indication interrupt */ 240 - #define IMR_BCNDMAINT0_8723B BIT20 /* Beacon DMA Interrupt 0 */ 241 - #define IMR_BCNDERR0_8723B BIT16 /* Beacon Queue DMA OK0 */ 242 - #define IMR_HSISR_IND_ON_INT_8723B BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ 243 - #define IMR_BCNDMAINT_E_8723B BIT14 /* Beacon DMA Interrupt Extension for Win7 */ 244 - #define IMR_ATIMEND_8723B BIT12 /* CTWidnow End or ATIM Window End */ 245 - #define IMR_C2HCMD_8723B BIT10 /* CPU to Host Command INT Status, Write 1 clear */ 246 - #define IMR_CPWM2_8723B BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */ 247 - #define IMR_CPWM_8723B BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */ 248 - #define IMR_HIGHDOK_8723B BIT7 /* High Queue DMA OK */ 249 - #define IMR_MGNTDOK_8723B BIT6 /* Management Queue DMA OK */ 250 - #define IMR_BKDOK_8723B BIT5 /* AC_BK DMA OK */ 251 - #define IMR_BEDOK_8723B BIT4 /* AC_BE DMA OK */ 252 - #define IMR_VIDOK_8723B BIT3 /* AC_VI DMA OK */ 253 - #define IMR_VODOK_8723B BIT2 /* AC_VO DMA OK */ 254 - #define IMR_RDU_8723B BIT1 /* Rx Descriptor Unavailable */ 255 - #define IMR_ROK_8723B BIT0 /* Receive DMA OK */ 256 - 257 - /* IMR DW1(0x00B4-00B7) Bit 0-31 */ 258 - #define IMR_BCNDMAINT7_8723B BIT27 /* Beacon DMA Interrupt 7 */ 259 - #define IMR_BCNDMAINT6_8723B BIT26 /* Beacon DMA Interrupt 6 */ 260 - #define IMR_BCNDMAINT5_8723B BIT25 /* Beacon DMA Interrupt 5 */ 261 - #define IMR_BCNDMAINT4_8723B BIT24 /* Beacon DMA Interrupt 4 */ 262 - #define IMR_BCNDMAINT3_8723B BIT23 /* Beacon DMA Interrupt 3 */ 263 - #define IMR_BCNDMAINT2_8723B BIT22 /* Beacon DMA Interrupt 2 */ 264 - #define IMR_BCNDMAINT1_8723B BIT21 /* Beacon DMA Interrupt 1 */ 265 - #define IMR_BCNDOK7_8723B BIT20 /* Beacon Queue DMA OK Interrupt 7 */ 266 - #define IMR_BCNDOK6_8723B BIT19 /* Beacon Queue DMA OK Interrupt 6 */ 267 - #define IMR_BCNDOK5_8723B BIT18 /* Beacon Queue DMA OK Interrupt 5 */ 268 - #define IMR_BCNDOK4_8723B BIT17 /* Beacon Queue DMA OK Interrupt 4 */ 269 - #define IMR_BCNDOK3_8723B BIT16 /* Beacon Queue DMA OK Interrupt 3 */ 270 - #define IMR_BCNDOK2_8723B BIT15 /* Beacon Queue DMA OK Interrupt 2 */ 271 - #define IMR_BCNDOK1_8723B BIT14 /* Beacon Queue DMA OK Interrupt 1 */ 272 - #define IMR_ATIMEND_E_8723B BIT13 /* ATIM Window End Extension for Win7 */ 273 - #define IMR_TXERR_8723B BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */ 274 - #define IMR_RXERR_8723B BIT10 /* Rx Error Flag INT Status, Write 1 clear */ 275 - #define IMR_TXFOVW_8723B BIT9 /* Transmit FIFO Overflow */ 276 - #define IMR_RXFOVW_8723B BIT8 /* Receive FIFO Overflow */ 277 - 278 - /* 2 ACMHWCTRL 0x05C0 */ 279 - #define ACMHW_HWEN_8723B BIT(0) 280 - #define ACMHW_VOQEN_8723B BIT(1) 281 - #define ACMHW_VIQEN_8723B BIT(2) 282 - #define ACMHW_BEQEN_8723B BIT(3) 283 - #define ACMHW_VOQSTATUS_8723B BIT(5) 284 - #define ACMHW_VIQSTATUS_8723B BIT(6) 285 - #define ACMHW_BEQSTATUS_8723B BIT(7) 286 - 287 - /* 8195 (RCR) Receive Configuration Register (Offset 0x608, 32 bits) */ 288 - #define RCR_TCPOFLD_EN BIT25 /* Enable TCP checksum offload */ 289 212 290 213 #endif /* #ifndef __INC_HAL8723BREG_H */