staging: rtl8723bs: Remove unused macros in Hal8192CPhyReg.h

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Remove unused macros.

Signed-off-by: Philipp Hortmann <philipp.g.hortmann@gmail.com>
Link: https://lore.kernel.org/r/59ee254104cee474b4647d605d4b3380829202a5.1720245061.git.philipp.g.hortmann@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Philipp Hortmann and committed by

Greg Kroah-Hartman 2 years ago 319ce38b a6fdb662

-881

1 changed file

expand all

drivers

staging

rtl8723bs

include

Hal8192CPhyReg.h

-881

drivers/staging/rtl8723bs/include/Hal8192CPhyReg.h

··· 46 46 /* 5. Other definition for BB/RF R/W */ 47 47 /* */ 48 48 49 - 50 - /* */ 51 - /* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */ 52 - /* 1. Page1(0x100) */ 53 - /* */ 54 - #define rPMAC_Reset 0x100 55 - #define rPMAC_TxStart 0x104 56 - #define rPMAC_TxLegacySIG 0x108 57 - #define rPMAC_TxHTSIG1 0x10c 58 - #define rPMAC_TxHTSIG2 0x110 59 - #define rPMAC_PHYDebug 0x114 60 - #define rPMAC_TxPacketNum 0x118 61 - #define rPMAC_TxIdle 0x11c 62 - #define rPMAC_TxMACHeader0 0x120 63 - #define rPMAC_TxMACHeader1 0x124 64 - #define rPMAC_TxMACHeader2 0x128 65 - #define rPMAC_TxMACHeader3 0x12c 66 - #define rPMAC_TxMACHeader4 0x130 67 - #define rPMAC_TxMACHeader5 0x134 68 - #define rPMAC_TxDataType 0x138 69 - #define rPMAC_TxRandomSeed 0x13c 70 - #define rPMAC_CCKPLCPPreamble 0x140 71 - #define rPMAC_CCKPLCPHeader 0x144 72 - #define rPMAC_CCKCRC16 0x148 73 - #define rPMAC_OFDMRxCRC32OK 0x170 74 - #define rPMAC_OFDMRxCRC32Er 0x174 75 - #define rPMAC_OFDMRxParityEr 0x178 76 - #define rPMAC_OFDMRxCRC8Er 0x17c 77 - #define rPMAC_CCKCRxRC16Er 0x180 78 - #define rPMAC_CCKCRxRC32Er 0x184 79 - #define rPMAC_CCKCRxRC32OK 0x188 80 - #define rPMAC_TxStatus 0x18c 81 - 82 - /* */ 83 - /* 2. Page2(0x200) */ 84 - /* */ 85 - /* The following two definition are only used for USB interface. */ 86 - #define RF_BB_CMD_ADDR 0x02c0 /* RF/BB read/write command address. */ 87 - #define RF_BB_CMD_DATA 0x02c4 /* RF/BB read/write command data. */ 88 - 89 49 /* */ 90 50 /* 3. Page8(0x800) */ 91 51 /* */ 92 52 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting?? */ 93 - 94 - #define rFPGA0_TxInfo 0x804 /* Status report?? */ 95 - #define rFPGA0_PSDFunction 0x808 96 - 97 - #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ 98 - 99 - #define rFPGA0_RFTiming1 0x810 /* Useless now */ 100 - #define rFPGA0_RFTiming2 0x814 101 53 102 54 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ 103 55 #define rFPGA0_XA_HSSIParameter2 0x824 ··· 65 113 #define rFPGA0_XA_LSSIParameter 0x840 66 114 #define rFPGA0_XB_LSSIParameter 0x844 67 115 68 - #define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */ 69 - #define rFPGA0_RFSleepUpParameter 0x854 70 - 71 - #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ 72 116 #define rFPGA0_XCD_SwitchControl 0x85c 73 117 74 118 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ ··· 75 127 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ 76 128 #define rFPGA0_XCD_RFInterfaceSW 0x874 77 129 78 - #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ 79 - #define rFPGA0_XCD_RFParameter 0x87c 80 - 81 - #define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */ 82 - #define rFPGA0_AnalogParameter2 0x884 83 - #define rFPGA0_AnalogParameter3 0x888 /* Useless now */ 84 - #define rFPGA0_AnalogParameter4 0x88c 85 - 86 130 #define rFPGA0_XA_LSSIReadBack 0x8a0 /* Transceiver LSSI Readback */ 87 131 #define rFPGA0_XB_LSSIReadBack 0x8a4 88 - #define rFPGA0_XC_LSSIReadBack 0x8a8 89 - #define rFPGA0_XD_LSSIReadBack 0x8ac 90 132 91 - #define rFPGA0_PSDReport 0x8b4 /* Useless now */ 92 133 #define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */ 93 134 #define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */ 94 - #define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now RF Interface Readback Value */ 95 - #define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ 96 135 97 136 /* */ 98 137 /* 4. Page9(0x900) */ 99 138 /* */ 100 139 #define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC RF BW Setting?? */ 101 140 102 - #define rFPGA1_TxBlock 0x904 /* Useless now */ 103 - #define rFPGA1_DebugSelect 0x908 /* Useless now */ 104 - #define rFPGA1_TxInfo 0x90c /* Useless now Status report?? */ 105 141 #define rS0S1_PathSwitch 0x948 106 142 107 143 /* */ ··· 95 163 #define rCCK0_System 0xa00 96 164 97 165 #define rCCK0_AFESetting 0xa04 /* Disable init gain now Select RX path by RSSI */ 98 - #define rCCK0_CCA 0xa08 /* Disable init gain now Init gain */ 99 166 100 - #define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */ 101 - #define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ 102 - 103 - #define rCCK0_RxHP 0xa14 104 - 105 - #define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */ 106 - #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ 107 - 108 - #define rCCK0_TxFilter1 0xa20 109 - #define rCCK0_TxFilter2 0xa24 110 - #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ 111 - #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */ 112 - #define rCCK0_TRSSIReport 0xa50 113 - #define rCCK0_RxReport 0xa54 /* 0xa57 */ 114 - #define rCCK0_FACounterLower 0xa5c /* 0xa5b */ 115 - #define rCCK0_FACounterUpper 0xa58 /* 0xa5c */ 116 167 /* */ 117 168 /* PageB(0xB00) */ 118 169 /* */ 119 - #define rPdp_AntA 0xb00 120 - #define rPdp_AntA_4 0xb04 121 - #define rConfig_Pmpd_AntA 0xb28 122 170 #define rConfig_AntA 0xb68 123 171 #define rConfig_AntB 0xb6c 124 - #define rPdp_AntB 0xb70 125 - #define rPdp_AntB_4 0xb74 126 - #define rConfig_Pmpd_AntB 0xb98 127 - #define rAPK 0xbd8 128 172 129 173 /* */ 130 174 /* 6. PageC(0xC00) */ 131 175 /* */ 132 - #define rOFDM0_LSTF 0xc00 133 - 134 176 #define rOFDM0_TRxPathEnable 0xc04 135 177 #define rOFDM0_TRMuxPar 0xc08 136 - #define rOFDM0_TRSWIsolation 0xc0c 137 178 138 - #define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ 139 179 #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imbalance matrix */ 140 - #define rOFDM0_XBRxAFE 0xc18 141 180 #define rOFDM0_XBRxIQImbalance 0xc1c 142 - #define rOFDM0_XCRxAFE 0xc20 143 - #define rOFDM0_XCRxIQImbalance 0xc24 144 - #define rOFDM0_XDRxAFE 0xc28 145 - #define rOFDM0_XDRxIQImbalance 0xc2c 146 - 147 - #define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD DM tune init gain */ 148 - #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ 149 - #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ 150 - #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ 151 181 152 182 #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 153 - #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ 154 - #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ 155 183 #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ 156 184 157 - #define rOFDM0_XAAGCCore1 0xc50 /* DIG */ 158 - #define rOFDM0_XAAGCCore2 0xc54 159 - #define rOFDM0_XBAGCCore1 0xc58 160 - #define rOFDM0_XBAGCCore2 0xc5c 161 - #define rOFDM0_XCAGCCore1 0xc60 162 - #define rOFDM0_XCAGCCore2 0xc64 163 - #define rOFDM0_XDAGCCore1 0xc68 164 - #define rOFDM0_XDAGCCore2 0xc6c 165 - 166 - #define rOFDM0_AGCParameter1 0xc70 167 - #define rOFDM0_AGCParameter2 0xc74 168 185 #define rOFDM0_AGCRSSITable 0xc78 169 - #define rOFDM0_HTSTFAGC 0xc7c 170 186 171 187 #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ 172 - #define rOFDM0_XATxAFE 0xc84 173 188 #define rOFDM0_XBTxIQImbalance 0xc88 174 - #define rOFDM0_XBTxAFE 0xc8c 175 - #define rOFDM0_XCTxIQImbalance 0xc90 176 189 #define rOFDM0_XCTxAFE 0xc94 177 - #define rOFDM0_XDTxIQImbalance 0xc98 178 190 #define rOFDM0_XDTxAFE 0xc9c 179 191 180 192 #define rOFDM0_RxIQExtAnta 0xca0 181 - #define rOFDM0_TxCoeff1 0xca4 182 - #define rOFDM0_TxCoeff2 0xca8 183 - #define rOFDM0_TxCoeff3 0xcac 184 - #define rOFDM0_TxCoeff4 0xcb0 185 - #define rOFDM0_TxCoeff5 0xcb4 186 - #define rOFDM0_TxCoeff6 0xcb8 187 - #define rOFDM0_RxHPParameter 0xce0 188 193 #define rOFDM0_TxPseudoNoiseWgt 0xce4 189 - #define rOFDM0_FrameSync 0xcf0 190 - #define rOFDM0_DFSReport 0xcf4 191 194 192 195 /* */ 193 196 /* 7. PageD(0xD00) */ 194 197 /* */ 195 198 #define rOFDM1_LSTF 0xd00 196 - #define rOFDM1_TRxPathEnable 0xd04 197 - 198 - #define rOFDM1_CFO 0xd08 /* No setting now */ 199 - #define rOFDM1_CSI1 0xd10 200 - #define rOFDM1_SBD 0xd14 201 - #define rOFDM1_CSI2 0xd18 202 - #define rOFDM1_CFOTracking 0xd2c 203 - #define rOFDM1_TRxMesaure1 0xd34 204 - #define rOFDM1_IntfDet 0xd3c 205 - #define rOFDM1_PseudoNoiseStateAB 0xd50 206 - #define rOFDM1_PseudoNoiseStateCD 0xd54 207 - #define rOFDM1_RxPseudoNoiseWgt 0xd58 208 - 209 - #define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ 210 - #define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ 211 - #define rOFDM_PHYCounter3 0xda8 /* MCS not support */ 212 - 213 - #define rOFDM_ShortCFOAB 0xdac /* No setting now */ 214 - #define rOFDM_ShortCFOCD 0xdb0 215 - #define rOFDM_LongCFOAB 0xdb4 216 - #define rOFDM_LongCFOCD 0xdb8 217 - #define rOFDM_TailCFOAB 0xdbc 218 - #define rOFDM_TailCFOCD 0xdc0 219 - #define rOFDM_PWMeasure1 0xdc4 220 - #define rOFDM_PWMeasure2 0xdc8 221 - #define rOFDM_BWReport 0xdcc 222 - #define rOFDM_AGCReport 0xdd0 223 - #define rOFDM_RxSNR 0xdd4 224 - #define rOFDM_RxEVMCSI 0xdd8 225 - #define rOFDM_SIGReport 0xddc 226 - 227 199 228 200 /* */ 229 201 /* 8. PageE(0xE00) */ ··· 152 316 #define rRx_IQK_Tone_B 0xe54 153 317 #define rTx_IQK_PI_B 0xe58 154 318 #define rRx_IQK_PI_B 0xe5c 155 - #define rIQK_AGC_Cont 0xe60 156 319 157 320 #define rBlue_Tooth 0xe6c 158 321 #define rRx_Wait_CCA 0xe70 ··· 166 331 #define rTx_Power_Before_IQK_A 0xe94 167 332 #define rTx_Power_After_IQK_A 0xe9c 168 333 169 - #define rRx_Power_Before_IQK_A 0xea0 170 334 #define rRx_Power_Before_IQK_A_2 0xea4 171 - #define rRx_Power_After_IQK_A 0xea8 172 335 #define rRx_Power_After_IQK_A_2 0xeac 173 - 174 - #define rTx_Power_Before_IQK_B 0xeb4 175 - #define rTx_Power_After_IQK_B 0xebc 176 - 177 - #define rRx_Power_Before_IQK_B 0xec0 178 - #define rRx_Power_Before_IQK_B_2 0xec4 179 - #define rRx_Power_After_IQK_B 0xec8 180 - #define rRx_Power_After_IQK_B_2 0xecc 181 336 182 337 #define rRx_OFDM 0xed0 183 338 #define rRx_Wait_RIFS 0xed4 ··· 177 352 #define rPMPD_ANAEN 0xeec 178 353 179 354 /* */ 180 - /* 7. RF Register 0x00-0x2E (RF 8256) */ 181 - /* RF-0222D 0x00-3F */ 182 - /* */ 183 - /* Zebra1 */ 184 - #define rZebra1_HSSIEnable 0x0 /* Useless now */ 185 - #define rZebra1_TRxEnable1 0x1 186 - #define rZebra1_TRxEnable2 0x2 187 - #define rZebra1_AGC 0x4 188 - #define rZebra1_ChargePump 0x5 189 - #define rZebra1_Channel 0x7 /* RF channel switch */ 190 - 191 - /* endif */ 192 - #define rZebra1_TxGain 0x8 /* Useless now */ 193 - #define rZebra1_TxLPF 0x9 194 - #define rZebra1_RxLPF 0xb 195 - #define rZebra1_RxHPFCorner 0xc 196 - 197 - /* Zebra4 */ 198 - #define rGlobalCtrl 0 /* Useless now */ 199 - #define rRTL8256_TxLPF 19 200 - #define rRTL8256_RxLPF 11 201 - 202 - /* RTL8258 */ 203 - #define rRTL8258_TxLPF 0x11 /* Useless now */ 204 - #define rRTL8258_RxLPF 0x13 205 - #define rRTL8258_RSSILPF 0xa 206 - 207 - /* */ 208 355 /* RL6052 Register definition */ 209 356 /* */ 210 357 #define RF_AC 0x00 /* */ 211 358 212 - #define RF_IQADJ_G1 0x01 /* */ 213 - #define RF_IQADJ_G2 0x02 /* */ 214 - #define RF_BS_PA_APSET_G1_G4 0x03 215 - #define RF_BS_PA_APSET_G5_G8 0x04 216 - #define RF_POW_TRSW 0x05 /* */ 217 - 218 - #define RF_GAIN_RX 0x06 /* */ 219 - #define RF_GAIN_TX 0x07 /* */ 220 - 221 359 #define RF_TXM_IDAC 0x08 /* */ 222 - #define RF_IPA_G 0x09 /* */ 223 - #define RF_TXBIAS_G 0x0A 224 - #define RF_TXPA_AG 0x0B 225 - #define RF_IPA_A 0x0C /* */ 226 - #define RF_TXBIAS_A 0x0D 227 - #define RF_BS_PA_APSET_G9_G11 0x0E 228 - #define RF_BS_IQGEN 0x0F /* */ 229 360 230 - #define RF_MODE1 0x10 /* */ 231 - #define RF_MODE2 0x11 /* */ 232 - 233 - #define RF_RX_AGC_HP 0x12 /* */ 234 - #define RF_TX_AGC 0x13 /* */ 235 - #define RF_BIAS 0x14 /* */ 236 - #define RF_IPA 0x15 /* */ 237 - #define RF_TXBIAS 0x16 /* */ 238 - #define RF_POW_ABILITY 0x17 /* */ 239 - #define RF_MODE_AG 0x18 /* */ 240 - #define rRfChannel 0x18 /* RF channel and BW switch */ 241 361 #define RF_CHNLBW 0x18 /* RF channel and BW switch */ 242 - #define RF_TOP 0x19 /* */ 243 - 244 - #define RF_RX_G1 0x1A /* */ 245 - #define RF_RX_G2 0x1B /* */ 246 - 247 - #define RF_RX_BB2 0x1C /* */ 248 - #define RF_RX_BB1 0x1D /* */ 249 - 250 - #define RF_RCK1 0x1E /* */ 251 - #define RF_RCK2 0x1F /* */ 252 - 253 - #define RF_TX_G1 0x20 /* */ 254 - #define RF_TX_G2 0x21 /* */ 255 - #define RF_TX_G3 0x22 /* */ 256 - 257 - #define RF_TX_BB1 0x23 /* */ 258 - 259 - #define RF_T_METER 0x24 /* */ 260 - 261 - #define RF_SYN_G1 0x25 /* RF TX Power control */ 262 - #define RF_SYN_G2 0x26 /* RF TX Power control */ 263 - #define RF_SYN_G3 0x27 /* RF TX Power control */ 264 - #define RF_SYN_G4 0x28 /* RF TX Power control */ 265 - #define RF_SYN_G5 0x29 /* RF TX Power control */ 266 - #define RF_SYN_G6 0x2A /* RF TX Power control */ 267 - #define RF_SYN_G7 0x2B /* RF TX Power control */ 268 - #define RF_SYN_G8 0x2C /* RF TX Power control */ 269 362 270 363 #define RF_RCK_OS 0x30 /* RF TX PA control */ 271 364 272 365 #define RF_TXPA_G1 0x31 /* RF TX PA control */ 273 366 #define RF_TXPA_G2 0x32 /* RF TX PA control */ 274 - #define RF_TXPA_G3 0x33 /* RF TX PA control */ 275 - #define RF_TX_BIAS_A 0x35 276 - #define RF_TX_BIAS_D 0x36 277 - #define RF_LOBF_9 0x38 278 - #define RF_RXRF_A3 0x3C /* */ 279 - #define RF_TRSW 0x3F 280 367 281 - #define RF_TXRF_A2 0x41 282 - #define RF_TXPA_G4 0x46 283 - #define RF_TXPA_A4 0x4B 284 - #define RF_0x52 0x52 285 368 #define RF_WE_LUT 0xEF 286 - #define RF_S0S1 0xB0 287 - 288 - /* */ 289 - /* Bit Mask */ 290 - /* */ 291 - /* 1. Page1(0x100) */ 292 - #define bBBResetB 0x100 /* Useless now? */ 293 - #define bGlobalResetB 0x200 294 - #define bOFDMTxStart 0x4 295 - #define bCCKTxStart 0x8 296 - #define bCRC32Debug 0x100 297 - #define bPMACLoopback 0x10 298 - #define bTxLSIG 0xffffff 299 - #define bOFDMTxRate 0xf 300 - #define bOFDMTxReserved 0x10 301 - #define bOFDMTxLength 0x1ffe0 302 - #define bOFDMTxParity 0x20000 303 - #define bTxHTSIG1 0xffffff 304 - #define bTxHTMCSRate 0x7f 305 - #define bTxHTBW 0x80 306 - #define bTxHTLength 0xffff00 307 - #define bTxHTSIG2 0xffffff 308 - #define bTxHTSmoothing 0x1 309 - #define bTxHTSounding 0x2 310 - #define bTxHTReserved 0x4 311 - #define bTxHTAggreation 0x8 312 - #define bTxHTSTBC 0x30 313 - #define bTxHTAdvanceCoding 0x40 314 - #define bTxHTShortGI 0x80 315 - #define bTxHTNumberHT_LTF 0x300 316 - #define bTxHTCRC8 0x3fc00 317 - #define bCounterReset 0x10000 318 - #define bNumOfOFDMTx 0xffff 319 - #define bNumOfCCKTx 0xffff0000 320 - #define bTxIdleInterval 0xffff 321 - #define bOFDMService 0xffff0000 322 - #define bTxMACHeader 0xffffffff 323 - #define bTxDataInit 0xff 324 - #define bTxHTMode 0x100 325 - #define bTxDataType 0x30000 326 - #define bTxRandomSeed 0xffffffff 327 - #define bCCKTxPreamble 0x1 328 - #define bCCKTxSFD 0xffff0000 329 - #define bCCKTxSIG 0xff 330 - #define bCCKTxService 0xff00 331 - #define bCCKLengthExt 0x8000 332 - #define bCCKTxLength 0xffff0000 333 - #define bCCKTxCRC16 0xffff 334 - #define bCCKTxStatus 0x1 335 - #define bOFDMTxStatus 0x2 336 - 337 - #define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) 338 369 339 370 /* 2. Page8(0x800) */ 340 371 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ 341 - #define bJapanMode 0x2 342 - #define bCCKTxSC 0x30 343 - #define bCCKEn 0x1000000 344 - #define bOFDMEn 0x2000000 345 - 346 - #define bOFDMRxADCPhase 0x10000 /* Useless now */ 347 - #define bOFDMTxDACPhase 0x40000 348 - #define bXATxAGC 0x3f 349 - 350 - #define bAntennaSelect 0x0300 351 - 352 - #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ 353 - #define bXCTxAGC 0xf000 354 - #define bXDTxAGC 0xf0000 355 - 356 - #define bPAStart 0xf0000000 /* Useless now */ 357 - #define bTRStart 0x00f00000 358 - #define bRFStart 0x0000f000 359 - #define bBBStart 0x000000f0 360 - #define bBBCCKStart 0x0000000f 361 - #define bPAEnd 0xf /* Reg0x814 */ 362 - #define bTREnd 0x0f000000 363 - #define bRFEnd 0x000f0000 364 - #define bCCAMask 0x000000f0 /* T2R */ 365 - #define bR2RCCAMask 0x00000f00 366 - #define bHSSI_R2TDelay 0xf8000000 367 - #define bHSSI_T2RDelay 0xf80000 368 - #define bContTxHSSI 0x400 /* chane gain at continue Tx */ 369 - #define bIGFromCCK 0x200 370 - #define bAGCAddress 0x3f 371 - #define bRxHPTx 0x7000 372 - #define bRxHPT2R 0x38000 373 - #define bRxHPCCKIni 0xc0000 374 - #define bAGCTxCode 0xc00000 375 - #define bAGCRxCode 0x300000 376 372 377 373 #define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */ 378 374 #define b3WireAddressLength 0x400 379 375 380 - #define b3WireRFPowerDown 0x1 /* Useless now */ 381 - /* define bHWSISelect 0x8 */ 382 - #define b2GPAPEPolarity 0x80000000 383 - #define bRFSW_TxDefaultAnt 0x3 384 - #define bRFSW_TxOptionAnt 0x30 385 - #define bRFSW_RxDefaultAnt 0x300 386 - #define bRFSW_RxOptionAnt 0x3000 387 - #define bRFSI_3WireData 0x1 388 - #define bRFSI_3WireClock 0x2 389 - #define bRFSI_3WireLoad 0x4 390 - #define bRFSI_3WireRW 0x8 391 - #define bRFSI_3Wire 0xf 392 - 393 376 #define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */ 394 - 395 - #define bRFSI_TRSW 0x20 /* Useless now */ 396 - #define bRFSI_TRSWB 0x40 397 - #define bRFSI_ANTSW 0x100 398 - #define bRFSI_ANTSWB 0x200 399 - #define bRFSI_PAPE 0x400 400 - #define bBandSelect 0x1 401 - #define bHTSIG2_GI 0x80 402 - #define bHTSIG2_Smoothing 0x01 403 - #define bHTSIG2_Sounding 0x02 404 - #define bHTSIG2_Aggreaton 0x08 405 - #define bHTSIG2_STBC 0x30 406 - #define bHTSIG2_AdvCoding 0x40 407 - #define bHTSIG2_NumOfHTLTF 0x300 408 - #define bHTSIG2_CRC8 0x3fc 409 - #define bHTSIG1_MCS 0x7f 410 - #define bHTSIG1_BandWidth 0x80 411 - #define bHTSIG1_HTLength 0xffff 412 - #define bLSIG_Rate 0xf 413 - #define bLSIG_Reserved 0x10 414 - #define bLSIG_Length 0x1fffe 415 - #define bLSIG_Parity 0x20 416 - #define bCCKRxPhase 0x4 417 377 418 378 #define bLSSIReadAddress 0x7f800000 /* T65 RF */ 419 379 ··· 206 596 207 597 #define bLSSIReadBackData 0xfffff /* T65 RF */ 208 598 209 - #define bLSSIReadOKFlag 0x1000 /* Useless now */ 210 - #define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */ 211 - #define bRegulator0Standby 0x1 212 - #define bRegulatorPLLStandby 0x2 213 - #define bRegulator1Standby 0x4 214 - #define bPLLPowerUp 0x8 215 - #define bDPLLPowerUp 0x10 216 - #define bDA10PowerUp 0x20 217 - #define bAD7PowerUp 0x200 218 - #define bDA6PowerUp 0x2000 219 - #define bXtalPowerUp 0x4000 220 - #define b40MDClkPowerUP 0x8000 221 - #define bDA6DebugMode 0x20000 222 - #define bDA6Swing 0x380000 223 - 224 - #define bADClkPhase 0x4000000 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */ 225 - 226 - #define b80MClkDelay 0x18000000 /* Useless */ 227 - #define bAFEWatchDogEnable 0x20000000 228 - 229 - #define bXtalCap01 0xc0000000 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */ 230 - #define bXtalCap23 0x3 231 - #define bXtalCap92x 0x0f000000 232 - #define bXtalCap 0x0f000000 233 - 234 - #define bIntDifClkEnable 0x400 /* Useless */ 235 - #define bExtSigClkEnable 0x800 236 - #define bBandgapMbiasPowerUp 0x10000 237 - #define bAD11SHGain 0xc0000 238 - #define bAD11InputRange 0x700000 239 - #define bAD11OPCurrent 0x3800000 240 - #define bIPathLoopback 0x4000000 241 - #define bQPathLoopback 0x8000000 242 - #define bAFELoopback 0x10000000 243 - #define bDA10Swing 0x7e0 244 - #define bDA10Reverse 0x800 245 - #define bDAClkSource 0x1000 246 - #define bAD7InputRange 0x6000 247 - #define bAD7Gain 0x38000 248 - #define bAD7OutputCMMode 0x40000 249 - #define bAD7InputCMMode 0x380000 250 - #define bAD7Current 0xc00000 251 - #define bRegulatorAdjust 0x7000000 252 - #define bAD11PowerUpAtTx 0x1 253 - #define bDA10PSAtTx 0x10 254 - #define bAD11PowerUpAtRx 0x100 255 - #define bDA10PSAtRx 0x1000 256 - #define bCCKRxAGCFormat 0x200 257 - #define bPSDFFTSamplepPoint 0xc000 258 - #define bPSDAverageNum 0x3000 259 - #define bIQPathControl 0xc00 260 - #define bPSDFreq 0x3ff 261 - #define bPSDAntennaPath 0x30 262 - #define bPSDIQSwitch 0x40 263 - #define bPSDRxTrigger 0x400000 264 - #define bPSDTxTrigger 0x80000000 265 - #define bPSDSineToneScale 0x7f000000 266 - #define bPSDReport 0xffff 267 - 268 - /* 3. Page9(0x900) */ 269 - #define bOFDMTxSC 0x30000000 /* Useless */ 270 - #define bCCKTxOn 0x1 271 - #define bOFDMTxOn 0x2 272 - #define bDebugPage 0xfff /* reset debug page and also HWord, LWord */ 273 - #define bDebugItem 0xff /* reset debug page and LWord */ 274 - #define bAntL 0x10 275 - #define bAntNonHT 0x100 276 - #define bAntHT1 0x1000 277 - #define bAntHT2 0x10000 278 - #define bAntHT1S1 0x100000 279 - #define bAntNonHTS1 0x1000000 280 - 281 599 /* 4. PageA(0xA00) */ 282 - #define bCCKBBMode 0x3 /* Useless */ 283 - #define bCCKTxPowerSaving 0x80 284 - #define bCCKRxPowerSaving 0x40 285 - 286 600 #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */ 287 - 288 - #define bCCKScramble 0x8 /* Useless */ 289 - #define bCCKAntDiversity 0x8000 290 - #define bCCKCarrierRecovery 0x4000 291 - #define bCCKTxRate 0x3000 292 - #define bCCKDCCancel 0x0800 293 - #define bCCKISICancel 0x0400 294 - #define bCCKMatchFilter 0x0200 295 - #define bCCKEqualizer 0x0100 296 - #define bCCKPreambleDetect 0x800000 297 - #define bCCKFastFalseCCA 0x400000 298 - #define bCCKChEstStart 0x300000 299 - #define bCCKCCACount 0x080000 300 - #define bCCKcs_lim 0x070000 301 - #define bCCKBistMode 0x80000000 302 - #define bCCKCCAMask 0x40000000 303 - #define bCCKTxDACPhase 0x4 304 - #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ 305 - #define bCCKr_cp_mode0 0x0100 306 - #define bCCKTxDCOffset 0xf0 307 - #define bCCKRxDCOffset 0xf 308 - #define bCCKCCAMode 0xc000 309 - #define bCCKFalseCS_lim 0x3f00 310 - #define bCCKCS_ratio 0xc00000 311 - #define bCCKCorgBit_sel 0x300000 312 - #define bCCKPD_lim 0x0f0000 313 - #define bCCKNewCCA 0x80000000 314 - #define bCCKRxHPofIG 0x8000 315 - #define bCCKRxIG 0x7f00 316 - #define bCCKLNAPolarity 0x800000 317 - #define bCCKRx1stGain 0x7f0000 318 - #define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ 319 - #define bCCKRxAGCSatLevel 0x1f000000 320 - #define bCCKRxAGCSatCount 0xe0 321 - #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ 322 - #define bCCKFixedRxAGC 0x8000 323 - #define bCCKAntennaPolarity 0x2000 324 - #define bCCKTxFilterType 0x0c00 325 - #define bCCKRxAGCReportType 0x0300 326 - #define bCCKRxDAGCEn 0x80000000 327 - #define bCCKRxDAGCPeriod 0x20000000 328 - #define bCCKRxDAGCSatLevel 0x1f000000 329 - #define bCCKTimingRecovery 0x800000 330 - #define bCCKTxC0 0x3f0000 331 - #define bCCKTxC1 0x3f000000 332 - #define bCCKTxC2 0x3f 333 - #define bCCKTxC3 0x3f00 334 - #define bCCKTxC4 0x3f0000 335 - #define bCCKTxC5 0x3f000000 336 - #define bCCKTxC6 0x3f 337 - #define bCCKTxC7 0x3f00 338 - #define bCCKDebugPort 0xff0000 339 - #define bCCKDACDebug 0x0f000000 340 - #define bCCKFalseAlarmEnable 0x8000 341 - #define bCCKFalseAlarmRead 0x4000 342 - #define bCCKTRSSI 0x7f 343 - #define bCCKRxAGCReport 0xfe 344 - #define bCCKRxReport_AntSel 0x80000000 345 - #define bCCKRxReport_MFOff 0x40000000 346 - #define bCCKRxRxReport_SQLoss 0x20000000 347 - #define bCCKRxReport_Pktloss 0x10000000 348 - #define bCCKRxReport_Lockedbit 0x08000000 349 - #define bCCKRxReport_RateError 0x04000000 350 - #define bCCKRxReport_RxRate 0x03000000 351 - #define bCCKRxFACounterLower 0xff 352 - #define bCCKRxFACounterUpper 0xff000000 353 - #define bCCKRxHPAGCStart 0xe000 354 - #define bCCKRxHPAGCFinal 0x1c00 355 - #define bCCKRxFalseAlarmEnable 0x8000 356 - #define bCCKFACounterFreeze 0x4000 357 - #define bCCKTxPathSel 0x10000000 358 - #define bCCKDefaultRxPath 0xc000000 359 - #define bCCKOptionRxPath 0x3000000 360 - 361 - /* 5. PageC(0xC00) */ 362 - #define bNumOfSTF 0x3 /* Useless */ 363 - #define bShift_L 0xc0 364 - #define bGI_TH 0xc 365 - #define bRxPathA 0x1 366 - #define bRxPathB 0x2 367 - #define bRxPathC 0x4 368 - #define bRxPathD 0x8 369 - #define bTxPathA 0x1 370 - #define bTxPathB 0x2 371 - #define bTxPathC 0x4 372 - #define bTxPathD 0x8 373 - #define bTRSSIFreq 0x200 374 - #define bADCBackoff 0x3000 375 - #define bDFIRBackoff 0xc000 376 - #define bTRSSILatchPhase 0x10000 377 - #define bRxIDCOffset 0xff 378 - #define bRxQDCOffset 0xff00 379 - #define bRxDFIRMode 0x1800000 380 - #define bRxDCNFType 0xe000000 381 - #define bRXIQImb_A 0x3ff 382 - #define bRXIQImb_B 0xfc00 383 - #define bRXIQImb_C 0x3f0000 384 - #define bRXIQImb_D 0xffc00000 385 - #define bDC_dc_Notch 0x60000 386 - #define bRxNBINotch 0x1f000000 387 - #define bPD_TH 0xf 388 - #define bPD_TH_Opt2 0xc000 389 - #define bPWED_TH 0x700 390 - #define bIfMF_Win_L 0x800 391 - #define bPD_Option 0x1000 392 - #define bMF_Win_L 0xe000 393 - #define bBW_Search_L 0x30000 394 - #define bwin_enh_L 0xc0000 395 - #define bBW_TH 0x700000 396 - #define bED_TH2 0x3800000 397 - #define bBW_option 0x4000000 398 - #define bRatio_TH 0x18000000 399 - #define bWindow_L 0xe0000000 400 - #define bSBD_Option 0x1 401 - #define bFrame_TH 0x1c 402 - #define bFS_Option 0x60 403 - #define bDC_Slope_check 0x80 404 - #define bFGuard_Counter_DC_L 0xe00 405 - #define bFrame_Weight_Short 0x7000 406 - #define bSub_Tune 0xe00000 407 - #define bFrame_DC_Length 0xe000000 408 - #define bSBD_start_offset 0x30000000 409 - #define bFrame_TH_2 0x7 410 - #define bFrame_GI2_TH 0x38 411 - #define bGI2_Sync_en 0x40 412 - #define bSarch_Short_Early 0x300 413 - #define bSarch_Short_Late 0xc00 414 - #define bSarch_GI2_Late 0x70000 415 - #define bCFOAntSum 0x1 416 - #define bCFOAcc 0x2 417 - #define bCFOStartOffset 0xc 418 - #define bCFOLookBack 0x70 419 - #define bCFOSumWeight 0x80 420 - #define bDAGCEnable 0x10000 421 - #define bTXIQImb_A 0x3ff 422 - #define bTXIQImb_B 0xfc00 423 - #define bTXIQImb_C 0x3f0000 424 - #define bTXIQImb_D 0xffc00000 425 - #define bTxIDCOffset 0xff 426 - #define bTxQDCOffset 0xff00 427 - #define bTxDFIRMode 0x10000 428 - #define bTxPesudoNoiseOn 0x4000000 429 - #define bTxPesudoNoise_A 0xff 430 - #define bTxPesudoNoise_B 0xff00 431 - #define bTxPesudoNoise_C 0xff0000 432 - #define bTxPesudoNoise_D 0xff000000 433 - #define bCCADropOption 0x20000 434 - #define bCCADropThres 0xfff00000 435 - #define bEDCCA_H 0xf 436 - #define bEDCCA_L 0xf0 437 - #define bLambda_ED 0x300 438 - #define bRxInitialGain 0x7f 439 - #define bRxAntDivEn 0x80 440 - #define bRxAGCAddressForLNA 0x7f00 441 - #define bRxHighPowerFlow 0x8000 442 - #define bRxAGCFreezeThres 0xc0000 443 - #define bRxFreezeStep_AGC1 0x300000 444 - #define bRxFreezeStep_AGC2 0xc00000 445 - #define bRxFreezeStep_AGC3 0x3000000 446 - #define bRxFreezeStep_AGC0 0xc000000 447 - #define bRxRssi_Cmp_En 0x10000000 448 - #define bRxQuickAGCEn 0x20000000 449 - #define bRxAGCFreezeThresMode 0x40000000 450 - #define bRxOverFlowCheckType 0x80000000 451 - #define bRxAGCShift 0x7f 452 - #define bTRSW_Tri_Only 0x80 453 - #define bPowerThres 0x300 454 - #define bRxAGCEn 0x1 455 - #define bRxAGCTogetherEn 0x2 456 - #define bRxAGCMin 0x4 457 - #define bRxHP_Ini 0x7 458 - #define bRxHP_TRLNA 0x70 459 - #define bRxHP_RSSI 0x700 460 - #define bRxHP_BBP1 0x7000 461 - #define bRxHP_BBP2 0x70000 462 - #define bRxHP_BBP3 0x700000 463 - #define bRSSI_H 0x7f0000 /* the threshold for high power */ 464 - #define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */ 465 - #define bRxSettle_TRSW 0x7 466 - #define bRxSettle_LNA 0x38 467 - #define bRxSettle_RSSI 0x1c0 468 - #define bRxSettle_BBP 0xe00 469 - #define bRxSettle_RxHP 0x7000 470 - #define bRxSettle_AntSW_RSSI 0x38000 471 - #define bRxSettle_AntSW 0xc0000 472 - #define bRxProcessTime_DAGC 0x300000 473 - #define bRxSettle_HSSI 0x400000 474 - #define bRxProcessTime_BBPPW 0x800000 475 - #define bRxAntennaPowerShift 0x3000000 476 - #define bRSSITableSelect 0xc000000 477 - #define bRxHP_Final 0x7000000 478 - #define bRxHTSettle_BBP 0x7 479 - #define bRxHTSettle_HSSI 0x8 480 - #define bRxHTSettle_RxHP 0x70 481 - #define bRxHTSettle_BBPPW 0x80 482 - #define bRxHTSettle_Idle 0x300 483 - #define bRxHTSettle_Reserved 0x1c00 484 - #define bRxHTRxHPEn 0x8000 485 - #define bRxHTAGCFreezeThres 0x30000 486 - #define bRxHTAGCTogetherEn 0x40000 487 - #define bRxHTAGCMin 0x80000 488 - #define bRxHTAGCEn 0x100000 489 - #define bRxHTDAGCEn 0x200000 490 - #define bRxHTRxHP_BBP 0x1c00000 491 - #define bRxHTRxHP_Final 0xe0000000 492 - #define bRxPWRatioTH 0x3 493 - #define bRxPWRatioEn 0x4 494 - #define bRxMFHold 0x3800 495 - #define bRxPD_Delay_TH1 0x38 496 - #define bRxPD_Delay_TH2 0x1c0 497 - #define bRxPD_DC_COUNT_MAX 0x600 498 - /* define bRxMF_Hold 0x3800 */ 499 - #define bRxPD_Delay_TH 0x8000 500 - #define bRxProcess_Delay 0xf0000 501 - #define bRxSearchrange_GI2_Early 0x700000 502 - #define bRxFrame_Guard_Counter_L 0x3800000 503 - #define bRxSGI_Guard_L 0xc000000 504 - #define bRxSGI_Search_L 0x30000000 505 - #define bRxSGI_TH 0xc0000000 506 - #define bDFSCnt0 0xff 507 - #define bDFSCnt1 0xff00 508 - #define bDFSFlag 0xf0000 509 - #define bMFWeightSum 0x300000 510 - #define bMinIdxTH 0x7f000000 511 - #define bDAFormat 0x40000 512 - #define bTxChEmuEnable 0x01000000 513 - #define bTRSWIsolation_A 0x7f 514 - #define bTRSWIsolation_B 0x7f00 515 - #define bTRSWIsolation_C 0x7f0000 516 - #define bTRSWIsolation_D 0x7f000000 517 - #define bExtLNAGain 0x7c00 518 - 519 - /* 6. PageE(0xE00) */ 520 - #define bSTBCEn 0x4 /* Useless */ 521 - #define bAntennaMapping 0x10 522 - #define bNss 0x20 523 - #define bCFOAntSumD 0x200 524 - #define bPHYCounterReset 0x8000000 525 - #define bCFOReportGet 0x4000000 526 - #define bOFDMContinueTx 0x10000000 527 - #define bOFDMSingleCarrier 0x20000000 528 - #define bOFDMSingleTone 0x40000000 529 - /* define bRxPath1 0x01 */ 530 - /* define bRxPath2 0x02 */ 531 - /* define bRxPath3 0x04 */ 532 - /* define bRxPath4 0x08 */ 533 - /* define bTxPath1 0x10 */ 534 - /* define bTxPath2 0x20 */ 535 - #define bHTDetect 0x100 536 - #define bCFOEn 0x10000 537 - #define bCFOValue 0xfff00000 538 - #define bSigTone_Re 0x3f 539 - #define bSigTone_Im 0x7f00 540 - #define bCounter_CCA 0xffff 541 - #define bCounter_ParityFail 0xffff0000 542 - #define bCounter_RateIllegal 0xffff 543 - #define bCounter_CRC8Fail 0xffff0000 544 - #define bCounter_MCSNoSupport 0xffff 545 - #define bCounter_FastSync 0xffff 546 - #define bShortCFO 0xfff 547 - #define bShortCFOTLength 12 /* total */ 548 - #define bShortCFOFLength 11 /* fraction */ 549 - #define bLongCFO 0x7ff 550 - #define bLongCFOTLength 11 551 - #define bLongCFOFLength 11 552 - #define bTailCFO 0x1fff 553 - #define bTailCFOTLength 13 554 - #define bTailCFOFLength 12 555 - #define bmax_en_pwdB 0xffff 556 - #define bCC_power_dB 0xffff0000 557 - #define bnoise_pwdB 0xffff 558 - #define bPowerMeasTLength 10 559 - #define bPowerMeasFLength 3 560 - #define bRx_HT_BW 0x1 561 - #define bRxSC 0x6 562 - #define bRx_HT 0x8 563 - #define bNB_intf_det_on 0x1 564 - #define bIntf_win_len_cfg 0x30 565 - #define bNB_Intf_TH_cfg 0x1c0 566 - #define bRFGain 0x3f 567 - #define bTableSel 0x40 568 - #define bTRSW 0x80 569 - #define bRxSNR_A 0xff 570 - #define bRxSNR_B 0xff00 571 - #define bRxSNR_C 0xff0000 572 - #define bRxSNR_D 0xff000000 573 - #define bSNREVMTLength 8 574 - #define bSNREVMFLength 1 575 - #define bCSI1st 0xff 576 - #define bCSI2nd 0xff00 577 - #define bRxEVM1st 0xff0000 578 - #define bRxEVM2nd 0xff000000 579 - #define bSIGEVM 0xff 580 - #define bPWDB 0xff00 581 - #define bSGIEN 0x10000 582 - 583 - #define bSFactorQAM1 0xf /* Useless */ 584 - #define bSFactorQAM2 0xf0 585 - #define bSFactorQAM3 0xf00 586 - #define bSFactorQAM4 0xf000 587 - #define bSFactorQAM5 0xf0000 588 - #define bSFactorQAM6 0xf0000 589 - #define bSFactorQAM7 0xf00000 590 - #define bSFactorQAM8 0xf000000 591 - #define bSFactorQAM9 0xf0000000 592 - #define bCSIScheme 0x100000 593 - 594 - #define bNoiseLvlTopSet 0x3 /* Useless */ 595 - #define bChSmooth 0x4 596 - #define bChSmoothCfg1 0x38 597 - #define bChSmoothCfg2 0x1c0 598 - #define bChSmoothCfg3 0xe00 599 - #define bChSmoothCfg4 0x7000 600 - #define bMRCMode 0x800000 601 - #define bTHEVMCfg 0x7000000 602 - 603 - #define bLoopFitType 0x1 /* Useless */ 604 - #define bUpdCFO 0x40 605 - #define bUpdCFOOffData 0x80 606 - #define bAdvUpdCFO 0x100 607 - #define bAdvTimeCtrl 0x800 608 - #define bUpdClko 0x1000 609 - #define bFC 0x6000 610 - #define bTrackingMode 0x8000 611 - #define bPhCmpEnable 0x10000 612 - #define bUpdClkoLTF 0x20000 613 - #define bComChCFO 0x40000 614 - #define bCSIEstiMode 0x80000 615 - #define bAdvUpdEqz 0x100000 616 - #define bUChCfg 0x7000000 617 - #define bUpdEqz 0x8000000 618 - 619 - /* Rx Pseduo noise */ 620 - #define bRxPesudoNoiseOn 0x20000000 /* Useless */ 621 - #define bRxPesudoNoise_A 0xff 622 - #define bRxPesudoNoise_B 0xff00 623 - #define bRxPesudoNoise_C 0xff0000 624 - #define bRxPesudoNoise_D 0xff000000 625 - #define bPesudoNoiseState_A 0xffff 626 - #define bPesudoNoiseState_B 0xffff0000 627 - #define bPesudoNoiseState_C 0xffff 628 - #define bPesudoNoiseState_D 0xffff0000 629 - 630 - /* 7. RF Register */ 631 - /* Zebra1 */ 632 - #define bZebra1_HSSIEnable 0x8 /* Useless */ 633 - #define bZebra1_TRxControl 0xc00 634 - #define bZebra1_TRxGainSetting 0x07f 635 - #define bZebra1_RxCorner 0xc00 636 - #define bZebra1_TxChargePump 0x38 637 - #define bZebra1_RxChargePump 0x7 638 - #define bZebra1_ChannelNum 0xf80 639 - #define bZebra1_TxLPFBW 0x400 640 - #define bZebra1_RxLPFBW 0x600 641 - 642 - /* Zebra4 */ 643 - #define bRTL8256RegModeCtrl1 0x100 /* Useless */ 644 - #define bRTL8256RegModeCtrl0 0x40 645 - #define bRTL8256_TxLPFBW 0x18 646 - #define bRTL8256_RxLPFBW 0x600 647 - 648 - /* RTL8258 */ 649 - #define bRTL8258_TxLPFBW 0xc /* Useless */ 650 - #define bRTL8258_RxLPFBW 0xc00 651 - #define bRTL8258_RSSILPFBW 0xc0 652 - 653 601 654 602 /* */ 655 603 /* Other Definition */ 656 604 /* */ 657 - 658 - /* byte endable for sb_write */ 659 - #define bByte0 0x1 /* Useless */ 660 - #define bByte1 0x2 661 - #define bByte2 0x4 662 - #define bByte3 0x8 663 - #define bWord0 0x3 664 - #define bWord1 0xc 665 - #define bDWord 0xf 666 605 667 606 /* for PutRegsetting & GetRegSetting BitMask */ 668 607 #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ ··· 224 1065 #define bMaskH3Bytes 0xffffff00 225 1066 #define bMask12Bits 0xfff 226 1067 #define bMaskH4Bits 0xf0000000 227 - #define bMaskOFDM_D 0xffc00000 228 - #define bMaskCCK 0x3f3f3f3f 229 - 230 1068 231 1069 #define bEnable 0x1 /* Useless */ 232 - #define bDisable 0x0 233 - 234 - #define LeftAntenna 0x0 /* Useless */ 235 - #define RightAntenna 0x1 236 - 237 - #define tCheckTxStatus 500 /* 500ms Useless */ 238 - #define tUpdateRxCounter 100 /* 100ms */ 239 - 240 - #define rateCCK 0 /* Useless */ 241 - #define rateOFDM 1 242 - #define rateHT 2 243 - 244 - /* define Register-End */ 245 - #define bPMAC_End 0x1ff /* Useless */ 246 - #define bFPGAPHY0_End 0x8ff 247 - #define bFPGAPHY1_End 0x9ff 248 - #define bCCKPHY0_End 0xaff 249 - #define bOFDMPHY0_End 0xcff 250 - #define bOFDMPHY1_End 0xdff 251 - 252 - /* define max debug item in each debug page */ 253 - /* define bMaxItem_FPGA_PHY0 0x9 */ 254 - /* define bMaxItem_FPGA_PHY1 0x3 */ 255 - /* define bMaxItem_PHY_11B 0x16 */ 256 - /* define bMaxItem_OFDM_PHY0 0x29 */ 257 - /* define bMaxItem_OFDM_PHY1 0x0 */ 258 - 259 - #define bPMACControl 0x0 /* Useless */ 260 - #define bWMACControl 0x1 261 - #define bWNICControl 0x2 262 - 263 - #define PathA 0x0 /* Useless */ 264 - #define PathB 0x1 265 - #define PathC 0x2 266 - #define PathD 0x3 267 - 268 - /*--------------------------Define Parameters-------------------------------*/ 269 1070 270 1071 #define rDPDT_control 0x92c 271 1072