Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
tjh.dev
kernel
os
linux
Merge tag 'loongarch-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
Pull LoongArch updates from Huacai Chen:
- Select some options in Kconfig
- Give a chance to build with !CONFIG_SMP
- Switch to use built-in rustc target
- Add new supported device nodes to dts
- Some bug fixes and other small changes
- Update the default config file
* tag 'loongarch-6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson:
LoongArch: Update Loongson-3 default config file
LoongArch: dts: Add new supported device nodes to Loongson-2K2000
LoongArch: dts: Add new supported device nodes to Loongson-2K0500
LoongArch: dts: Remove "disabled" state of clock controller node
LoongArch: rust: Switch to use built-in rustc target
LoongArch: Fix callchain parse error with kernel tracepoint events again
LoongArch: Give a chance to build with !CONFIG_SMP
LoongArch: Select THP_SWAP if HAVE_ARCH_TRANSPARENT_HUGEPAGE
LoongArch: Select ARCH_WANT_DEFAULT_BPF_JIT
LoongArch: Select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
LoongArch: Select ARCH_HAS_FAST_MULTIPLIER
+5
-1
arch/loongarch/Kconfig
+5
-1
arch/loongarch/Kconfig
···
16
select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
17
select ARCH_HAS_CPU_FINALIZE_INIT
18
select ARCH_HAS_CURRENT_STACK_POINTER
19
select ARCH_HAS_FORTIFY_SOURCE
20
select ARCH_HAS_KCOV
21
select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS
···
57
select ARCH_SUPPORTS_ACPI
58
select ARCH_SUPPORTS_ATOMIC_RMW
59
select ARCH_SUPPORTS_HUGETLBFS
60
select ARCH_SUPPORTS_LTO_CLANG
61
select ARCH_SUPPORTS_LTO_CLANG_THIN
62
select ARCH_SUPPORTS_NUMA_BALANCING
···
65
select ARCH_USE_CMPXCHG_LOCKREF
66
select ARCH_USE_QUEUED_RWLOCKS
67
select ARCH_USE_QUEUED_SPINLOCKS
68
select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
69
select ARCH_WANT_LD_ORPHAN_WARN
70
select ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP
71
select ARCH_WANTS_NO_INSTR
72
select BUILDTIME_TABLE_SORT
73
select COMMON_CLK
74
select CPU_PM
···
178
select PCI_QUIRKS
179
select PERF_USE_VMALLOC
180
select RTC_LIB
181
-
select SMP
182
select SPARSE_IRQ
183
select SYSCTL_ARCH_UNALIGN_ALLOW
184
select SYSCTL_ARCH_UNALIGN_NO_WARN
···
423
424
config SCHED_SMT
425
bool "SMT scheduler support"
426
default y
427
help
428
Improves scheduler's performance when there are multiple
···
16
select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
17
select ARCH_HAS_CPU_FINALIZE_INIT
18
select ARCH_HAS_CURRENT_STACK_POINTER
19
+
select ARCH_HAS_FAST_MULTIPLIER
20
select ARCH_HAS_FORTIFY_SOURCE
21
select ARCH_HAS_KCOV
22
select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS
···
56
select ARCH_SUPPORTS_ACPI
57
select ARCH_SUPPORTS_ATOMIC_RMW
58
select ARCH_SUPPORTS_HUGETLBFS
59
+
select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
60
select ARCH_SUPPORTS_LTO_CLANG
61
select ARCH_SUPPORTS_LTO_CLANG_THIN
62
select ARCH_SUPPORTS_NUMA_BALANCING
···
63
select ARCH_USE_CMPXCHG_LOCKREF
64
select ARCH_USE_QUEUED_RWLOCKS
65
select ARCH_USE_QUEUED_SPINLOCKS
66
+
select ARCH_WANT_DEFAULT_BPF_JIT
67
select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
68
select ARCH_WANT_LD_ORPHAN_WARN
69
select ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP
70
select ARCH_WANTS_NO_INSTR
71
+
select ARCH_WANTS_THP_SWAP if HAVE_ARCH_TRANSPARENT_HUGEPAGE
72
select BUILDTIME_TABLE_SORT
73
select COMMON_CLK
74
select CPU_PM
···
174
select PCI_QUIRKS
175
select PERF_USE_VMALLOC
176
select RTC_LIB
177
select SPARSE_IRQ
178
select SYSCTL_ARCH_UNALIGN_ALLOW
179
select SYSCTL_ARCH_UNALIGN_NO_WARN
···
420
421
config SCHED_SMT
422
bool "SMT scheduler support"
423
+
depends on SMP
424
default y
425
help
426
Improves scheduler's performance when there are multiple
+1
-1
arch/loongarch/Makefile
+1
-1
arch/loongarch/Makefile
+83
-3
arch/loongarch/boot/dts/loongson-2k0500.dtsi
+83
-3
arch/loongarch/boot/dts/loongson-2k0500.dtsi
···
6
/dts-v1/;
7
8
#include <dt-bindings/interrupt-controller/irq.h>
9
10
/ {
11
#address-cells = <2>;
···
20
compatible = "loongson,la264";
21
device_type = "cpu";
22
reg = <0x0>;
23
-
clocks = <&cpu_clk>;
24
};
25
};
26
27
-
cpu_clk: cpu-clk {
28
compatible = "fixed-clock";
29
#clock-cells = <0>;
30
-
clock-frequency = <500000000>;
31
};
32
33
cpuintc: interrupt-controller {
34
compatible = "loongson,cpu-interrupt-controller";
35
#interrupt-cells = <1>;
36
interrupt-controller;
37
};
38
39
bus@10000000 {
···
74
#size-cells = <1>;
75
#address-cells = <2>;
76
ranges = <1 0x0 0x0 0x16400000 0x4000>;
77
};
78
79
liointc0: interrupt-controller@1fe11400 {
···
209
interrupt-parent = <&eiointc>;
210
interrupts = <72>;
211
status = "disabled";
212
};
213
214
uart0: serial@1ff40800 {
···
6
/dts-v1/;
7
8
#include <dt-bindings/interrupt-controller/irq.h>
9
+
#include <dt-bindings/clock/loongson,ls2k-clk.h>
10
11
/ {
12
#address-cells = <2>;
···
19
compatible = "loongson,la264";
20
device_type = "cpu";
21
reg = <0x0>;
22
+
clocks = <&clk LOONGSON2_NODE_CLK>;
23
};
24
};
25
26
+
ref_100m: clock-ref-100m {
27
compatible = "fixed-clock";
28
#clock-cells = <0>;
29
+
clock-frequency = <100000000>;
30
+
clock-output-names = "ref_100m";
31
};
32
33
cpuintc: interrupt-controller {
34
compatible = "loongson,cpu-interrupt-controller";
35
#interrupt-cells = <1>;
36
interrupt-controller;
37
+
};
38
+
39
+
thermal-zones {
40
+
cpu-thermal {
41
+
polling-delay-passive = <1000>;
42
+
polling-delay = <5000>;
43
+
thermal-sensors = <&tsensor 0>;
44
+
45
+
trips {
46
+
cpu-alert {
47
+
temperature = <33000>;
48
+
hysteresis = <2000>;
49
+
type = "active";
50
+
};
51
+
52
+
cpu-crit {
53
+
temperature = <85000>;
54
+
hysteresis = <5000>;
55
+
type = "critical";
56
+
};
57
+
};
58
+
};
59
};
60
61
bus@10000000 {
···
50
#size-cells = <1>;
51
#address-cells = <2>;
52
ranges = <1 0x0 0x0 0x16400000 0x4000>;
53
+
};
54
+
55
+
clk: clock-controller@1fe10400 {
56
+
compatible = "loongson,ls2k0500-clk";
57
+
reg = <0x0 0x1fe10400 0x0 0x2c>;
58
+
#clock-cells = <1>;
59
+
clocks = <&ref_100m>;
60
+
clock-names = "ref_100m";
61
+
};
62
+
63
+
dma-controller@1fe10c00 {
64
+
compatible = "loongson,ls2k0500-apbdma", "loongson,ls2k1000-apbdma";
65
+
reg = <0 0x1fe10c00 0 0x8>;
66
+
interrupt-parent = <&eiointc>;
67
+
interrupts = <67>;
68
+
clocks = <&clk LOONGSON2_APB_CLK>;
69
+
#dma-cells = <1>;
70
+
status = "disabled";
71
+
};
72
+
73
+
dma-controller@1fe10c10 {
74
+
compatible = "loongson,ls2k0500-apbdma", "loongson,ls2k1000-apbdma";
75
+
reg = <0 0x1fe10c10 0 0x8>;
76
+
interrupt-parent = <&eiointc>;
77
+
interrupts = <68>;
78
+
clocks = <&clk LOONGSON2_APB_CLK>;
79
+
#dma-cells = <1>;
80
+
status = "disabled";
81
+
};
82
+
83
+
dma-controller@1fe10c20 {
84
+
compatible = "loongson,ls2k0500-apbdma", "loongson,ls2k1000-apbdma";
85
+
reg = <0 0x1fe10c20 0 0x8>;
86
+
interrupt-parent = <&eiointc>;
87
+
interrupts = <69>;
88
+
clocks = <&clk LOONGSON2_APB_CLK>;
89
+
#dma-cells = <1>;
90
+
status = "disabled";
91
+
};
92
+
93
+
dma-controller@1fe10c30 {
94
+
compatible = "loongson,ls2k0500-apbdma", "loongson,ls2k1000-apbdma";
95
+
reg = <0 0x1fe10c30 0 0x8>;
96
+
interrupt-parent = <&eiointc>;
97
+
interrupts = <70>;
98
+
clocks = <&clk LOONGSON2_APB_CLK>;
99
+
#dma-cells = <1>;
100
+
status = "disabled";
101
};
102
103
liointc0: interrupt-controller@1fe11400 {
···
137
interrupt-parent = <&eiointc>;
138
interrupts = <72>;
139
status = "disabled";
140
+
};
141
+
142
+
tsensor: thermal-sensor@1fe11500 {
143
+
compatible = "loongson,ls2k0500-thermal", "loongson,ls2k1000-thermal";
144
+
reg = <0x0 0x1fe11500 0x0 0x30>;
145
+
interrupt-parent = <&liointc0>;
146
+
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
147
+
#thermal-sensor-cells = <1>;
148
};
149
150
uart0: serial@1ff40800 {
-4
arch/loongarch/boot/dts/loongson-2k1000-ref.dts
-4
arch/loongarch/boot/dts/loongson-2k1000-ref.dts
-1
arch/loongarch/boot/dts/loongson-2k1000.dtsi
-1
arch/loongarch/boot/dts/loongson-2k1000.dtsi
+45
-4
arch/loongarch/boot/dts/loongson-2k2000.dtsi
+45
-4
arch/loongarch/boot/dts/loongson-2k2000.dtsi
···
6
/dts-v1/;
7
8
#include <dt-bindings/interrupt-controller/irq.h>
9
10
/ {
11
#address-cells = <2>;
···
20
compatible = "loongson,la364";
21
device_type = "cpu";
22
reg = <0x0>;
23
-
clocks = <&cpu_clk>;
24
};
25
26
cpu1: cpu@2 {
27
compatible = "loongson,la364";
28
device_type = "cpu";
29
reg = <0x1>;
30
-
clocks = <&cpu_clk>;
31
};
32
};
33
34
-
cpu_clk: cpu-clk {
35
compatible = "fixed-clock";
36
#clock-cells = <0>;
37
-
clock-frequency = <1400000000>;
38
};
39
40
cpuintc: interrupt-controller {
41
compatible = "loongson,cpu-interrupt-controller";
42
#interrupt-cells = <1>;
43
interrupt-controller;
44
};
45
46
bus@10000000 {
···
80
#size-cells = <1>;
81
#address-cells = <2>;
82
ranges = <1 0x0 0x0 0x18400000 0x4000>;
83
};
84
85
pmc: power-management@100d0000 {
···
110
mask = <0x3c00>;
111
value = <0x3c00>;
112
};
113
};
114
115
liointc: interrupt-controller@1fe01400 {
···
6
/dts-v1/;
7
8
#include <dt-bindings/interrupt-controller/irq.h>
9
+
#include <dt-bindings/clock/loongson,ls2k-clk.h>
10
11
/ {
12
#address-cells = <2>;
···
19
compatible = "loongson,la364";
20
device_type = "cpu";
21
reg = <0x0>;
22
+
clocks = <&clk LOONGSON2_NODE_CLK>;
23
};
24
25
cpu1: cpu@2 {
26
compatible = "loongson,la364";
27
device_type = "cpu";
28
reg = <0x1>;
29
+
clocks = <&clk LOONGSON2_NODE_CLK>;
30
};
31
};
32
33
+
ref_100m: clock-ref-100m {
34
compatible = "fixed-clock";
35
#clock-cells = <0>;
36
+
clock-frequency = <100000000>;
37
+
clock-output-names = "ref_100m";
38
};
39
40
cpuintc: interrupt-controller {
41
compatible = "loongson,cpu-interrupt-controller";
42
#interrupt-cells = <1>;
43
interrupt-controller;
44
+
};
45
+
46
+
thermal-zones {
47
+
cpu-thermal {
48
+
polling-delay-passive = <1000>;
49
+
polling-delay = <5000>;
50
+
thermal-sensors = <&tsensor 0>;
51
+
52
+
trips {
53
+
cpu-alert {
54
+
temperature = <40000>;
55
+
hysteresis = <2000>;
56
+
type = "active";
57
+
};
58
+
59
+
cpu-crit {
60
+
temperature = <85000>;
61
+
hysteresis = <5000>;
62
+
type = "critical";
63
+
};
64
+
};
65
+
};
66
};
67
68
bus@10000000 {
···
56
#size-cells = <1>;
57
#address-cells = <2>;
58
ranges = <1 0x0 0x0 0x18400000 0x4000>;
59
+
};
60
+
61
+
clk: clock-controller@10010480 {
62
+
compatible = "loongson,ls2k2000-clk";
63
+
reg = <0x0 0x10010480 0x0 0x100>;
64
+
#clock-cells = <1>;
65
+
clocks = <&ref_100m>;
66
+
clock-names = "ref_100m";
67
};
68
69
pmc: power-management@100d0000 {
···
78
mask = <0x3c00>;
79
value = <0x3c00>;
80
};
81
+
};
82
+
83
+
tsensor: thermal-sensor@1fe01460 {
84
+
compatible = "loongson,ls2k2000-thermal";
85
+
reg = <0x0 0x1fe01460 0x0 0x30>,
86
+
<0x0 0x1fe0019c 0x0 0x4>;
87
+
interrupt-parent = <&liointc>;
88
+
interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
89
+
#thermal-sensor-cells = <1>;
90
};
91
92
liointc: interrupt-controller@1fe01400 {
+24
arch/loongarch/configs/loongson3_defconfig
+24
arch/loongarch/configs/loongson3_defconfig
···
14
CONFIG_TASK_DELAY_ACCT=y
15
CONFIG_TASK_XACCT=y
16
CONFIG_TASK_IO_ACCOUNTING=y
17
CONFIG_LOG_BUF_SHIFT=18
18
CONFIG_NUMA_BALANCING=y
19
CONFIG_MEMCG=y
···
133
CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
134
CONFIG_IP_PIMSM_V1=y
135
CONFIG_IP_PIMSM_V2=y
136
CONFIG_INET_ESP=m
137
CONFIG_INET_UDP_DIAG=y
138
CONFIG_TCP_CONG_ADVANCED=y
139
CONFIG_TCP_CONG_BBR=m
140
CONFIG_IPV6_ROUTER_PREF=y
141
CONFIG_IPV6_ROUTE_INFO=y
142
CONFIG_INET6_ESP=m
143
CONFIG_IPV6_MROUTE=y
144
CONFIG_MPTCP=y
145
CONFIG_NETWORK_PHY_TIMESTAMPING=y
···
164
CONFIG_NF_CONNTRACK_TFTP=m
165
CONFIG_NF_CT_NETLINK=m
166
CONFIG_NF_TABLES=m
167
CONFIG_NFT_CONNLIMIT=m
168
CONFIG_NFT_LOG=m
169
CONFIG_NFT_LIMIT=m
···
178
CONFIG_NFT_REJECT=m
179
CONFIG_NFT_COMPAT=m
180
CONFIG_NFT_HASH=m
181
CONFIG_NFT_SOCKET=m
182
CONFIG_NFT_OSF=m
183
CONFIG_NFT_TPROXY=m
···
275
CONFIG_IP_NF_ARPFILTER=m
276
CONFIG_IP_NF_ARP_MANGLE=m
277
CONFIG_NF_TABLES_IPV6=y
278
CONFIG_IP6_NF_IPTABLES=y
279
CONFIG_IP6_NF_MATCH_AH=m
280
CONFIG_IP6_NF_MATCH_EUI64=m
···
296
CONFIG_IP6_NF_TARGET_MASQUERADE=m
297
CONFIG_IP6_NF_TARGET_NPT=m
298
CONFIG_NF_TABLES_BRIDGE=m
299
CONFIG_BRIDGE_NF_EBTABLES=m
300
CONFIG_BRIDGE_EBT_BROUTE=m
301
CONFIG_BRIDGE_EBT_T_FILTER=m
···
567
CONFIG_TXGBE=y
568
# CONFIG_NET_VENDOR_WIZNET is not set
569
# CONFIG_NET_VENDOR_XILINX is not set
570
CONFIG_PPP=m
571
CONFIG_PPP_BSDCOMP=m
572
CONFIG_PPP_DEFLATE=m
···
829
CONFIG_NTB_PERF=m
830
CONFIG_NTB_TRANSPORT=m
831
CONFIG_PWM=y
832
CONFIG_USB4=y
833
CONFIG_EXT2_FS=y
834
CONFIG_EXT2_FS_XATTR=y
···
895
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
896
CONFIG_CRAMFS=m
897
CONFIG_SQUASHFS=y
898
CONFIG_SQUASHFS_XATTR=y
899
CONFIG_SQUASHFS_LZ4=y
900
CONFIG_SQUASHFS_LZO=y
901
CONFIG_SQUASHFS_XZ=y
902
CONFIG_MINIX_FS=m
903
CONFIG_ROMFS_FS=m
904
CONFIG_PSTORE=m
···
983
CONFIG_SCHEDSTATS=y
984
# CONFIG_DEBUG_PREEMPT is not set
985
# CONFIG_FTRACE is not set
···
14
CONFIG_TASK_DELAY_ACCT=y
15
CONFIG_TASK_XACCT=y
16
CONFIG_TASK_IO_ACCOUNTING=y
17
+
CONFIG_PSI=y
18
+
CONFIG_IKCONFIG=y
19
+
CONFIG_IKCONFIG_PROC=y
20
+
CONFIG_IKHEADERS=y
21
CONFIG_LOG_BUF_SHIFT=18
22
CONFIG_NUMA_BALANCING=y
23
CONFIG_MEMCG=y
···
129
CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
130
CONFIG_IP_PIMSM_V1=y
131
CONFIG_IP_PIMSM_V2=y
132
+
CONFIG_INET_AH=m
133
CONFIG_INET_ESP=m
134
+
CONFIG_INET_ESP_OFFLOAD=m
135
+
CONFIG_INET_ESPINTCP=y
136
+
CONFIG_INET_IPCOMP=m
137
CONFIG_INET_UDP_DIAG=y
138
CONFIG_TCP_CONG_ADVANCED=y
139
CONFIG_TCP_CONG_BBR=m
140
CONFIG_IPV6_ROUTER_PREF=y
141
CONFIG_IPV6_ROUTE_INFO=y
142
+
CONFIG_INET6_AH=m
143
CONFIG_INET6_ESP=m
144
+
CONFIG_INET6_ESP_OFFLOAD=m
145
+
CONFIG_INET6_ESPINTCP=y
146
+
CONFIG_INET6_IPCOMP=m
147
+
CONFIG_IPV6_MULTIPLE_TABLES=y
148
CONFIG_IPV6_MROUTE=y
149
CONFIG_MPTCP=y
150
CONFIG_NETWORK_PHY_TIMESTAMPING=y
···
151
CONFIG_NF_CONNTRACK_TFTP=m
152
CONFIG_NF_CT_NETLINK=m
153
CONFIG_NF_TABLES=m
154
+
CONFIG_NF_TABLES_INET=y
155
+
CONFIG_NFT_CT=m
156
CONFIG_NFT_CONNLIMIT=m
157
CONFIG_NFT_LOG=m
158
CONFIG_NFT_LIMIT=m
···
163
CONFIG_NFT_REJECT=m
164
CONFIG_NFT_COMPAT=m
165
CONFIG_NFT_HASH=m
166
+
CONFIG_NFT_FIB_INET=m
167
CONFIG_NFT_SOCKET=m
168
CONFIG_NFT_OSF=m
169
CONFIG_NFT_TPROXY=m
···
259
CONFIG_IP_NF_ARPFILTER=m
260
CONFIG_IP_NF_ARP_MANGLE=m
261
CONFIG_NF_TABLES_IPV6=y
262
+
CONFIG_NFT_FIB_IPV6=m
263
CONFIG_IP6_NF_IPTABLES=y
264
CONFIG_IP6_NF_MATCH_AH=m
265
CONFIG_IP6_NF_MATCH_EUI64=m
···
279
CONFIG_IP6_NF_TARGET_MASQUERADE=m
280
CONFIG_IP6_NF_TARGET_NPT=m
281
CONFIG_NF_TABLES_BRIDGE=m
282
+
CONFIG_NF_CONNTRACK_BRIDGE=m
283
CONFIG_BRIDGE_NF_EBTABLES=m
284
CONFIG_BRIDGE_EBT_BROUTE=m
285
CONFIG_BRIDGE_EBT_T_FILTER=m
···
549
CONFIG_TXGBE=y
550
# CONFIG_NET_VENDOR_WIZNET is not set
551
# CONFIG_NET_VENDOR_XILINX is not set
552
+
CONFIG_MOTORCOMM_PHY=y
553
CONFIG_PPP=m
554
CONFIG_PPP_BSDCOMP=m
555
CONFIG_PPP_DEFLATE=m
···
810
CONFIG_NTB_PERF=m
811
CONFIG_NTB_TRANSPORT=m
812
CONFIG_PWM=y
813
+
CONFIG_GENERIC_PHY=y
814
CONFIG_USB4=y
815
CONFIG_EXT2_FS=y
816
CONFIG_EXT2_FS_XATTR=y
···
875
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
876
CONFIG_CRAMFS=m
877
CONFIG_SQUASHFS=y
878
+
CONFIG_SQUASHFS_FILE_DIRECT=y
879
+
CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT=y
880
CONFIG_SQUASHFS_XATTR=y
881
CONFIG_SQUASHFS_LZ4=y
882
CONFIG_SQUASHFS_LZO=y
883
CONFIG_SQUASHFS_XZ=y
884
+
CONFIG_SQUASHFS_ZSTD=y
885
CONFIG_MINIX_FS=m
886
CONFIG_ROMFS_FS=m
887
CONFIG_PSTORE=m
···
960
CONFIG_SCHEDSTATS=y
961
# CONFIG_DEBUG_PREEMPT is not set
962
# CONFIG_FTRACE is not set
963
+
CONFIG_UNWINDER_ORC=y
+1
arch/loongarch/include/asm/acpi.h
+1
arch/loongarch/include/asm/acpi.h
+6
arch/loongarch/include/asm/asm-prototypes.h
+6
arch/loongarch/include/asm/asm-prototypes.h
+1
-2
arch/loongarch/include/asm/perf_event.h
+1
-2
arch/loongarch/include/asm/perf_event.h
+6
arch/loongarch/include/asm/smp.h
+6
arch/loongarch/include/asm/smp.h
···
6
#ifndef __ASM_SMP_H
7
#define __ASM_SMP_H
8
9
+
#ifdef CONFIG_SMP
10
+
11
#include <linux/atomic.h>
12
#include <linux/bitops.h>
13
#include <linux/linkage.h>
···
108
loongson_cpu_die(cpu);
109
}
110
#endif
111
+
112
+
#else /* !CONFIG_SMP */
113
+
#define cpu_logical_map(cpu) 0
114
+
#endif /* CONFIG_SMP */
115
116
#endif /* __ASM_SMP_H */
+1
-1
arch/loongarch/kernel/machine_kexec.c
+1
-1
arch/loongarch/kernel/machine_kexec.c
+2
arch/loongarch/lib/Makefile
+2
arch/loongarch/lib/Makefile
+56
arch/loongarch/lib/tishift.S
+56
arch/loongarch/lib/tishift.S
···
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
3
+
#include <asm/asmmacro.h>
4
+
#include <linux/export.h>
5
+
#include <linux/linkage.h>
6
+
7
+
SYM_FUNC_START(__ashlti3)
8
+
srli.d t2, a0, 1
9
+
nor t3, zero, a2
10
+
sll.d t1, a1, a2
11
+
srl.d t2, t2, t3
12
+
andi t0, a2, 64
13
+
sll.d a0, a0, a2
14
+
or t1, t2, t1
15
+
maskeqz a1, a0, t0
16
+
masknez a0, a0, t0
17
+
masknez t0, t1, t0
18
+
or a1, t0, a1
19
+
jr ra
20
+
SYM_FUNC_END(__ashlti3)
21
+
EXPORT_SYMBOL(__ashlti3)
22
+
23
+
SYM_FUNC_START(__ashrti3)
24
+
nor t3, zero, a2
25
+
slli.d t2, a1, 1
26
+
srl.d t1, a0, a2
27
+
sll.d t2, t2, t3
28
+
andi t0, a2, 64
29
+
or t1, t2, t1
30
+
sra.d a2, a1, a2
31
+
srai.d a1, a1, 63
32
+
maskeqz a0, a2, t0
33
+
maskeqz a1, a1, t0
34
+
masknez a2, a2, t0
35
+
masknez t0, t1, t0
36
+
or a1, a1, a2
37
+
or a0, t0, a0
38
+
jr ra
39
+
SYM_FUNC_END(__ashrti3)
40
+
EXPORT_SYMBOL(__ashrti3)
41
+
42
+
SYM_FUNC_START(__lshrti3)
43
+
slli.d t2, a1, 1
44
+
nor t3, zero, a2
45
+
srl.d t1, a0, a2
46
+
sll.d t2, t2, t3
47
+
andi t0, a2, 64
48
+
srl.d a1, a1, a2
49
+
or t1, t2, t1
50
+
maskeqz a0, a1, t0
51
+
masknez a1, a1, t0
52
+
masknez t0, t1, t0
53
+
or a0, t0, a0
54
+
jr ra
55
+
SYM_FUNC_END(__lshrti3)
56
+
EXPORT_SYMBOL(__lshrti3)
+6
-3
arch/loongarch/mm/tlbex.S
+6
-3
arch/loongarch/mm/tlbex.S
···
125
tlb_huge_update_load:
126
#ifdef CONFIG_SMP
127
ll.d ra, t1, 0
128
#endif
129
andi t0, ra, _PAGE_PRESENT
130
beqz t0, nopage_tlb_load
···
137
beqz t0, tlb_huge_update_load
138
ori t0, ra, _PAGE_VALID
139
#else
140
-
rotri.d ra, ra, 64 - (_PAGE_HUGE_SHIFT + 1)
141
ori t0, ra, _PAGE_VALID
142
st.d t0, t1, 0
143
#endif
···
282
tlb_huge_update_store:
283
#ifdef CONFIG_SMP
284
ll.d ra, t1, 0
285
#endif
286
andi t0, ra, _PAGE_PRESENT | _PAGE_WRITE
287
xori t0, t0, _PAGE_PRESENT | _PAGE_WRITE
···
295
beqz t0, tlb_huge_update_store
296
ori t0, ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
297
#else
298
-
rotri.d ra, ra, 64 - (_PAGE_HUGE_SHIFT + 1)
299
ori t0, ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
300
st.d t0, t1, 0
301
#endif
···
440
tlb_huge_update_modify:
441
#ifdef CONFIG_SMP
442
ll.d ra, t1, 0
443
#endif
444
andi t0, ra, _PAGE_WRITE
445
beqz t0, nopage_tlb_modify
···
452
beqz t0, tlb_huge_update_modify
453
ori t0, ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
454
#else
455
-
rotri.d ra, ra, 64 - (_PAGE_HUGE_SHIFT + 1)
456
ori t0, ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
457
st.d t0, t1, 0
458
#endif
···
125
tlb_huge_update_load:
126
#ifdef CONFIG_SMP
127
ll.d ra, t1, 0
128
+
#else
129
+
rotri.d ra, ra, 64 - (_PAGE_HUGE_SHIFT + 1)
130
#endif
131
andi t0, ra, _PAGE_PRESENT
132
beqz t0, nopage_tlb_load
···
135
beqz t0, tlb_huge_update_load
136
ori t0, ra, _PAGE_VALID
137
#else
138
ori t0, ra, _PAGE_VALID
139
st.d t0, t1, 0
140
#endif
···
281
tlb_huge_update_store:
282
#ifdef CONFIG_SMP
283
ll.d ra, t1, 0
284
+
#else
285
+
rotri.d ra, ra, 64 - (_PAGE_HUGE_SHIFT + 1)
286
#endif
287
andi t0, ra, _PAGE_PRESENT | _PAGE_WRITE
288
xori t0, t0, _PAGE_PRESENT | _PAGE_WRITE
···
292
beqz t0, tlb_huge_update_store
293
ori t0, ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
294
#else
295
ori t0, ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
296
st.d t0, t1, 0
297
#endif
···
438
tlb_huge_update_modify:
439
#ifdef CONFIG_SMP
440
ll.d ra, t1, 0
441
+
#else
442
+
rotri.d ra, ra, 64 - (_PAGE_HUGE_SHIFT + 1)
443
#endif
444
andi t0, ra, _PAGE_WRITE
445
beqz t0, nopage_tlb_modify
···
448
beqz t0, tlb_huge_update_modify
449
ori t0, ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
450
#else
451
ori t0, ra, (_PAGE_VALID | _PAGE_DIRTY | _PAGE_MODIFIED)
452
st.d t0, t1, 0
453
#endif
+3
-1
arch/loongarch/power/suspend.c
+3
-1
arch/loongarch/power/suspend.c
···
24
u64 kpgd;
25
u32 pwctl0;
26
u32 pwctl1;
27
};
28
static struct saved_registers saved_regs;
29
···
37
saved_regs.pwctl1 = csr_read32(LOONGARCH_CSR_PWCTL1);
38
saved_regs.ecfg = csr_read32(LOONGARCH_CSR_ECFG);
39
saved_regs.euen = csr_read32(LOONGARCH_CSR_EUEN);
40
41
loongarch_suspend_addr = loongson_sysconf.suspend_addr;
42
}
···
46
{
47
sync_counter();
48
local_flush_tlb_all();
49
-
csr_write64(per_cpu_offset(0), PERCPU_BASE_KS);
50
csr_write64(eentry, LOONGARCH_CSR_EENTRY);
51
csr_write64(eentry, LOONGARCH_CSR_MERRENTRY);
52
csr_write64(tlbrentry, LOONGARCH_CSR_TLBRENTRY);
···
56
csr_write32(saved_regs.pwctl1, LOONGARCH_CSR_PWCTL1);
57
csr_write32(saved_regs.ecfg, LOONGARCH_CSR_ECFG);
58
csr_write32(saved_regs.euen, LOONGARCH_CSR_EUEN);
59
}
60
61
int loongarch_acpi_suspend(void)
···
24
u64 kpgd;
25
u32 pwctl0;
26
u32 pwctl1;
27
+
u64 pcpu_base;
28
};
29
static struct saved_registers saved_regs;
30
···
36
saved_regs.pwctl1 = csr_read32(LOONGARCH_CSR_PWCTL1);
37
saved_regs.ecfg = csr_read32(LOONGARCH_CSR_ECFG);
38
saved_regs.euen = csr_read32(LOONGARCH_CSR_EUEN);
39
+
saved_regs.pcpu_base = csr_read64(PERCPU_BASE_KS);
40
41
loongarch_suspend_addr = loongson_sysconf.suspend_addr;
42
}
···
44
{
45
sync_counter();
46
local_flush_tlb_all();
47
csr_write64(eentry, LOONGARCH_CSR_EENTRY);
48
csr_write64(eentry, LOONGARCH_CSR_MERRENTRY);
49
csr_write64(tlbrentry, LOONGARCH_CSR_TLBRENTRY);
···
55
csr_write32(saved_regs.pwctl1, LOONGARCH_CSR_PWCTL1);
56
csr_write32(saved_regs.ecfg, LOONGARCH_CSR_ECFG);
57
csr_write32(saved_regs.euen, LOONGARCH_CSR_EUEN);
58
+
csr_write64(saved_regs.pcpu_base, PERCPU_BASE_KS);
59
}
60
61
int loongarch_acpi_suspend(void)
+1
-1
rust/Makefile
+1
-1
rust/Makefile
+1
-1
scripts/Makefile
+1
-1
scripts/Makefile
···
12
hostprogs-always-$(CONFIG_RUST_KERNEL_DOCTESTS) += rustdoc_test_builder
13
hostprogs-always-$(CONFIG_RUST_KERNEL_DOCTESTS) += rustdoc_test_gen
14
15
-
ifneq ($(or $(CONFIG_X86_64),$(CONFIG_LOONGARCH)),)
16
always-$(CONFIG_RUST) += target.json
17
filechk_rust_target = $< < include/config/auto.conf
18
+1
-6
scripts/generate_rust_target.rs
+1
-6
scripts/generate_rust_target.rs
···
164
ts.push("llvm-target", "x86_64-linux-gnu");
165
ts.push("target-pointer-width", "64");
166
} else if cfg.has("LOONGARCH") {
167
-
ts.push("arch", "loongarch64");
168
-
ts.push("data-layout", "e-m:e-p:64:64-i64:64-i128:128-n64-S128");
169
-
ts.push("features", "-f,-d");
170
-
ts.push("llvm-target", "loongarch64-linux-gnusf");
171
-
ts.push("llvm-abiname", "lp64s");
172
-
ts.push("target-pointer-width", "64");
173
} else {
174
panic!("Unsupported architecture");
175
}