drm/radeon: consolidate redundant macros and constants

+9 -9

drivers/gpu/drm/radeon/evergreen_cs.c

··· 2639 2639 } 2640 2640 p->idx += pkt.count + 2; 2641 2641 switch (pkt.type) { 2642 - case PACKET_TYPE0: 2642 + case RADEON_PACKET_TYPE0: 2643 2643 r = evergreen_cs_parse_packet0(p, &pkt); 2644 2644 break; 2645 - case PACKET_TYPE2: 2645 + case RADEON_PACKET_TYPE2: 2646 2646 break; 2647 - case PACKET_TYPE3: 2647 + case RADEON_PACKET_TYPE3: 2648 2648 r = evergreen_packet3_check(p, &pkt); 2649 2649 break; 2650 2650 default: ··· 3395 3395 3396 3396 do { 3397 3397 pkt.idx = idx; 3398 - pkt.type = CP_PACKET_GET_TYPE(ib->ptr[idx]); 3399 - pkt.count = CP_PACKET_GET_COUNT(ib->ptr[idx]); 3398 + pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]); 3399 + pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]); 3400 3400 pkt.one_reg_wr = 0; 3401 3401 switch (pkt.type) { 3402 - case PACKET_TYPE0: 3402 + case RADEON_PACKET_TYPE0: 3403 3403 dev_err(rdev->dev, "Packet0 not allowed!\n"); 3404 3404 ret = -EINVAL; 3405 3405 break; 3406 - case PACKET_TYPE2: 3406 + case RADEON_PACKET_TYPE2: 3407 3407 idx += 1; 3408 3408 break; 3409 - case PACKET_TYPE3: 3410 - pkt.opcode = CP_PACKET3_GET_OPCODE(ib->ptr[idx]); 3409 + case RADEON_PACKET_TYPE3: 3410 + pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]); 3411 3411 ret = evergreen_vm_packet3_check(rdev, ib->ptr, &pkt); 3412 3412 idx += pkt.count + 2; 3413 3413 break;

+2 -11

drivers/gpu/drm/radeon/evergreend.h

··· 980 980 /* 981 981 * PM4 982 982 */ 983 - #define PACKET_TYPE0 0 984 - #define PACKET_TYPE1 1 985 - #define PACKET_TYPE2 2 986 - #define PACKET_TYPE3 3 987 - 988 - #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 989 - #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 990 - #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 991 - #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 992 - #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 983 + #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ 993 984 (((reg) >> 2) & 0xFFFF) | \ 994 985 ((n) & 0x3FFF) << 16) 995 986 #define CP_PACKET2 0x80000000 ··· 989 998 990 999 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 991 1000 992 - #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 1001 + #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 993 1002 (((op) & 0xFF) << 8) | \ 994 1003 ((n) & 0x3FFF) << 16) 995 1004

+2 -11

drivers/gpu/drm/radeon/nid.h

··· 474 474 /* 475 475 * PM4 476 476 */ 477 - #define PACKET_TYPE0 0 478 - #define PACKET_TYPE1 1 479 - #define PACKET_TYPE2 2 480 - #define PACKET_TYPE3 3 481 - 482 - #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 483 - #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 484 - #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 485 - #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 486 - #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 477 + #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ 487 478 (((reg) >> 2) & 0xFFFF) | \ 488 479 ((n) & 0x3FFF) << 16) 489 480 #define CP_PACKET2 0x80000000 ··· 483 492 484 493 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 485 494 486 - #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 495 + #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 487 496 (((op) & 0xFF) << 8) | \ 488 497 ((n) & 0x3FFF) << 16) 489 498

+4 -4

drivers/gpu/drm/radeon/r100.c

··· 1410 1410 1411 1411 header = radeon_get_ib_value(p, h_idx); 1412 1412 crtc_id = radeon_get_ib_value(p, h_idx + 5); 1413 - reg = CP_PACKET0_GET_REG(header); 1413 + reg = R100_CP_PACKET0_GET_REG(header); 1414 1414 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); 1415 1415 if (!obj) { 1416 1416 DRM_ERROR("cannot find crtc %d\n", crtc_id); ··· 1997 1997 } 1998 1998 p->idx += pkt.count + 2; 1999 1999 switch (pkt.type) { 2000 - case PACKET_TYPE0: 2000 + case RADEON_PACKET_TYPE0: 2001 2001 if (p->rdev->family >= CHIP_R200) 2002 2002 r = r100_cs_parse_packet0(p, &pkt, 2003 2003 p->rdev->config.r100.reg_safe_bm, ··· 2009 2009 p->rdev->config.r100.reg_safe_bm_size, 2010 2010 &r100_packet0_check); 2011 2011 break; 2012 - case PACKET_TYPE2: 2012 + case RADEON_PACKET_TYPE2: 2013 2013 break; 2014 - case PACKET_TYPE3: 2014 + case RADEON_PACKET_TYPE3: 2015 2015 r = r100_packet3_check(p, &pkt); 2016 2016 break; 2017 2017 default:

-11

drivers/gpu/drm/radeon/r100d.h

··· 64 64 REG_SET(PACKET3_IT_OPCODE, (op)) | \ 65 65 REG_SET(PACKET3_COUNT, (n))) 66 66 67 - #define PACKET_TYPE0 0 68 - #define PACKET_TYPE1 1 69 - #define PACKET_TYPE2 2 70 - #define PACKET_TYPE3 3 71 - 72 - #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 73 - #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 74 - #define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2) 75 - #define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) 76 - #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 77 - 78 67 /* Registers */ 79 68 #define R_0000F0_RBBM_SOFT_RESET 0x0000F0 80 69 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0)

+3 -3

drivers/gpu/drm/radeon/r300.c

··· 1263 1263 } 1264 1264 p->idx += pkt.count + 2; 1265 1265 switch (pkt.type) { 1266 - case PACKET_TYPE0: 1266 + case RADEON_PACKET_TYPE0: 1267 1267 r = r100_cs_parse_packet0(p, &pkt, 1268 1268 p->rdev->config.r300.reg_safe_bm, 1269 1269 p->rdev->config.r300.reg_safe_bm_size, 1270 1270 &r300_packet0_check); 1271 1271 break; 1272 - case PACKET_TYPE2: 1272 + case RADEON_PACKET_TYPE2: 1273 1273 break; 1274 - case PACKET_TYPE3: 1274 + case RADEON_PACKET_TYPE3: 1275 1275 r = r300_packet3_check(p, &pkt); 1276 1276 break; 1277 1277 default:

-11

drivers/gpu/drm/radeon/r300d.h

··· 65 65 REG_SET(PACKET3_IT_OPCODE, (op)) | \ 66 66 REG_SET(PACKET3_COUNT, (n))) 67 67 68 - #define PACKET_TYPE0 0 69 - #define PACKET_TYPE1 1 70 - #define PACKET_TYPE2 2 71 - #define PACKET_TYPE3 3 72 - 73 - #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 74 - #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 75 - #define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2) 76 - #define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) 77 - #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 78 - 79 68 /* Registers */ 80 69 #define R_000148_MC_FB_LOCATION 0x000148 81 70 #define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0)

+5 -5

drivers/gpu/drm/radeon/r600_cs.c

··· 839 839 return r; 840 840 841 841 /* check its a WAIT_REG_MEM */ 842 - if (wait_reg_mem.type != PACKET_TYPE3 || 842 + if (wait_reg_mem.type != RADEON_PACKET_TYPE3 || 843 843 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) { 844 844 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n"); 845 845 return -EINVAL; ··· 882 882 883 883 header = radeon_get_ib_value(p, h_idx); 884 884 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1); 885 - reg = CP_PACKET0_GET_REG(header); 885 + reg = R600_CP_PACKET0_GET_REG(header); 886 886 887 887 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC); 888 888 if (!obj) { ··· 2282 2282 } 2283 2283 p->idx += pkt.count + 2; 2284 2284 switch (pkt.type) { 2285 - case PACKET_TYPE0: 2285 + case RADEON_PACKET_TYPE0: 2286 2286 r = r600_cs_parse_packet0(p, &pkt); 2287 2287 break; 2288 - case PACKET_TYPE2: 2288 + case RADEON_PACKET_TYPE2: 2289 2289 break; 2290 - case PACKET_TYPE3: 2290 + case RADEON_PACKET_TYPE3: 2291 2291 r = r600_packet3_check(p, &pkt); 2292 2292 break; 2293 2293 default:

+2 -11

drivers/gpu/drm/radeon/r600d.h

··· 1143 1143 /* 1144 1144 * PM4 1145 1145 */ 1146 - #define PACKET_TYPE0 0 1147 - #define PACKET_TYPE1 1 1148 - #define PACKET_TYPE2 2 1149 - #define PACKET_TYPE3 3 1150 - 1151 - #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 1152 - #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 1153 - #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 1154 - #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 1155 - #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 1146 + #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ 1156 1147 (((reg) >> 2) & 0xFFFF) | \ 1157 1148 ((n) & 0x3FFF) << 16) 1158 - #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 1149 + #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 1159 1150 (((op) & 0xFF) << 8) | \ 1160 1151 ((n) & 0x3FFF) << 16) 1161 1152

-11

drivers/gpu/drm/radeon/rv515d.h

··· 205 205 REG_SET(PACKET3_IT_OPCODE, (op)) | \ 206 206 REG_SET(PACKET3_COUNT, (n))) 207 207 208 - #define PACKET_TYPE0 0 209 - #define PACKET_TYPE1 1 210 - #define PACKET_TYPE2 2 211 - #define PACKET_TYPE3 3 212 - 213 - #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 214 - #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 215 - #define CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2) 216 - #define CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1) 217 - #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 218 - 219 208 /* Registers */ 220 209 #define R_0000F0_RBBM_SOFT_RESET 0x0000F0 221 210 #define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0)

+6 -6

drivers/gpu/drm/radeon/si.c

··· 2855 2855 2856 2856 do { 2857 2857 pkt.idx = idx; 2858 - pkt.type = CP_PACKET_GET_TYPE(ib->ptr[idx]); 2859 - pkt.count = CP_PACKET_GET_COUNT(ib->ptr[idx]); 2858 + pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]); 2859 + pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]); 2860 2860 pkt.one_reg_wr = 0; 2861 2861 switch (pkt.type) { 2862 - case PACKET_TYPE0: 2862 + case RADEON_PACKET_TYPE0: 2863 2863 dev_err(rdev->dev, "Packet0 not allowed!\n"); 2864 2864 ret = -EINVAL; 2865 2865 break; 2866 - case PACKET_TYPE2: 2866 + case RADEON_PACKET_TYPE2: 2867 2867 idx += 1; 2868 2868 break; 2869 - case PACKET_TYPE3: 2870 - pkt.opcode = CP_PACKET3_GET_OPCODE(ib->ptr[idx]); 2869 + case RADEON_PACKET_TYPE3: 2870 + pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]); 2871 2871 if (ib->is_const_ib) 2872 2872 ret = si_vm_packet3_ce_check(rdev, ib->ptr, &pkt); 2873 2873 else {

+2 -11

drivers/gpu/drm/radeon/sid.h

··· 783 783 /* 784 784 * PM4 785 785 */ 786 - #define PACKET_TYPE0 0 787 - #define PACKET_TYPE1 1 788 - #define PACKET_TYPE2 2 789 - #define PACKET_TYPE3 3 790 - 791 - #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 792 - #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 793 - #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 794 - #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 795 - #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 786 + #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ 796 787 (((reg) >> 2) & 0xFFFF) | \ 797 788 ((n) & 0x3FFF) << 16) 798 789 #define CP_PACKET2 0x80000000 ··· 792 801 793 802 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 794 803 795 - #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 804 + #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 796 805 (((op) & 0xFF) << 8) | \ 797 806 ((n) & 0x3FFF) << 16) 798 807