drm/radeon: use common next_reloc function

+40 -89

drivers/gpu/drm/radeon/evergreen_cs.c

··· 36 36 37 37 int r600_dma_cs_next_reloc(struct radeon_cs_parser *p, 38 38 struct radeon_cs_reloc **cs_reloc); 39 - static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p, 40 - struct radeon_cs_reloc **cs_reloc); 41 - 42 39 struct evergreen_cs_track { 43 40 u32 group_size; 44 41 u32 nbanks; ··· 1006 1009 } 1007 1010 1008 1011 /** 1009 - * evergreen_cs_packet_next_reloc() - parse next packet which should be reloc packet3 1010 - * @parser: parser structure holding parsing context. 1011 - * @data: pointer to relocation data 1012 - * @offset_start: starting offset 1013 - * @offset_mask: offset mask (to align start offset on) 1014 - * @reloc: reloc informations 1015 - * 1016 - * Check next packet is relocation packet3, do bo validation and compute 1017 - * GPU offset using the provided start. 1018 - **/ 1019 - static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p, 1020 - struct radeon_cs_reloc **cs_reloc) 1021 - { 1022 - struct radeon_cs_chunk *relocs_chunk; 1023 - struct radeon_cs_packet p3reloc; 1024 - unsigned idx; 1025 - int r; 1026 - 1027 - if (p->chunk_relocs_idx == -1) { 1028 - DRM_ERROR("No relocation chunk !\n"); 1029 - return -EINVAL; 1030 - } 1031 - *cs_reloc = NULL; 1032 - relocs_chunk = &p->chunks[p->chunk_relocs_idx]; 1033 - r = radeon_cs_packet_parse(p, &p3reloc, p->idx); 1034 - if (r) { 1035 - return r; 1036 - } 1037 - p->idx += p3reloc.count + 2; 1038 - if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { 1039 - DRM_ERROR("No packet3 for relocation for packet at %d.\n", 1040 - p3reloc.idx); 1041 - return -EINVAL; 1042 - } 1043 - idx = radeon_get_ib_value(p, p3reloc.idx + 1); 1044 - if (idx >= relocs_chunk->length_dw) { 1045 - DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", 1046 - idx, relocs_chunk->length_dw); 1047 - return -EINVAL; 1048 - } 1049 - /* FIXME: we assume reloc size is 4 dwords */ 1050 - *cs_reloc = p->relocs_ptr[(idx / 4)]; 1051 - return 0; 1052 - } 1053 - 1054 - /** 1055 1012 * evergreen_cs_packet_parse_vline() - parse userspace VLINE packet 1056 1013 * @parser: parser structure holding parsing context. 1057 1014 * ··· 1156 1205 case SQ_LSTMP_RING_BASE: 1157 1206 case SQ_PSTMP_RING_BASE: 1158 1207 case SQ_VSTMP_RING_BASE: 1159 - r = evergreen_cs_packet_next_reloc(p, &reloc); 1208 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1160 1209 if (r) { 1161 1210 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1162 1211 "0x%04X\n", reg); ··· 1185 1234 case DB_Z_INFO: 1186 1235 track->db_z_info = radeon_get_ib_value(p, idx); 1187 1236 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1188 - r = evergreen_cs_packet_next_reloc(p, &reloc); 1237 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1189 1238 if (r) { 1190 1239 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1191 1240 "0x%04X\n", reg); ··· 1227 1276 track->db_dirty = true; 1228 1277 break; 1229 1278 case DB_Z_READ_BASE: 1230 - r = evergreen_cs_packet_next_reloc(p, &reloc); 1279 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1231 1280 if (r) { 1232 1281 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1233 1282 "0x%04X\n", reg); ··· 1239 1288 track->db_dirty = true; 1240 1289 break; 1241 1290 case DB_Z_WRITE_BASE: 1242 - r = evergreen_cs_packet_next_reloc(p, &reloc); 1291 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1243 1292 if (r) { 1244 1293 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1245 1294 "0x%04X\n", reg); ··· 1251 1300 track->db_dirty = true; 1252 1301 break; 1253 1302 case DB_STENCIL_READ_BASE: 1254 - r = evergreen_cs_packet_next_reloc(p, &reloc); 1303 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1255 1304 if (r) { 1256 1305 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1257 1306 "0x%04X\n", reg); ··· 1263 1312 track->db_dirty = true; 1264 1313 break; 1265 1314 case DB_STENCIL_WRITE_BASE: 1266 - r = evergreen_cs_packet_next_reloc(p, &reloc); 1315 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1267 1316 if (r) { 1268 1317 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1269 1318 "0x%04X\n", reg); ··· 1286 1335 case VGT_STRMOUT_BUFFER_BASE_1: 1287 1336 case VGT_STRMOUT_BUFFER_BASE_2: 1288 1337 case VGT_STRMOUT_BUFFER_BASE_3: 1289 - r = evergreen_cs_packet_next_reloc(p, &reloc); 1338 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1290 1339 if (r) { 1291 1340 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1292 1341 "0x%04X\n", reg); ··· 1308 1357 track->streamout_dirty = true; 1309 1358 break; 1310 1359 case CP_COHER_BASE: 1311 - r = evergreen_cs_packet_next_reloc(p, &reloc); 1360 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1312 1361 if (r) { 1313 1362 dev_warn(p->dev, "missing reloc for CP_COHER_BASE " 1314 1363 "0x%04X\n", reg); ··· 1372 1421 tmp = (reg - CB_COLOR0_INFO) / 0x3c; 1373 1422 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); 1374 1423 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1375 - r = evergreen_cs_packet_next_reloc(p, &reloc); 1424 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1376 1425 if (r) { 1377 1426 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1378 1427 "0x%04X\n", reg); ··· 1390 1439 tmp = ((reg - CB_COLOR8_INFO) / 0x1c) + 8; 1391 1440 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); 1392 1441 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1393 - r = evergreen_cs_packet_next_reloc(p, &reloc); 1442 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1394 1443 if (r) { 1395 1444 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1396 1445 "0x%04X\n", reg); ··· 1451 1500 case CB_COLOR5_ATTRIB: 1452 1501 case CB_COLOR6_ATTRIB: 1453 1502 case CB_COLOR7_ATTRIB: 1454 - r = evergreen_cs_packet_next_reloc(p, &reloc); 1503 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1455 1504 if (r) { 1456 1505 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1457 1506 "0x%04X\n", reg); ··· 1479 1528 case CB_COLOR9_ATTRIB: 1480 1529 case CB_COLOR10_ATTRIB: 1481 1530 case CB_COLOR11_ATTRIB: 1482 - r = evergreen_cs_packet_next_reloc(p, &reloc); 1531 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1483 1532 if (r) { 1484 1533 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1485 1534 "0x%04X\n", reg); ··· 1512 1561 case CB_COLOR6_FMASK: 1513 1562 case CB_COLOR7_FMASK: 1514 1563 tmp = (reg - CB_COLOR0_FMASK) / 0x3c; 1515 - r = evergreen_cs_packet_next_reloc(p, &reloc); 1564 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1516 1565 if (r) { 1517 1566 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); 1518 1567 return -EINVAL; ··· 1529 1578 case CB_COLOR6_CMASK: 1530 1579 case CB_COLOR7_CMASK: 1531 1580 tmp = (reg - CB_COLOR0_CMASK) / 0x3c; 1532 - r = evergreen_cs_packet_next_reloc(p, &reloc); 1581 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1533 1582 if (r) { 1534 1583 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); 1535 1584 return -EINVAL; ··· 1567 1616 case CB_COLOR5_BASE: 1568 1617 case CB_COLOR6_BASE: 1569 1618 case CB_COLOR7_BASE: 1570 - r = evergreen_cs_packet_next_reloc(p, &reloc); 1619 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1571 1620 if (r) { 1572 1621 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1573 1622 "0x%04X\n", reg); ··· 1583 1632 case CB_COLOR9_BASE: 1584 1633 case CB_COLOR10_BASE: 1585 1634 case CB_COLOR11_BASE: 1586 - r = evergreen_cs_packet_next_reloc(p, &reloc); 1635 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1587 1636 if (r) { 1588 1637 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1589 1638 "0x%04X\n", reg); ··· 1596 1645 track->cb_dirty = true; 1597 1646 break; 1598 1647 case DB_HTILE_DATA_BASE: 1599 - r = evergreen_cs_packet_next_reloc(p, &reloc); 1648 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1600 1649 if (r) { 1601 1650 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1602 1651 "0x%04X\n", reg); ··· 1714 1763 case SQ_ALU_CONST_CACHE_LS_13: 1715 1764 case SQ_ALU_CONST_CACHE_LS_14: 1716 1765 case SQ_ALU_CONST_CACHE_LS_15: 1717 - r = evergreen_cs_packet_next_reloc(p, &reloc); 1766 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1718 1767 if (r) { 1719 1768 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1720 1769 "0x%04X\n", reg); ··· 1728 1777 "0x%04X\n", reg); 1729 1778 return -EINVAL; 1730 1779 } 1731 - r = evergreen_cs_packet_next_reloc(p, &reloc); 1780 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1732 1781 if (r) { 1733 1782 dev_warn(p->dev, "bad SET_CONFIG_REG " 1734 1783 "0x%04X\n", reg); ··· 1742 1791 "0x%04X\n", reg); 1743 1792 return -EINVAL; 1744 1793 } 1745 - r = evergreen_cs_packet_next_reloc(p, &reloc); 1794 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1746 1795 if (r) { 1747 1796 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1748 1797 "0x%04X\n", reg); ··· 1827 1876 return -EINVAL; 1828 1877 } 1829 1878 1830 - r = evergreen_cs_packet_next_reloc(p, &reloc); 1879 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1831 1880 if (r) { 1832 1881 DRM_ERROR("bad SET PREDICATION\n"); 1833 1882 return -EINVAL; ··· 1873 1922 DRM_ERROR("bad INDEX_BASE\n"); 1874 1923 return -EINVAL; 1875 1924 } 1876 - r = evergreen_cs_packet_next_reloc(p, &reloc); 1925 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1877 1926 if (r) { 1878 1927 DRM_ERROR("bad INDEX_BASE\n"); 1879 1928 return -EINVAL; ··· 1900 1949 DRM_ERROR("bad DRAW_INDEX\n"); 1901 1950 return -EINVAL; 1902 1951 } 1903 - r = evergreen_cs_packet_next_reloc(p, &reloc); 1952 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1904 1953 if (r) { 1905 1954 DRM_ERROR("bad DRAW_INDEX\n"); 1906 1955 return -EINVAL; ··· 1928 1977 DRM_ERROR("bad DRAW_INDEX_2\n"); 1929 1978 return -EINVAL; 1930 1979 } 1931 - r = evergreen_cs_packet_next_reloc(p, &reloc); 1980 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1932 1981 if (r) { 1933 1982 DRM_ERROR("bad DRAW_INDEX_2\n"); 1934 1983 return -EINVAL; ··· 2019 2068 DRM_ERROR("bad DISPATCH_INDIRECT\n"); 2020 2069 return -EINVAL; 2021 2070 } 2022 - r = evergreen_cs_packet_next_reloc(p, &reloc); 2071 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2023 2072 if (r) { 2024 2073 DRM_ERROR("bad DISPATCH_INDIRECT\n"); 2025 2074 return -EINVAL; ··· 2040 2089 if (idx_value & 0x10) { 2041 2090 uint64_t offset; 2042 2091 2043 - r = evergreen_cs_packet_next_reloc(p, &reloc); 2092 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2044 2093 if (r) { 2045 2094 DRM_ERROR("bad WAIT_REG_MEM\n"); 2046 2095 return -EINVAL; ··· 2094 2143 } 2095 2144 /* src address space is memory */ 2096 2145 if (((info & 0x60000000) >> 29) == 0) { 2097 - r = evergreen_cs_packet_next_reloc(p, &reloc); 2146 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2098 2147 if (r) { 2099 2148 DRM_ERROR("bad CP DMA SRC\n"); 2100 2149 return -EINVAL; ··· 2132 2181 return -EINVAL; 2133 2182 } 2134 2183 if (((info & 0x00300000) >> 20) == 0) { 2135 - r = evergreen_cs_packet_next_reloc(p, &reloc); 2184 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2136 2185 if (r) { 2137 2186 DRM_ERROR("bad CP DMA DST\n"); 2138 2187 return -EINVAL; ··· 2166 2215 /* 0xffffffff/0x0 is flush all cache flag */ 2167 2216 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff || 2168 2217 radeon_get_ib_value(p, idx + 2) != 0) { 2169 - r = evergreen_cs_packet_next_reloc(p, &reloc); 2218 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2170 2219 if (r) { 2171 2220 DRM_ERROR("bad SURFACE_SYNC\n"); 2172 2221 return -EINVAL; ··· 2182 2231 if (pkt->count) { 2183 2232 uint64_t offset; 2184 2233 2185 - r = evergreen_cs_packet_next_reloc(p, &reloc); 2234 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2186 2235 if (r) { 2187 2236 DRM_ERROR("bad EVENT_WRITE\n"); 2188 2237 return -EINVAL; ··· 2203 2252 DRM_ERROR("bad EVENT_WRITE_EOP\n"); 2204 2253 return -EINVAL; 2205 2254 } 2206 - r = evergreen_cs_packet_next_reloc(p, &reloc); 2255 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2207 2256 if (r) { 2208 2257 DRM_ERROR("bad EVENT_WRITE_EOP\n"); 2209 2258 return -EINVAL; ··· 2225 2274 DRM_ERROR("bad EVENT_WRITE_EOS\n"); 2226 2275 return -EINVAL; 2227 2276 } 2228 - r = evergreen_cs_packet_next_reloc(p, &reloc); 2277 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2229 2278 if (r) { 2230 2279 DRM_ERROR("bad EVENT_WRITE_EOS\n"); 2231 2280 return -EINVAL; ··· 2292 2341 switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) { 2293 2342 case SQ_TEX_VTX_VALID_TEXTURE: 2294 2343 /* tex base */ 2295 - r = evergreen_cs_packet_next_reloc(p, &reloc); 2344 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2296 2345 if (r) { 2297 2346 DRM_ERROR("bad SET_RESOURCE (tex)\n"); 2298 2347 return -EINVAL; ··· 2329 2378 moffset = 0; 2330 2379 mipmap = NULL; 2331 2380 } else { 2332 - r = evergreen_cs_packet_next_reloc(p, &reloc); 2381 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2333 2382 if (r) { 2334 2383 DRM_ERROR("bad SET_RESOURCE (tex)\n"); 2335 2384 return -EINVAL; ··· 2348 2397 { 2349 2398 uint64_t offset64; 2350 2399 /* vtx base */ 2351 - r = evergreen_cs_packet_next_reloc(p, &reloc); 2400 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2352 2401 if (r) { 2353 2402 DRM_ERROR("bad SET_RESOURCE (vtx)\n"); 2354 2403 return -EINVAL; ··· 2430 2479 /* Updating memory at DST_ADDRESS. */ 2431 2480 if (idx_value & 0x1) { 2432 2481 u64 offset; 2433 - r = evergreen_cs_packet_next_reloc(p, &reloc); 2482 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2434 2483 if (r) { 2435 2484 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n"); 2436 2485 return -EINVAL; ··· 2449 2498 /* Reading data from SRC_ADDRESS. */ 2450 2499 if (((idx_value >> 1) & 0x3) == 2) { 2451 2500 u64 offset; 2452 - r = evergreen_cs_packet_next_reloc(p, &reloc); 2501 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2453 2502 if (r) { 2454 2503 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n"); 2455 2504 return -EINVAL; ··· 2474 2523 DRM_ERROR("bad MEM_WRITE (invalid count)\n"); 2475 2524 return -EINVAL; 2476 2525 } 2477 - r = evergreen_cs_packet_next_reloc(p, &reloc); 2526 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2478 2527 if (r) { 2479 2528 DRM_ERROR("bad MEM_WRITE (missing reloc)\n"); 2480 2529 return -EINVAL; ··· 2503 2552 if (idx_value & 0x1) { 2504 2553 u64 offset; 2505 2554 /* SRC is memory. */ 2506 - r = evergreen_cs_packet_next_reloc(p, &reloc); 2555 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2507 2556 if (r) { 2508 2557 DRM_ERROR("bad COPY_DW (missing src reloc)\n"); 2509 2558 return -EINVAL; ··· 2527 2576 if (idx_value & 0x2) { 2528 2577 u64 offset; 2529 2578 /* DST is memory. */ 2530 - r = evergreen_cs_packet_next_reloc(p, &reloc); 2579 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 2531 2580 if (r) { 2532 2581 DRM_ERROR("bad COPY_DW (missing dst reloc)\n"); 2533 2582 return -EINVAL;

+14 -62

drivers/gpu/drm/radeon/r100.c

··· 1215 1215 struct radeon_cs_reloc *reloc; 1216 1216 u32 value; 1217 1217 1218 - r = r100_cs_packet_next_reloc(p, &reloc); 1218 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1219 1219 if (r) { 1220 1220 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1221 1221 idx, reg); ··· 1268 1268 } 1269 1269 track->num_arrays = c; 1270 1270 for (i = 0; i < (c - 1); i+=2, idx+=3) { 1271 - r = r100_cs_packet_next_reloc(p, &reloc); 1271 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1272 1272 if (r) { 1273 1273 DRM_ERROR("No reloc for packet3 %d\n", 1274 1274 pkt->opcode); ··· 1281 1281 track->arrays[i + 0].esize = idx_value >> 8; 1282 1282 track->arrays[i + 0].robj = reloc->robj; 1283 1283 track->arrays[i + 0].esize &= 0x7F; 1284 - r = r100_cs_packet_next_reloc(p, &reloc); 1284 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1285 1285 if (r) { 1286 1286 DRM_ERROR("No reloc for packet3 %d\n", 1287 1287 pkt->opcode); ··· 1294 1294 track->arrays[i + 1].esize &= 0x7F; 1295 1295 } 1296 1296 if (c & 1) { 1297 - r = r100_cs_packet_next_reloc(p, &reloc); 1297 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1298 1298 if (r) { 1299 1299 DRM_ERROR("No reloc for packet3 %d\n", 1300 1300 pkt->opcode); ··· 1445 1445 return 0; 1446 1446 } 1447 1447 1448 - /** 1449 - * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3 1450 - * @parser: parser structure holding parsing context. 1451 - * @data: pointer to relocation data 1452 - * @offset_start: starting offset 1453 - * @offset_mask: offset mask (to align start offset on) 1454 - * @reloc: reloc informations 1455 - * 1456 - * Check next packet is relocation packet3, do bo validation and compute 1457 - * GPU offset using the provided start. 1458 - **/ 1459 - int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, 1460 - struct radeon_cs_reloc **cs_reloc) 1461 - { 1462 - struct radeon_cs_chunk *relocs_chunk; 1463 - struct radeon_cs_packet p3reloc; 1464 - unsigned idx; 1465 - int r; 1466 - 1467 - if (p->chunk_relocs_idx == -1) { 1468 - DRM_ERROR("No relocation chunk !\n"); 1469 - return -EINVAL; 1470 - } 1471 - *cs_reloc = NULL; 1472 - relocs_chunk = &p->chunks[p->chunk_relocs_idx]; 1473 - r = radeon_cs_packet_parse(p, &p3reloc, p->idx); 1474 - if (r) { 1475 - return r; 1476 - } 1477 - p->idx += p3reloc.count + 2; 1478 - if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { 1479 - DRM_ERROR("No packet3 for relocation for packet at %d.\n", 1480 - p3reloc.idx); 1481 - radeon_cs_dump_packet(p, &p3reloc); 1482 - return -EINVAL; 1483 - } 1484 - idx = radeon_get_ib_value(p, p3reloc.idx + 1); 1485 - if (idx >= relocs_chunk->length_dw) { 1486 - DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", 1487 - idx, relocs_chunk->length_dw); 1488 - radeon_cs_dump_packet(p, &p3reloc); 1489 - return -EINVAL; 1490 - } 1491 - /* FIXME: we assume reloc size is 4 dwords */ 1492 - *cs_reloc = p->relocs_ptr[(idx / 4)]; 1493 - return 0; 1494 - } 1495 - 1496 1448 static int r100_get_vtx_size(uint32_t vtx_fmt) 1497 1449 { 1498 1450 int vtx_size; ··· 1535 1583 return r; 1536 1584 break; 1537 1585 case RADEON_RB3D_DEPTHOFFSET: 1538 - r = r100_cs_packet_next_reloc(p, &reloc); 1586 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1539 1587 if (r) { 1540 1588 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1541 1589 idx, reg); ··· 1548 1596 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1549 1597 break; 1550 1598 case RADEON_RB3D_COLOROFFSET: 1551 - r = r100_cs_packet_next_reloc(p, &reloc); 1599 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1552 1600 if (r) { 1553 1601 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1554 1602 idx, reg); ··· 1564 1612 case RADEON_PP_TXOFFSET_1: 1565 1613 case RADEON_PP_TXOFFSET_2: 1566 1614 i = (reg - RADEON_PP_TXOFFSET_0) / 24; 1567 - r = r100_cs_packet_next_reloc(p, &reloc); 1615 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1568 1616 if (r) { 1569 1617 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1570 1618 idx, reg); ··· 1591 1639 case RADEON_PP_CUBIC_OFFSET_T0_3: 1592 1640 case RADEON_PP_CUBIC_OFFSET_T0_4: 1593 1641 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4; 1594 - r = r100_cs_packet_next_reloc(p, &reloc); 1642 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1595 1643 if (r) { 1596 1644 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1597 1645 idx, reg); ··· 1609 1657 case RADEON_PP_CUBIC_OFFSET_T1_3: 1610 1658 case RADEON_PP_CUBIC_OFFSET_T1_4: 1611 1659 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4; 1612 - r = r100_cs_packet_next_reloc(p, &reloc); 1660 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1613 1661 if (r) { 1614 1662 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1615 1663 idx, reg); ··· 1627 1675 case RADEON_PP_CUBIC_OFFSET_T2_3: 1628 1676 case RADEON_PP_CUBIC_OFFSET_T2_4: 1629 1677 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4; 1630 - r = r100_cs_packet_next_reloc(p, &reloc); 1678 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1631 1679 if (r) { 1632 1680 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1633 1681 idx, reg); ··· 1645 1693 track->zb_dirty = true; 1646 1694 break; 1647 1695 case RADEON_RB3D_COLORPITCH: 1648 - r = r100_cs_packet_next_reloc(p, &reloc); 1696 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1649 1697 if (r) { 1650 1698 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1651 1699 idx, reg); ··· 1716 1764 track->zb_dirty = true; 1717 1765 break; 1718 1766 case RADEON_RB3D_ZPASS_ADDR: 1719 - r = r100_cs_packet_next_reloc(p, &reloc); 1767 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1720 1768 if (r) { 1721 1769 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1722 1770 idx, reg); ··· 1877 1925 return r; 1878 1926 break; 1879 1927 case PACKET3_INDX_BUFFER: 1880 - r = r100_cs_packet_next_reloc(p, &reloc); 1928 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1881 1929 if (r) { 1882 1930 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1883 1931 radeon_cs_dump_packet(p, pkt); ··· 1891 1939 break; 1892 1940 case 0x23: 1893 1941 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */ 1894 - r = r100_cs_packet_next_reloc(p, &reloc); 1942 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1895 1943 if (r) { 1896 1944 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1897 1945 radeon_cs_dump_packet(p, pkt);

-2

drivers/gpu/drm/radeon/r100_track.h

··· 81 81 82 82 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track); 83 83 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track); 84 - int r100_cs_packet_next_reloc(struct radeon_cs_parser *p, 85 - struct radeon_cs_reloc **cs_reloc); 86 84 87 85 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p); 88 86

+6 -6

drivers/gpu/drm/radeon/r200.c

··· 175 175 return r; 176 176 break; 177 177 case RADEON_RB3D_DEPTHOFFSET: 178 - r = r100_cs_packet_next_reloc(p, &reloc); 178 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 179 179 if (r) { 180 180 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 181 181 idx, reg); ··· 188 188 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 189 189 break; 190 190 case RADEON_RB3D_COLOROFFSET: 191 - r = r100_cs_packet_next_reloc(p, &reloc); 191 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 192 192 if (r) { 193 193 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 194 194 idx, reg); ··· 207 207 case R200_PP_TXOFFSET_4: 208 208 case R200_PP_TXOFFSET_5: 209 209 i = (reg - R200_PP_TXOFFSET_0) / 24; 210 - r = r100_cs_packet_next_reloc(p, &reloc); 210 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 211 211 if (r) { 212 212 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 213 213 idx, reg); ··· 260 260 case R200_PP_CUBIC_OFFSET_F5_5: 261 261 i = (reg - R200_PP_TXOFFSET_0) / 24; 262 262 face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4; 263 - r = r100_cs_packet_next_reloc(p, &reloc); 263 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 264 264 if (r) { 265 265 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 266 266 idx, reg); ··· 278 278 track->zb_dirty = true; 279 279 break; 280 280 case RADEON_RB3D_COLORPITCH: 281 - r = r100_cs_packet_next_reloc(p, &reloc); 281 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 282 282 if (r) { 283 283 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 284 284 idx, reg); ··· 355 355 track->zb_dirty = true; 356 356 break; 357 357 case RADEON_RB3D_ZPASS_ADDR: 358 - r = r100_cs_packet_next_reloc(p, &reloc); 358 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 359 359 if (r) { 360 360 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 361 361 idx, reg);

+8 -8

drivers/gpu/drm/radeon/r300.c

··· 630 630 case R300_RB3D_COLOROFFSET2: 631 631 case R300_RB3D_COLOROFFSET3: 632 632 i = (reg - R300_RB3D_COLOROFFSET0) >> 2; 633 - r = r100_cs_packet_next_reloc(p, &reloc); 633 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 634 634 if (r) { 635 635 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 636 636 idx, reg); ··· 643 643 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 644 644 break; 645 645 case R300_ZB_DEPTHOFFSET: 646 - r = r100_cs_packet_next_reloc(p, &reloc); 646 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 647 647 if (r) { 648 648 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 649 649 idx, reg); ··· 672 672 case R300_TX_OFFSET_0+56: 673 673 case R300_TX_OFFSET_0+60: 674 674 i = (reg - R300_TX_OFFSET_0) >> 2; 675 - r = r100_cs_packet_next_reloc(p, &reloc); 675 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 676 676 if (r) { 677 677 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 678 678 idx, reg); ··· 745 745 /* RB3D_COLORPITCH2 */ 746 746 /* RB3D_COLORPITCH3 */ 747 747 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 748 - r = r100_cs_packet_next_reloc(p, &reloc); 748 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 749 749 if (r) { 750 750 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 751 751 idx, reg); ··· 830 830 case 0x4F24: 831 831 /* ZB_DEPTHPITCH */ 832 832 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 833 - r = r100_cs_packet_next_reloc(p, &reloc); 833 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 834 834 if (r) { 835 835 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 836 836 idx, reg); ··· 1045 1045 track->tex_dirty = true; 1046 1046 break; 1047 1047 case R300_ZB_ZPASS_ADDR: 1048 - r = r100_cs_packet_next_reloc(p, &reloc); 1048 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1049 1049 if (r) { 1050 1050 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1051 1051 idx, reg); ··· 1087 1087 track->cb_dirty = true; 1088 1088 break; 1089 1089 case R300_RB3D_AARESOLVE_OFFSET: 1090 - r = r100_cs_packet_next_reloc(p, &reloc); 1090 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1091 1091 if (r) { 1092 1092 DRM_ERROR("No reloc for ib[%d]=0x%04X\n", 1093 1093 idx, reg); ··· 1156 1156 return r; 1157 1157 break; 1158 1158 case PACKET3_INDX_BUFFER: 1159 - r = r100_cs_packet_next_reloc(p, &reloc); 1159 + r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1160 1160 if (r) { 1161 1161 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode); 1162 1162 radeon_cs_dump_packet(p, pkt);

+30 -128

drivers/gpu/drm/radeon/r600_cs.c

··· 31 31 #include "r600d.h" 32 32 #include "r600_reg_safe.h" 33 33 34 - static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p, 35 - struct radeon_cs_reloc **cs_reloc); 36 - static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p, 37 - struct radeon_cs_reloc **cs_reloc); 38 - typedef int (*next_reloc_t)(struct radeon_cs_parser*, struct radeon_cs_reloc**); 39 - static next_reloc_t r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_mm; 34 + static int r600_nomm; 40 35 extern void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size); 41 36 42 37 ··· 779 784 } 780 785 781 786 /** 782 - * r600_cs_packet_next_reloc_mm() - parse next packet which should be reloc packet3 783 - * @parser: parser structure holding parsing context. 784 - * @data: pointer to relocation data 785 - * @offset_start: starting offset 786 - * @offset_mask: offset mask (to align start offset on) 787 - * @reloc: reloc informations 788 - * 789 - * Check next packet is relocation packet3, do bo validation and compute 790 - * GPU offset using the provided start. 791 - **/ 792 - static int r600_cs_packet_next_reloc_mm(struct radeon_cs_parser *p, 793 - struct radeon_cs_reloc **cs_reloc) 794 - { 795 - struct radeon_cs_chunk *relocs_chunk; 796 - struct radeon_cs_packet p3reloc; 797 - unsigned idx; 798 - int r; 799 - 800 - if (p->chunk_relocs_idx == -1) { 801 - DRM_ERROR("No relocation chunk !\n"); 802 - return -EINVAL; 803 - } 804 - *cs_reloc = NULL; 805 - relocs_chunk = &p->chunks[p->chunk_relocs_idx]; 806 - r = radeon_cs_packet_parse(p, &p3reloc, p->idx); 807 - if (r) { 808 - return r; 809 - } 810 - p->idx += p3reloc.count + 2; 811 - if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { 812 - DRM_ERROR("No packet3 for relocation for packet at %d.\n", 813 - p3reloc.idx); 814 - return -EINVAL; 815 - } 816 - idx = radeon_get_ib_value(p, p3reloc.idx + 1); 817 - if (idx >= relocs_chunk->length_dw) { 818 - DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", 819 - idx, relocs_chunk->length_dw); 820 - return -EINVAL; 821 - } 822 - /* FIXME: we assume reloc size is 4 dwords */ 823 - *cs_reloc = p->relocs_ptr[(idx / 4)]; 824 - return 0; 825 - } 826 - 827 - /** 828 - * r600_cs_packet_next_reloc_nomm() - parse next packet which should be reloc packet3 829 - * @parser: parser structure holding parsing context. 830 - * @data: pointer to relocation data 831 - * @offset_start: starting offset 832 - * @offset_mask: offset mask (to align start offset on) 833 - * @reloc: reloc informations 834 - * 835 - * Check next packet is relocation packet3, do bo validation and compute 836 - * GPU offset using the provided start. 837 - **/ 838 - static int r600_cs_packet_next_reloc_nomm(struct radeon_cs_parser *p, 839 - struct radeon_cs_reloc **cs_reloc) 840 - { 841 - struct radeon_cs_chunk *relocs_chunk; 842 - struct radeon_cs_packet p3reloc; 843 - unsigned idx; 844 - int r; 845 - 846 - if (p->chunk_relocs_idx == -1) { 847 - DRM_ERROR("No relocation chunk !\n"); 848 - return -EINVAL; 849 - } 850 - *cs_reloc = NULL; 851 - relocs_chunk = &p->chunks[p->chunk_relocs_idx]; 852 - r = radeon_cs_packet_parse(p, &p3reloc, p->idx); 853 - if (r) { 854 - return r; 855 - } 856 - p->idx += p3reloc.count + 2; 857 - if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) { 858 - DRM_ERROR("No packet3 for relocation for packet at %d.\n", 859 - p3reloc.idx); 860 - return -EINVAL; 861 - } 862 - idx = radeon_get_ib_value(p, p3reloc.idx + 1); 863 - if (idx >= relocs_chunk->length_dw) { 864 - DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", 865 - idx, relocs_chunk->length_dw); 866 - return -EINVAL; 867 - } 868 - *cs_reloc = p->relocs; 869 - (*cs_reloc)->lobj.gpu_offset = (u64)relocs_chunk->kdata[idx + 3] << 32; 870 - (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0]; 871 - return 0; 872 - } 873 - 874 - /** 875 787 * r600_cs_packet_parse_vline() - parse userspace VLINE packet 876 788 * @parser: parser structure holding parsing context. 877 789 * ··· 1017 1115 case R_028010_DB_DEPTH_INFO: 1018 1116 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) && 1019 1117 radeon_cs_packet_next_is_pkt3_nop(p)) { 1020 - r = r600_cs_packet_next_reloc(p, &reloc); 1118 + r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1021 1119 if (r) { 1022 1120 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1023 1121 "0x%04X\n", reg); ··· 1059 1157 case VGT_STRMOUT_BUFFER_BASE_1: 1060 1158 case VGT_STRMOUT_BUFFER_BASE_2: 1061 1159 case VGT_STRMOUT_BUFFER_BASE_3: 1062 - r = r600_cs_packet_next_reloc(p, &reloc); 1160 + r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1063 1161 if (r) { 1064 1162 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1065 1163 "0x%04X\n", reg); ··· 1082 1180 track->streamout_dirty = true; 1083 1181 break; 1084 1182 case CP_COHER_BASE: 1085 - r = r600_cs_packet_next_reloc(p, &reloc); 1183 + r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1086 1184 if (r) { 1087 1185 dev_warn(p->dev, "missing reloc for CP_COHER_BASE " 1088 1186 "0x%04X\n", reg); ··· 1118 1216 case R_0280BC_CB_COLOR7_INFO: 1119 1217 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) && 1120 1218 radeon_cs_packet_next_is_pkt3_nop(p)) { 1121 - r = r600_cs_packet_next_reloc(p, &reloc); 1219 + r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1122 1220 if (r) { 1123 1221 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); 1124 1222 return -EINVAL; ··· 1190 1288 track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp]; 1191 1289 ib[idx] = track->cb_color_base_last[tmp]; 1192 1290 } else { 1193 - r = r600_cs_packet_next_reloc(p, &reloc); 1291 + r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1194 1292 if (r) { 1195 1293 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); 1196 1294 return -EINVAL; ··· 1221 1319 track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp]; 1222 1320 ib[idx] = track->cb_color_base_last[tmp]; 1223 1321 } else { 1224 - r = r600_cs_packet_next_reloc(p, &reloc); 1322 + r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1225 1323 if (r) { 1226 1324 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); 1227 1325 return -EINVAL; ··· 1256 1354 case CB_COLOR5_BASE: 1257 1355 case CB_COLOR6_BASE: 1258 1356 case CB_COLOR7_BASE: 1259 - r = r600_cs_packet_next_reloc(p, &reloc); 1357 + r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1260 1358 if (r) { 1261 1359 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1262 1360 "0x%04X\n", reg); ··· 1271 1369 track->cb_dirty = true; 1272 1370 break; 1273 1371 case DB_DEPTH_BASE: 1274 - r = r600_cs_packet_next_reloc(p, &reloc); 1372 + r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1275 1373 if (r) { 1276 1374 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1277 1375 "0x%04X\n", reg); ··· 1284 1382 track->db_dirty = true; 1285 1383 break; 1286 1384 case DB_HTILE_DATA_BASE: 1287 - r = r600_cs_packet_next_reloc(p, &reloc); 1385 + r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1288 1386 if (r) { 1289 1387 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1290 1388 "0x%04X\n", reg); ··· 1354 1452 case SQ_ALU_CONST_CACHE_VS_13: 1355 1453 case SQ_ALU_CONST_CACHE_VS_14: 1356 1454 case SQ_ALU_CONST_CACHE_VS_15: 1357 - r = r600_cs_packet_next_reloc(p, &reloc); 1455 + r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1358 1456 if (r) { 1359 1457 dev_warn(p->dev, "bad SET_CONTEXT_REG " 1360 1458 "0x%04X\n", reg); ··· 1363 1461 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); 1364 1462 break; 1365 1463 case SX_MEMORY_EXPORT_BASE: 1366 - r = r600_cs_packet_next_reloc(p, &reloc); 1464 + r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1367 1465 if (r) { 1368 1466 dev_warn(p->dev, "bad SET_CONFIG_REG " 1369 1467 "0x%04X\n", reg); ··· 1649 1747 return -EINVAL; 1650 1748 } 1651 1749 1652 - r = r600_cs_packet_next_reloc(p, &reloc); 1750 + r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1653 1751 if (r) { 1654 1752 DRM_ERROR("bad SET PREDICATION\n"); 1655 1753 return -EINVAL; ··· 1690 1788 DRM_ERROR("bad DRAW_INDEX\n"); 1691 1789 return -EINVAL; 1692 1790 } 1693 - r = r600_cs_packet_next_reloc(p, &reloc); 1791 + r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1694 1792 if (r) { 1695 1793 DRM_ERROR("bad DRAW_INDEX\n"); 1696 1794 return -EINVAL; ··· 1742 1840 if (idx_value & 0x10) { 1743 1841 uint64_t offset; 1744 1842 1745 - r = r600_cs_packet_next_reloc(p, &reloc); 1843 + r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1746 1844 if (r) { 1747 1845 DRM_ERROR("bad WAIT_REG_MEM\n"); 1748 1846 return -EINVAL; ··· 1779 1877 return -EINVAL; 1780 1878 } 1781 1879 /* src address space is memory */ 1782 - r = r600_cs_packet_next_reloc(p, &reloc); 1880 + r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1783 1881 if (r) { 1784 1882 DRM_ERROR("bad CP DMA SRC\n"); 1785 1883 return -EINVAL; ··· 1809 1907 DRM_ERROR("CP DMA DAIC only supported for registers\n"); 1810 1908 return -EINVAL; 1811 1909 } 1812 - r = r600_cs_packet_next_reloc(p, &reloc); 1910 + r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1813 1911 if (r) { 1814 1912 DRM_ERROR("bad CP DMA DST\n"); 1815 1913 return -EINVAL; ··· 1839 1937 /* 0xffffffff/0x0 is flush all cache flag */ 1840 1938 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff || 1841 1939 radeon_get_ib_value(p, idx + 2) != 0) { 1842 - r = r600_cs_packet_next_reloc(p, &reloc); 1940 + r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1843 1941 if (r) { 1844 1942 DRM_ERROR("bad SURFACE_SYNC\n"); 1845 1943 return -EINVAL; ··· 1855 1953 if (pkt->count) { 1856 1954 uint64_t offset; 1857 1955 1858 - r = r600_cs_packet_next_reloc(p, &reloc); 1956 + r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1859 1957 if (r) { 1860 1958 DRM_ERROR("bad EVENT_WRITE\n"); 1861 1959 return -EINVAL; ··· 1876 1974 DRM_ERROR("bad EVENT_WRITE_EOP\n"); 1877 1975 return -EINVAL; 1878 1976 } 1879 - r = r600_cs_packet_next_reloc(p, &reloc); 1977 + r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1880 1978 if (r) { 1881 1979 DRM_ERROR("bad EVENT_WRITE\n"); 1882 1980 return -EINVAL; ··· 1942 2040 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) { 1943 2041 case SQ_TEX_VTX_VALID_TEXTURE: 1944 2042 /* tex base */ 1945 - r = r600_cs_packet_next_reloc(p, &reloc); 2043 + r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1946 2044 if (r) { 1947 2045 DRM_ERROR("bad SET_RESOURCE\n"); 1948 2046 return -EINVAL; ··· 1956 2054 } 1957 2055 texture = reloc->robj; 1958 2056 /* tex mip base */ 1959 - r = r600_cs_packet_next_reloc(p, &reloc); 2057 + r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1960 2058 if (r) { 1961 2059 DRM_ERROR("bad SET_RESOURCE\n"); 1962 2060 return -EINVAL; ··· 1977 2075 { 1978 2076 uint64_t offset64; 1979 2077 /* vtx base */ 1980 - r = r600_cs_packet_next_reloc(p, &reloc); 2078 + r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 1981 2079 if (r) { 1982 2080 DRM_ERROR("bad SET_RESOURCE\n"); 1983 2081 return -EINVAL; ··· 2078 2176 { 2079 2177 u64 offset; 2080 2178 2081 - r = r600_cs_packet_next_reloc(p, &reloc); 2179 + r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 2082 2180 if (r) { 2083 2181 DRM_ERROR("bad STRMOUT_BASE_UPDATE reloc\n"); 2084 2182 return -EINVAL; ··· 2122 2220 /* Updating memory at DST_ADDRESS. */ 2123 2221 if (idx_value & 0x1) { 2124 2222 u64 offset; 2125 - r = r600_cs_packet_next_reloc(p, &reloc); 2223 + r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 2126 2224 if (r) { 2127 2225 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n"); 2128 2226 return -EINVAL; ··· 2141 2239 /* Reading data from SRC_ADDRESS. */ 2142 2240 if (((idx_value >> 1) & 0x3) == 2) { 2143 2241 u64 offset; 2144 - r = r600_cs_packet_next_reloc(p, &reloc); 2242 + r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 2145 2243 if (r) { 2146 2244 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n"); 2147 2245 return -EINVAL; ··· 2166 2264 DRM_ERROR("bad MEM_WRITE (invalid count)\n"); 2167 2265 return -EINVAL; 2168 2266 } 2169 - r = r600_cs_packet_next_reloc(p, &reloc); 2267 + r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 2170 2268 if (r) { 2171 2269 DRM_ERROR("bad MEM_WRITE (missing reloc)\n"); 2172 2270 return -EINVAL; ··· 2195 2293 if (idx_value & 0x1) { 2196 2294 u64 offset; 2197 2295 /* SRC is memory. */ 2198 - r = r600_cs_packet_next_reloc(p, &reloc); 2296 + r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 2199 2297 if (r) { 2200 2298 DRM_ERROR("bad COPY_DW (missing src reloc)\n"); 2201 2299 return -EINVAL; ··· 2219 2317 if (idx_value & 0x2) { 2220 2318 u64 offset; 2221 2319 /* DST is memory. */ 2222 - r = r600_cs_packet_next_reloc(p, &reloc); 2320 + r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm); 2223 2321 if (r) { 2224 2322 DRM_ERROR("bad COPY_DW (missing dst reloc)\n"); 2225 2323 return -EINVAL; ··· 2407 2505 2408 2506 void r600_cs_legacy_init(void) 2409 2507 { 2410 - r600_cs_packet_next_reloc = &r600_cs_packet_next_reloc_nomm; 2508 + r600_nomm = 1; 2411 2509 } 2412 2510 2413 2511 /*