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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drivers: usb: fsl: Define usb control register mask for w1c bits
Define and use CONTROL_REGISTER_W1C_MASK to make sure that
w1c bits of usb control register do not get reset while
writing any other bit
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
authored by
Nikhil Badola
and committed by
Greg Kroah-Hartman
4e02bea8
f4fdfaa2
+17
-9
+16
-9
drivers/usb/host/ehci-fsl.c
+16
-9
drivers/usb/host/ehci-fsl.c
···
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/* Enable USB controller, 83xx or 8536 */
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if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6)
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-
setbits32(hcd->regs + FSL_SOC_USB_CTRL, 0x4);
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+
clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,
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+
CONTROL_REGISTER_W1C_MASK, 0x4);
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/*
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* Enable UTMI phy and program PTS field in UTMI mode before asserting
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* controller reset for USB Controller version 2.5
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*/
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if (pdata->has_fsl_erratum_a007792) {
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-
writel_be(CTRL_UTMI_PHY_EN, hcd->regs + FSL_SOC_USB_CTRL);
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+
clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,
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+
CONTROL_REGISTER_W1C_MASK, CTRL_UTMI_PHY_EN);
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writel(PORT_PTS_UTMI, hcd->regs + FSL_SOC_USB_PORTSC1);
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}
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···
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case FSL_USB2_PHY_ULPI:
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if (pdata->have_sysif_regs && pdata->controller_ver) {
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/* controller version 1.6 or above */
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-
clrbits32(non_ehci + FSL_SOC_USB_CTRL, UTMI_PHY_EN);
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-
setbits32(non_ehci + FSL_SOC_USB_CTRL,
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-
ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN);
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+
clrbits32(non_ehci + FSL_SOC_USB_CTRL,
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+
CONTROL_REGISTER_W1C_MASK | UTMI_PHY_EN);
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+
clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
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+
CONTROL_REGISTER_W1C_MASK,
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+
ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN);
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}
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portsc |= PORT_PTS_ULPI;
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break;
···
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case FSL_USB2_PHY_UTMI_DUAL:
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if (pdata->have_sysif_regs && pdata->controller_ver) {
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/* controller version 1.6 or above */
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-
setbits32(non_ehci + FSL_SOC_USB_CTRL, UTMI_PHY_EN);
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+
clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
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+
CONTROL_REGISTER_W1C_MASK, UTMI_PHY_EN);
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mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI PHY CLK to
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become stable - 10ms*/
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}
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/* enable UTMI PHY */
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if (pdata->have_sysif_regs)
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-
setbits32(non_ehci + FSL_SOC_USB_CTRL,
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-
CTRL_UTMI_PHY_EN);
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+
clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
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+
CONTROL_REGISTER_W1C_MASK,
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+
CTRL_UTMI_PHY_EN);
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portsc |= PORT_PTS_UTMI;
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break;
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case FSL_USB2_PHY_NONE:
···
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ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
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if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs)
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-
setbits32(non_ehci + FSL_SOC_USB_CTRL, USB_CTRL_USB_EN);
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+
clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
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+
CONTROL_REGISTER_W1C_MASK, USB_CTRL_USB_EN);
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return 0;
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}