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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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kernel
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linux
[POWERPC] 85xx: Add device nodes for error reporting devices used by EDAC
Adding memory-controller and l2-cache-controller entries to be used by EDAC
as of_devices for MPC8541 CDS, MPC8544 DS, MPC8555 CDS, and MPC8568 MDS.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
authored by Kumar Gala and committed by Paul Mackerras 4da421d6 50cf6707
+16
arch/powerpc/boot/dts/mpc8541cds.dts
+16
arch/powerpc/boot/dts/mpc8541cds.dts
···
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reg = <e0000000 00100000>; // CCSRBAR 1M
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bus-frequency = <0>;
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+
memory-controller@2000 {
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compatible = "fsl,8541-memory-controller";
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reg = <2000 1000>;
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interrupt-parent = <&mpic>;
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interrupts = <2 2>;
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};
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+
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l2-cache-controller@20000 {
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compatible = "fsl,8541-l2-cache-controller";
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reg = <20000 1000>;
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cache-line-size = <20>; // 32 bytes
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cache-size = <40000>; // L2, 256K
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interrupt-parent = <&mpic>;
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interrupts = <0 2>;
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};
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+
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i2c@3000 {
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device_type = "i2c";
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compatible = "fsl-i2c";
+16
arch/powerpc/boot/dts/mpc8544ds.dts
+16
arch/powerpc/boot/dts/mpc8544ds.dts
···
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reg = <e0000000 00100000>; // CCSRBAR 1M
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bus-frequency = <0>; // Filled out by uboot.
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memory-controller@2000 {
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compatible = "fsl,8544-memory-controller";
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reg = <2000 1000>;
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interrupt-parent = <&mpic>;
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interrupts = <2 2>;
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};
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l2-cache-controller@20000 {
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compatible = "fsl,8544-l2-cache-controller";
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reg = <20000 1000>;
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cache-line-size = <20>; // 32 bytes
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cache-size = <40000>; // L2, 256K
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+
interrupt-parent = <&mpic>;
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interrupts = <0 2>;
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};
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+
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i2c@3000 {
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device_type = "i2c";
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compatible = "fsl-i2c";
+16
arch/powerpc/boot/dts/mpc8555cds.dts
+16
arch/powerpc/boot/dts/mpc8555cds.dts
···
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reg = <e0000000 00100000>; // CCSRBAR 1M
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bus-frequency = <0>;
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+
memory-controller@2000 {
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compatible = "fsl,8555-memory-controller";
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reg = <2000 1000>;
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+
interrupt-parent = <&mpic>;
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+
interrupts = <2 2>;
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+
};
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+
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l2-cache-controller@20000 {
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compatible = "fsl,8555-l2-cache-controller";
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reg = <20000 1000>;
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cache-line-size = <20>; // 32 bytes
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cache-size = <40000>; // L2, 256K
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+
interrupt-parent = <&mpic>;
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+
interrupts = <0 2>;
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};
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+
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i2c@3000 {
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device_type = "i2c";
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compatible = "fsl-i2c";
+16
arch/powerpc/boot/dts/mpc8568mds.dts
+16
arch/powerpc/boot/dts/mpc8568mds.dts
···
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reg = <e0000000 00100000>;
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bus-frequency = <0>;
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+
memory-controller@2000 {
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compatible = "fsl,8568-memory-controller";
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reg = <2000 1000>;
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interrupt-parent = <&mpic>;
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interrupts = <2 2>;
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};
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+
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l2-cache-controller@20000 {
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compatible = "fsl,8568-l2-cache-controller";
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reg = <20000 1000>;
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cache-line-size = <20>; // 32 bytes
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cache-size = <80000>; // L2, 512K
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interrupt-parent = <&mpic>;
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interrupts = <0 2>;
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};
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+
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i2c@3000 {
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device_type = "i2c";
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compatible = "fsl-i2c";