tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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m68knommu: support ColdFire caches that do copyback and write-through

The version 3 and version 4 ColdFire cache controllers support both
write-through and copy-back modes on the data cache. Allow for Kconfig
time configuration of this, and set the cache mode appropriately.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>

Greg Ungerer 4a5bae41 0ef6c9b8

+35 -1
unified split
+7 -1
arch/m68k/include/asm/m53xxacr.h
··· 53 53 * CACR is cache inhibited, we use the ACR register to set cacheing 54 54 * enabled on the regions we want (eg RAM). 55 55 */ 56 + #if defined(CONFIG_CACHE_COPYBACK) 57 + #define CACHE_TYPE ACR_CM_CB 58 + #else 59 + #define CACHE_TYPE ACR_CM_WT 60 + #endif 61 + 56 62 #ifdef CONFIG_COLDFIRE_SW_A7 57 63 #define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE) 58 64 #else ··· 69 63 70 64 #define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \ 71 65 (0x000f0000) + \ 72 - (ACR_ENABLE + ACR_ANY + ACR_CM_CB)) 66 + (ACR_ENABLE + ACR_ANY + CACHE_TYPE)) 73 67 #define ACR1_MODE 0 74 68 75 69 /****************************************************************************/
+4
arch/m68k/include/asm/m54xxacr.h
··· 73 73 #else 74 74 #define CACHE_MODE (CACR_DEC+CACR_DESB+CACR_DDCM_P+CACR_BEC+CACR_IEC+CACR_EUSP) 75 75 #endif 76 + #if defined(CONFIG_CACHE_COPYBACK) 77 + #define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_CP) 78 + #else 76 79 #define DATA_CACHE_MODE (ACR_ENABLE+ACR_ANY+ACR_CM_WT) 80 + #endif 77 81 #define INSN_CACHE_MODE (ACR_ENABLE+ACR_ANY) 78 82 79 83 #define CACHE_INIT (CACR_DCINVA+CACR_BCINVA+CACR_ICINVA)
+24
arch/m68knommu/Kconfig
··· 82 82 config HAVE_CACHE_SPLIT 83 83 bool 84 84 85 + config HAVE_CACHE_CB 86 + bool 87 + 85 88 source "init/Kconfig" 86 89 87 90 source "kernel/Kconfig.freezer" ··· 175 172 config M5307 176 173 bool "MCF5307" 177 174 select COLDFIRE_SW_A7 175 + select HAVE_CACHE_CB 178 176 help 179 177 Motorola ColdFire 5307 processor support. 180 178 181 179 config M532x 182 180 bool "MCF532x" 181 + select HAVE_CACHE_CB 183 182 help 184 183 Freescale (Motorola) ColdFire 532x processor support. 185 184 186 185 config M5407 187 186 bool "MCF5407" 188 187 select COLDFIRE_SW_A7 188 + select HAVE_CACHE_CB 189 189 help 190 190 Motorola ColdFire 5407 processor support. 191 191 192 192 config M547x 193 193 bool "MCF547x" 194 + select HAVE_CACHE_CB 194 195 help 195 196 Freescale ColdFire 5470/5471/5472/5473/5474/5475 processor support. 196 197 197 198 config M548x 198 199 bool "MCF548x" 200 + select HAVE_CACHE_CB 199 201 help 200 202 Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support. 201 203 ··· 287 279 Split the ColdFire CPU cache, and use half as an instruction cache 288 280 and half as a data cache. 289 281 endchoice 282 + endif 290 283 284 + if HAVE_CACHE_CB 285 + choice 286 + prompt "Data cache mode" 287 + default CACHE_WRITETHRU 288 + 289 + config CACHE_WRITETHRU 290 + bool "Write-through" 291 + help 292 + The ColdFire CPU cache is set into Write-through mode. 293 + 294 + config CACHE_COPYBACK 295 + bool "Copy-back" 296 + help 297 + The ColdFire CPU cache is set into Copy-back mode. 298 + endchoice 291 299 endif 292 300 293 301 comment "Platform"