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linux
m68knommu: support version 2 ColdFire split cache
The newer version 2 ColdFire CPU cores support a configurable cache
arrangement. The cache memory can be used as all instruction cache, all
data cache, or split in half for both instruction and data caching.
Support this setup via a Kconfig time menu that allows a kernel builder
to choose the arrangement they want to use.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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arch/m68k/include/asm/m52xxacr.h
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arch/m68k/include/asm/m52xxacr.h
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#define ACR_WPROTECT 0x00000004 /* Write protect region */
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/*
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* Set the cache controller settings we will use. This code is set to
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* only use the instruction cache, even on the controllers that support
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* split cache. (This setup is trying to preserve the existing behavior
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* for now, in the furture I hope to actually use the split cache mode).
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* Set the cache controller settings we will use. On the cores that support
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* a split cache configuration we allow all the combinations at Kconfig
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* time. For those cores that only have an instruction cache we just set
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* that as on.
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*/
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#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
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defined(CONFIG_M5249) || defined(CONFIG_M5272)
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#if defined(CONFIG_CACHE_I)
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#define CACHE_TYPE CACR_DISD
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#elif defined(CONFIG_CACHE_D)
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#define CACHE_TYPE CACR_DISI
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#else
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#define CACHE_TYPE
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#endif
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#if defined(CONFIG_HAVE_CACHE_SPLIT)
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#define CACHE_INIT (CACR_CINV + CACHE_TYPE + CACR_EUSP)
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#define CACHE_MODE (CACR_CENB + CACHE_TYPE + CACR_DCM + CACR_EUSP)
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#else
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#define CACHE_INIT (CACR_CINV)
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#define CACHE_MODE (CACR_CENB + CACR_DCM)
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#else
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#ifdef CONFIG_COLDFIRE_SW_A7
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#define CACHE_INIT (CACR_CINV + CACR_DISD)
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#define CACHE_MODE (CACR_CENB + CACR_DISD + CACR_DCM)
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#else
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#define CACHE_INIT (CACR_CINV + CACR_DISD + CACR_EUSP)
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#define CACHE_MODE (CACR_CENB + CACR_DISD + CACR_DCM + CACR_EUSP)
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#endif
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#endif
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#define CACHE_INVALIDATE (CACHE_MODE + CACR_CINV)
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arch/m68knommu/Kconfig
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arch/m68knommu/Kconfig
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bool
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default n
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config HAVE_CACHE_SPLIT
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bool
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source "init/Kconfig"
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source "kernel/Kconfig.freezer"
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config M520x
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bool "MCF520x"
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select GENERIC_CLOCKEVENTS
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select HAVE_CACHE_SPLIT
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help
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Freescale Coldfire 5207/5208 processor support.
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config M523x
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bool "MCF523x"
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select GENERIC_CLOCKEVENTS
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select HAVE_CACHE_SPLIT
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help
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Freescale Coldfire 5230/1/2/4/5 processor support
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···
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config M5271
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bool "MCF5271"
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select HAVE_CACHE_SPLIT
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help
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Freescale (Motorola) ColdFire 5270/5271 processor support.
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···
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config M5275
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bool "MCF5275"
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select HAVE_CACHE_SPLIT
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help
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Freescale (Motorola) ColdFire 5274/5275 processor support.
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config M528x
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bool "MCF528x"
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select GENERIC_CLOCKEVENTS
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select HAVE_CACHE_SPLIT
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help
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Motorola ColdFire 5280/5282 processor support.
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···
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help
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Build support for the older revision ColdFire 5307 silicon.
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Specifically this is the 1H55J mask revision.
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if HAVE_CACHE_SPLIT
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choice
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prompt "Split Cache Configuration"
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default CACHE_I
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config CACHE_I
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bool "Instruction"
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help
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Use all of the ColdFire CPU cache memory as an instruction cache.
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config CACHE_D
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bool "Data"
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help
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Use all of the ColdFire CPU cache memory as a data cache.
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config CACHE_BOTH
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bool "Both"
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help
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Split the ColdFire CPU cache, and use half as an instruction cache
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and half as a data cache.
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endchoice
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endif
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comment "Platform"
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