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ARM: dts: qcom: align SDHCI clocks with DT schema

The DT schema expects clocks iface-core order. No functional change.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220712144245.17417-6-krzysztof.kozlowski@linaro.org

authored by

Krzysztof Kozlowski and committed by
Bjorn Andersson 49c19337 5eb82ddb

+29 -29
+6 -6
arch/arm/boot/dts/qcom-apq8084.dtsi
··· 425 425 reg-names = "hc", "core"; 426 426 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 427 427 interrupt-names = "hc_irq", "pwr_irq"; 428 - clocks = <&gcc GCC_SDCC1_APPS_CLK>, 429 - <&gcc GCC_SDCC1_AHB_CLK>, 428 + clocks = <&gcc GCC_SDCC1_AHB_CLK>, 429 + <&gcc GCC_SDCC1_APPS_CLK>, 430 430 <&xo_board>; 431 - clock-names = "core", "iface", "xo"; 431 + clock-names = "iface", "core", "xo"; 432 432 status = "disabled"; 433 433 }; 434 434 ··· 438 438 reg-names = "hc", "core"; 439 439 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 440 440 interrupt-names = "hc_irq", "pwr_irq"; 441 - clocks = <&gcc GCC_SDCC2_APPS_CLK>, 442 - <&gcc GCC_SDCC2_AHB_CLK>, 441 + clocks = <&gcc GCC_SDCC2_AHB_CLK>, 442 + <&gcc GCC_SDCC2_APPS_CLK>, 443 443 <&xo_board>; 444 - clock-names = "core", "iface", "xo"; 444 + clock-names = "iface", "core", "xo"; 445 445 status = "disabled"; 446 446 }; 447 447
+2 -2
arch/arm/boot/dts/qcom-ipq4019.dtsi
··· 228 228 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 229 229 interrupt-names = "hc_irq", "pwr_irq"; 230 230 bus-width = <8>; 231 - clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>, 231 + clocks = <&gcc GCC_SDCC1_AHB_CLK>, <&gcc GCC_SDCC1_APPS_CLK>, 232 232 <&gcc GCC_DCD_XO_CLK>; 233 - clock-names = "core", "iface", "xo"; 233 + clock-names = "iface", "core", "xo"; 234 234 status = "disabled"; 235 235 }; 236 236
+9 -9
arch/arm/boot/dts/qcom-msm8226.dtsi
··· 134 134 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 135 135 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 136 136 interrupt-names = "hc_irq", "pwr_irq"; 137 - clocks = <&gcc GCC_SDCC1_APPS_CLK>, 138 - <&gcc GCC_SDCC1_AHB_CLK>, 137 + clocks = <&gcc GCC_SDCC1_AHB_CLK>, 138 + <&gcc GCC_SDCC1_APPS_CLK>, 139 139 <&xo_board>; 140 - clock-names = "core", "iface", "xo"; 140 + clock-names = "iface", "core", "xo"; 141 141 pinctrl-names = "default"; 142 142 pinctrl-0 = <&sdhc1_default_state>; 143 143 status = "disabled"; ··· 150 150 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 151 151 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 152 152 interrupt-names = "hc_irq", "pwr_irq"; 153 - clocks = <&gcc GCC_SDCC2_APPS_CLK>, 154 - <&gcc GCC_SDCC2_AHB_CLK>, 153 + clocks = <&gcc GCC_SDCC2_AHB_CLK>, 154 + <&gcc GCC_SDCC2_APPS_CLK>, 155 155 <&xo_board>; 156 - clock-names = "core", "iface", "xo"; 156 + clock-names = "iface", "core", "xo"; 157 157 pinctrl-names = "default"; 158 158 pinctrl-0 = <&sdhc2_default_state>; 159 159 status = "disabled"; ··· 166 166 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 167 167 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 168 168 interrupt-names = "hc_irq", "pwr_irq"; 169 - clocks = <&gcc GCC_SDCC3_APPS_CLK>, 170 - <&gcc GCC_SDCC3_AHB_CLK>, 169 + clocks = <&gcc GCC_SDCC3_AHB_CLK>, 170 + <&gcc GCC_SDCC3_APPS_CLK>, 171 171 <&xo_board>; 172 - clock-names = "core", "iface", "xo"; 172 + clock-names = "iface", "core", "xo"; 173 173 pinctrl-names = "default"; 174 174 pinctrl-0 = <&sdhc3_default_state>; 175 175 status = "disabled";
+9 -9
arch/arm/boot/dts/qcom-msm8974.dtsi
··· 443 443 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 444 444 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 445 445 interrupt-names = "hc_irq", "pwr_irq"; 446 - clocks = <&gcc GCC_SDCC1_APPS_CLK>, 447 - <&gcc GCC_SDCC1_AHB_CLK>, 446 + clocks = <&gcc GCC_SDCC1_AHB_CLK>, 447 + <&gcc GCC_SDCC1_APPS_CLK>, 448 448 <&xo_board>; 449 - clock-names = "core", "iface", "xo"; 449 + clock-names = "iface", "core", "xo"; 450 450 bus-width = <8>; 451 451 non-removable; 452 452 ··· 460 460 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 461 461 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 462 462 interrupt-names = "hc_irq", "pwr_irq"; 463 - clocks = <&gcc GCC_SDCC3_APPS_CLK>, 464 - <&gcc GCC_SDCC3_AHB_CLK>, 463 + clocks = <&gcc GCC_SDCC3_AHB_CLK>, 464 + <&gcc GCC_SDCC3_APPS_CLK>, 465 465 <&xo_board>; 466 - clock-names = "core", "iface", "xo"; 466 + clock-names = "iface", "core", "xo"; 467 467 bus-width = <4>; 468 468 469 469 #address-cells = <1>; ··· 479 479 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 480 480 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 481 481 interrupt-names = "hc_irq", "pwr_irq"; 482 - clocks = <&gcc GCC_SDCC2_APPS_CLK>, 483 - <&gcc GCC_SDCC2_AHB_CLK>, 482 + clocks = <&gcc GCC_SDCC2_AHB_CLK>, 483 + <&gcc GCC_SDCC2_APPS_CLK>, 484 484 <&xo_board>; 485 - clock-names = "core", "iface", "xo"; 485 + clock-names = "iface", "core", "xo"; 486 486 bus-width = <4>; 487 487 488 488 #address-cells = <1>;
+3 -3
arch/arm/boot/dts/qcom-msm8974pro.dtsi
··· 10 10 }; 11 11 12 12 &sdhc_1 { 13 - clocks = <&gcc GCC_SDCC1_APPS_CLK>, 14 - <&gcc GCC_SDCC1_AHB_CLK>, 13 + clocks = <&gcc GCC_SDCC1_AHB_CLK>, 14 + <&gcc GCC_SDCC1_APPS_CLK>, 15 15 <&xo_board>, 16 16 <&gcc GCC_SDCC1_CDCCAL_FF_CLK>, 17 17 <&gcc GCC_SDCC1_CDCCAL_SLEEP_CLK>; 18 - clock-names = "core", "iface", "xo", "cal", "sleep"; 18 + clock-names = "iface", "core", "xo", "cal", "sleep"; 19 19 };