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ARM: dts: qcom: align SDHCI reg-names with DT schema

DT schema requires SDHCI reg names to be hc/core without "_mem" suffix,
just like TXT bindings were expecting before the conversion.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220712144245.17417-5-krzysztof.kozlowski@linaro.org

authored by

Krzysztof Kozlowski and committed by
Bjorn Andersson 5eb82ddb 2e312b34

+10 -9
+2 -2
arch/arm/boot/dts/qcom-apq8084.dtsi
··· 422 422 mmc@f9824900 { 423 423 compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; 424 424 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; 425 - reg-names = "hc_mem", "core_mem"; 425 + reg-names = "hc", "core"; 426 426 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 427 427 interrupt-names = "hc_irq", "pwr_irq"; 428 428 clocks = <&gcc GCC_SDCC1_APPS_CLK>, ··· 435 435 mmc@f98a4900 { 436 436 compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; 437 437 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 438 - reg-names = "hc_mem", "core_mem"; 438 + reg-names = "hc", "core"; 439 439 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 440 440 interrupt-names = "hc_irq", "pwr_irq"; 441 441 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
+1
arch/arm/boot/dts/qcom-ipq4019.dtsi
··· 224 224 sdhci: mmc@7824900 { 225 225 compatible = "qcom,sdhci-msm-v4"; 226 226 reg = <0x7824900 0x11c>, <0x7824000 0x800>; 227 + reg-names = "hc", "core"; 227 228 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 228 229 interrupt-names = "hc_irq", "pwr_irq"; 229 230 bus-width = <8>;
+3 -3
arch/arm/boot/dts/qcom-msm8226.dtsi
··· 130 130 sdhc_1: mmc@f9824900 { 131 131 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; 132 132 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; 133 - reg-names = "hc_mem", "core_mem"; 133 + reg-names = "hc", "core"; 134 134 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 135 135 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 136 136 interrupt-names = "hc_irq", "pwr_irq"; ··· 146 146 sdhc_2: mmc@f98a4900 { 147 147 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; 148 148 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 149 - reg-names = "hc_mem", "core_mem"; 149 + reg-names = "hc", "core"; 150 150 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 151 151 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 152 152 interrupt-names = "hc_irq", "pwr_irq"; ··· 162 162 sdhc_3: mmc@f9864900 { 163 163 compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"; 164 164 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; 165 - reg-names = "hc_mem", "core_mem"; 165 + reg-names = "hc", "core"; 166 166 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 167 167 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 168 168 interrupt-names = "hc_irq", "pwr_irq";
+3 -3
arch/arm/boot/dts/qcom-msm8974.dtsi
··· 439 439 sdhc_1: mmc@f9824900 { 440 440 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 441 441 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; 442 - reg-names = "hc_mem", "core_mem"; 442 + reg-names = "hc", "core"; 443 443 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 444 444 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 445 445 interrupt-names = "hc_irq", "pwr_irq"; ··· 456 456 sdhc_3: mmc@f9864900 { 457 457 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 458 458 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>; 459 - reg-names = "hc_mem", "core_mem"; 459 + reg-names = "hc", "core"; 460 460 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 461 461 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 462 462 interrupt-names = "hc_irq", "pwr_irq"; ··· 475 475 sdhc_2: mmc@f98a4900 { 476 476 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"; 477 477 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 478 - reg-names = "hc_mem", "core_mem"; 478 + reg-names = "hc", "core"; 479 479 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 480 480 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 481 481 interrupt-names = "hc_irq", "pwr_irq";
+1 -1
arch/arm/boot/dts/qcom-sdx65.dtsi
··· 334 334 sdhc_1: mmc@8804000 { 335 335 compatible = "qcom,sdx65-sdhci", "qcom,sdhci-msm-v5"; 336 336 reg = <0x08804000 0x1000>; 337 - reg-names = "hc_mem"; 337 + reg-names = "hc"; 338 338 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 339 339 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 340 340 interrupt-names = "hc_irq", "pwr_irq";