···18#include <linux/bitops.h>19#include <linux/uaccess.h>20#include <linux/clk.h>02122#define DRV_NAME "WDOG COH 901 327"23···93static void coh901327_enable(u16 timeout)94{95 u16 val;009697 clk_enable(clk);98 /* Restart timer if it is disabled */···105 /* Acknowledge any pending interrupt so it doesn't just fire off */106 writew(U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE,107 virtbase + U300_WDOG_IER);00000000108 /* Enable the watchdog interrupt */109 writew(U300_WDOG_IMR_WILL_BARK_IRQ_ENABLE, virtbase + U300_WDOG_IMR);110 /* Activate the watchdog timer */
···18#include <linux/bitops.h>19#include <linux/uaccess.h>20#include <linux/clk.h>21+#include <linux/delay.h>2223#define DRV_NAME "WDOG COH 901 327"24···92static void coh901327_enable(u16 timeout)93{94 u16 val;95+ unsigned long freq;96+ unsigned long delay_ns;9798 clk_enable(clk);99 /* Restart timer if it is disabled */···102 /* Acknowledge any pending interrupt so it doesn't just fire off */103 writew(U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE,104 virtbase + U300_WDOG_IER);105+ /*106+ * The interrupt is cleared in the 32 kHz clock domain.107+ * Wait 3 32 kHz cycles for it to take effect108+ */109+ freq = clk_get_rate(clk);110+ delay_ns = (1000000000 + freq - 1) / freq; /* Freq to ns and round up */111+ delay_ns = 3 * delay_ns; /* Wait 3 cycles */112+ ndelay(delay_ns);113 /* Enable the watchdog interrupt */114 writew(U300_WDOG_IMR_WILL_BARK_IRQ_ENABLE, virtbase + U300_WDOG_IMR);115 /* Activate the watchdog timer */