···1818#include <linux/bitops.h>1919#include <linux/uaccess.h>2020#include <linux/clk.h>2121+#include <linux/delay.h>21222223#define DRV_NAME "WDOG COH 901 327"2324···9392static void coh901327_enable(u16 timeout)9493{9594 u16 val;9595+ unsigned long freq;9696+ unsigned long delay_ns;96979798 clk_enable(clk);9899 /* Restart timer if it is disabled */···105102 /* Acknowledge any pending interrupt so it doesn't just fire off */106103 writew(U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE,107104 virtbase + U300_WDOG_IER);105105+ /*106106+ * The interrupt is cleared in the 32 kHz clock domain.107107+ * Wait 3 32 kHz cycles for it to take effect108108+ */109109+ freq = clk_get_rate(clk);110110+ delay_ns = (1000000000 + freq - 1) / freq; /* Freq to ns and round up */111111+ delay_ns = 3 * delay_ns; /* Wait 3 cycles */112112+ ndelay(delay_ns);108113 /* Enable the watchdog interrupt */109114 writew(U300_WDOG_IMR_WILL_BARK_IRQ_ENABLE, virtbase + U300_WDOG_IMR);110115 /* Activate the watchdog timer */