Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

amd-xgbe: align CL37 AN sequence as per databook

Update the Clause 37 Auto-Negotiation implementation to properly align
with the PCS hardware specifications:
- Fix incorrect bit settings in Link Status and Link Duplex fields
- Implement missing sequence steps 2 and 7

These changes ensure CL37 auto-negotiation protocol follows the exact
sequence patterns as specified in the hardware databook.

Fixes: 1bf40ada6290 ("amd-xgbe: Add support for clause 37 auto-negotiation")
Signed-off-by: Raju Rangoju <Raju.Rangoju@amd.com>
Link: https://patch.msgid.link/20250630192636.3838291-1-Raju.Rangoju@amd.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

authored by

Raju Rangoju and committed by
Jakub Kicinski
42fd432f e6ed134a

+13 -2
+2
drivers/net/ethernet/amd/xgbe/xgbe-common.h
··· 1269 1269 #define MDIO_VEND2_CTRL1_SS13 BIT(13) 1270 1270 #endif 1271 1271 1272 + #define XGBE_VEND2_MAC_AUTO_SW BIT(9) 1273 + 1272 1274 /* MDIO mask values */ 1273 1275 #define XGBE_AN_CL73_INT_CMPLT BIT(0) 1274 1276 #define XGBE_AN_CL73_INC_LINK BIT(1)
+9
drivers/net/ethernet/amd/xgbe/xgbe-mdio.c
··· 266 266 reg |= MDIO_VEND2_CTRL1_AN_RESTART; 267 267 268 268 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg); 269 + 270 + reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_PCS_DIG_CTRL); 271 + reg |= XGBE_VEND2_MAC_AUTO_SW; 272 + XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_PCS_DIG_CTRL, reg); 269 273 } 270 274 271 275 static void xgbe_an37_restart(struct xgbe_prv_data *pdata) ··· 898 894 899 895 netif_dbg(pdata, link, pdata->netdev, "CL37 AN (%s) initialized\n", 900 896 (pdata->an_mode == XGBE_AN_MODE_CL37) ? "BaseX" : "SGMII"); 897 + 898 + reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1); 899 + reg &= ~MDIO_AN_CTRL1_ENABLE; 900 + XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg); 901 + 901 902 } 902 903 903 904 static void xgbe_an73_init(struct xgbe_prv_data *pdata)
+2 -2
drivers/net/ethernet/amd/xgbe/xgbe.h
··· 183 183 #define XGBE_LINK_TIMEOUT 5 184 184 #define XGBE_KR_TRAINING_WAIT_ITER 50 185 185 186 - #define XGBE_SGMII_AN_LINK_STATUS BIT(1) 186 + #define XGBE_SGMII_AN_LINK_DUPLEX BIT(1) 187 187 #define XGBE_SGMII_AN_LINK_SPEED (BIT(2) | BIT(3)) 188 188 #define XGBE_SGMII_AN_LINK_SPEED_10 0x00 189 189 #define XGBE_SGMII_AN_LINK_SPEED_100 0x04 190 190 #define XGBE_SGMII_AN_LINK_SPEED_1000 0x08 191 - #define XGBE_SGMII_AN_LINK_DUPLEX BIT(4) 191 + #define XGBE_SGMII_AN_LINK_STATUS BIT(4) 192 192 193 193 /* ECC correctable error notification window (seconds) */ 194 194 #define XGBE_ECC_LIMIT 60