Merge branch '4.0-fixes' into mips-for-linux-next

+37 -2

arch/mips/Kconfig

··· 415 415 select SYS_HAS_CPU_MIPS32_R1 416 416 select SYS_HAS_CPU_MIPS32_R2 417 417 select SYS_HAS_CPU_MIPS32_R3_5 418 + select SYS_HAS_CPU_MIPS32_R5 418 419 select SYS_HAS_CPU_MIPS32_R6 419 420 select SYS_HAS_CPU_MIPS64_R1 420 421 select SYS_HAS_CPU_MIPS64_R2 ··· 425 424 select SYS_SUPPORTS_32BIT_KERNEL 426 425 select SYS_SUPPORTS_64BIT_KERNEL 427 426 select SYS_SUPPORTS_BIG_ENDIAN 427 + select SYS_SUPPORTS_HIGHMEM 428 428 select SYS_SUPPORTS_LITTLE_ENDIAN 429 429 select SYS_SUPPORTS_MICROMIPS 430 430 select SYS_SUPPORTS_MIPS_CMP ··· 1640 1638 One of its primary benefits is an increase in the maximum size 1641 1639 of lowmem (up to 3GB). If unsure, say 'N' here. 1642 1640 1641 + config CPU_MIPS32_R5_FEATURES 1642 + bool "MIPS32 Release 5 Features" 1643 + depends on SYS_HAS_CPU_MIPS32_R5 1644 + depends on CPU_MIPS32_R2 1645 + help 1646 + Choose this option to build a kernel for release 2 or later of the 1647 + MIPS32 architecture including features from release 5 such as 1648 + support for Extended Physical Addressing (XPA). 1649 + 1650 + config CPU_MIPS32_R5_XPA 1651 + bool "Extended Physical Addressing (XPA)" 1652 + depends on CPU_MIPS32_R5_FEATURES 1653 + depends on !EVA 1654 + depends on !PAGE_SIZE_4KB 1655 + depends on SYS_SUPPORTS_HIGHMEM 1656 + select XPA 1657 + select HIGHMEM 1658 + select ARCH_PHYS_ADDR_T_64BIT 1659 + default n 1660 + help 1661 + Choose this option if you want to enable the Extended Physical 1662 + Addressing (XPA) on your MIPS32 core (such as P5600 series). The 1663 + benefit is to increase physical addressing equal to or greater 1664 + than 40 bits. Note that this has the side effect of turning on 1665 + 64-bit addressing which in turn makes the PTEs 64-bit in size. 1666 + If unsure, say 'N' here. 1667 + 1643 1668 if CPU_LOONGSON2F 1644 1669 config CPU_NOP_WORKAROUNDS 1645 1670 bool ··· 1768 1739 bool 1769 1740 1770 1741 config SYS_HAS_CPU_MIPS32_R3_5 1742 + bool 1743 + 1744 + config SYS_HAS_CPU_MIPS32_R5 1771 1745 bool 1772 1746 1773 1747 config SYS_HAS_CPU_MIPS32_R6 ··· 1908 1876 select MIPS_SPRAM 1909 1877 1910 1878 config EVA 1879 + bool 1880 + 1881 + config XPA 1911 1882 bool 1912 1883 1913 1884 config SYS_SUPPORTS_32BIT_KERNEL ··· 2149 2114 help 2150 2115 Choose this option if you want to run non-R6 MIPS userland code. 2151 2116 Even if you say 'Y' here, the emulator will still be disabled by 2152 - default. You can enable it using the 'mipsr2emul' kernel option. 2117 + default. You can enable it using the 'mipsr2emu' kernel option. 2153 2118 The only reason this is a build-time option is to save ~14K from the 2154 2119 final kernel image. 2155 2120 comment "MIPS R2-to-R6 emulator is only available for UP kernels" ··· 2219 2184 2220 2185 config MIPS_CPS 2221 2186 bool "MIPS Coherent Processing System support" 2222 - depends on SYS_SUPPORTS_MIPS_CPS 2187 + depends on SYS_SUPPORTS_MIPS_CPS && !64BIT 2223 2188 select MIPS_CM 2224 2189 select MIPS_CPC 2225 2190 select MIPS_CPS_PM if HOTPLUG_CPU

+10 -4

arch/mips/Makefile

··· 197 197 # Warning: the 64-bit MIPS architecture does not support the `smartmips' extension 198 198 # Pass -Wa,--no-warn to disable all assembler warnings until the kernel code has 199 199 # been fixed properly. 200 - mips-cflags := "$(cflags-y)" 201 - cflags-$(CONFIG_CPU_HAS_SMARTMIPS) += $(call cc-option,$(mips-cflags),-msmartmips) -Wa,--no-warn 202 - cflags-$(CONFIG_CPU_MICROMIPS) += $(call cc-option,$(mips-cflags),-mmicromips) 200 + mips-cflags := $(cflags-y) 201 + ifeq ($(CONFIG_CPU_HAS_SMARTMIPS),y) 202 + smartmips-ase := $(call cc-option-yn,$(mips-cflags) -msmartmips) 203 + cflags-$(smartmips-ase) += -msmartmips -Wa,--no-warn 204 + endif 205 + ifeq ($(CONFIG_CPU_MICROMIPS),y) 206 + micromips-ase := $(call cc-option-yn,$(mips-cflags) -mmicromips) 207 + cflags-$(micromips-ase) += -mmicromips 208 + endif 203 209 ifeq ($(CONFIG_CPU_HAS_MSA),y) 204 - toolchain-msa := $(call cc-option-yn,-$(mips-cflags),mhard-float -mfp64 -Wa$(comma)-mmsa) 210 + toolchain-msa := $(call cc-option-yn,$(mips-cflags) -mhard-float -mfp64 -Wa$(comma)-mmsa) 205 211 cflags-$(toolchain-msa) += -DTOOLCHAIN_SUPPORTS_MSA 206 212 endif 207 213

+2 -2

arch/mips/bcm47xx/board.c

··· 235 235 } 236 236 237 237 if (bcm47xx_nvram_getenv("hardware_version", buf1, sizeof(buf1)) >= 0 && 238 - bcm47xx_nvram_getenv("boardtype", buf2, sizeof(buf2)) >= 0) { 239 - for (e2 = bcm47xx_board_list_boot_hw; e2->value1; e2++) { 238 + bcm47xx_nvram_getenv("boardnum", buf2, sizeof(buf2)) >= 0) { 239 + for (e2 = bcm47xx_board_list_hw_version_num; e2->value1; e2++) { 240 240 if (!strstarts(buf1, e2->value1) && 241 241 !strcmp(buf2, e2->value2)) 242 242 return &e2->board;

-4

arch/mips/bcm63xx/prom.c

··· 17 17 #include <bcm63xx_cpu.h> 18 18 #include <bcm63xx_io.h> 19 19 #include <bcm63xx_regs.h> 20 - #include <bcm63xx_gpio.h> 21 20 22 21 void __init prom_init(void) 23 22 { ··· 51 52 reg = bcm_perf_readl(PERF_CKCTL_REG); 52 53 reg &= ~mask; 53 54 bcm_perf_writel(reg, PERF_CKCTL_REG); 54 - 55 - /* register gpiochip */ 56 - bcm63xx_gpio_init(); 57 55 58 56 /* do low level board init */ 59 57 board_prom_init();

+4

arch/mips/bcm63xx/setup.c

··· 20 20 #include <bcm63xx_cpu.h> 21 21 #include <bcm63xx_regs.h> 22 22 #include <bcm63xx_io.h> 23 + #include <bcm63xx_gpio.h> 23 24 24 25 void bcm63xx_machine_halt(void) 25 26 { ··· 161 160 162 161 int __init bcm63xx_register_devices(void) 163 162 { 163 + /* register gpiochip */ 164 + bcm63xx_gpio_init(); 165 + 164 166 return board_register_devices(); 165 167 } 166 168

+1 -1

arch/mips/cavium-octeon/dma-octeon.c

··· 306 306 swiotlbsize = 64 * (1<<20); 307 307 } 308 308 #endif 309 - #ifdef CONFIG_USB_OCTEON_OHCI 309 + #ifdef CONFIG_USB_OHCI_HCD_PLATFORM 310 310 /* OCTEON II ohci is only 32-bit. */ 311 311 if (OCTEON_IS_OCTEON2() && max_addr >= 0x100000000ul) 312 312 swiotlbsize = 64 * (1<<20);

+93 -44

arch/mips/include/asm/asm-eva.h

··· 11 11 #define __ASM_ASM_EVA_H 12 12 13 13 #ifndef __ASSEMBLY__ 14 + 15 + /* Kernel variants */ 16 + 17 + #define kernel_cache(op, base) "cache " op ", " base "\n" 18 + #define kernel_ll(reg, addr) "ll " reg ", " addr "\n" 19 + #define kernel_sc(reg, addr) "sc " reg ", " addr "\n" 20 + #define kernel_lw(reg, addr) "lw " reg ", " addr "\n" 21 + #define kernel_lwl(reg, addr) "lwl " reg ", " addr "\n" 22 + #define kernel_lwr(reg, addr) "lwr " reg ", " addr "\n" 23 + #define kernel_lh(reg, addr) "lh " reg ", " addr "\n" 24 + #define kernel_lb(reg, addr) "lb " reg ", " addr "\n" 25 + #define kernel_lbu(reg, addr) "lbu " reg ", " addr "\n" 26 + #define kernel_sw(reg, addr) "sw " reg ", " addr "\n" 27 + #define kernel_swl(reg, addr) "swl " reg ", " addr "\n" 28 + #define kernel_swr(reg, addr) "swr " reg ", " addr "\n" 29 + #define kernel_sh(reg, addr) "sh " reg ", " addr "\n" 30 + #define kernel_sb(reg, addr) "sb " reg ", " addr "\n" 31 + 32 + #ifdef CONFIG_32BIT 33 + /* 34 + * No 'sd' or 'ld' instructions in 32-bit but the code will 35 + * do the correct thing 36 + */ 37 + #define kernel_sd(reg, addr) user_sw(reg, addr) 38 + #define kernel_ld(reg, addr) user_lw(reg, addr) 39 + #else 40 + #define kernel_sd(reg, addr) "sd " reg", " addr "\n" 41 + #define kernel_ld(reg, addr) "ld " reg", " addr "\n" 42 + #endif /* CONFIG_32BIT */ 43 + 14 44 #ifdef CONFIG_EVA 15 45 16 46 #define __BUILD_EVA_INSN(insn, reg, addr) \ ··· 71 41 72 42 #else 73 43 74 - #define user_cache(op, base) "cache " op ", " base "\n" 75 - #define user_ll(reg, addr) "ll " reg ", " addr "\n" 76 - #define user_sc(reg, addr) "sc " reg ", " addr "\n" 77 - #define user_lw(reg, addr) "lw " reg ", " addr "\n" 78 - #define user_lwl(reg, addr) "lwl " reg ", " addr "\n" 79 - #define user_lwr(reg, addr) "lwr " reg ", " addr "\n" 80 - #define user_lh(reg, addr) "lh " reg ", " addr "\n" 81 - #define user_lb(reg, addr) "lb " reg ", " addr "\n" 82 - #define user_lbu(reg, addr) "lbu " reg ", " addr "\n" 83 - #define user_sw(reg, addr) "sw " reg ", " addr "\n" 84 - #define user_swl(reg, addr) "swl " reg ", " addr "\n" 85 - #define user_swr(reg, addr) "swr " reg ", " addr "\n" 86 - #define user_sh(reg, addr) "sh " reg ", " addr "\n" 87 - #define user_sb(reg, addr) "sb " reg ", " addr "\n" 44 + #define user_cache(op, base) kernel_cache(op, base) 45 + #define user_ll(reg, addr) kernel_ll(reg, addr) 46 + #define user_sc(reg, addr) kernel_sc(reg, addr) 47 + #define user_lw(reg, addr) kernel_lw(reg, addr) 48 + #define user_lwl(reg, addr) kernel_lwl(reg, addr) 49 + #define user_lwr(reg, addr) kernel_lwr(reg, addr) 50 + #define user_lh(reg, addr) kernel_lh(reg, addr) 51 + #define user_lb(reg, addr) kernel_lb(reg, addr) 52 + #define user_lbu(reg, addr) kernel_lbu(reg, addr) 53 + #define user_sw(reg, addr) kernel_sw(reg, addr) 54 + #define user_swl(reg, addr) kernel_swl(reg, addr) 55 + #define user_swr(reg, addr) kernel_swr(reg, addr) 56 + #define user_sh(reg, addr) kernel_sh(reg, addr) 57 + #define user_sb(reg, addr) kernel_sb(reg, addr) 58 + 59 + #ifdef CONFIG_32BIT 60 + #define user_sd(reg, addr) kernel_sw(reg, addr) 61 + #define user_ld(reg, addr) kernel_lw(reg, addr) 62 + #else 63 + #define user_sd(reg, addr) kernel_sd(reg, addr) 64 + #define user_ld(reg, addr) kernel_ld(reg, addr) 65 + #endif /* CONFIG_32BIT */ 66 + 67 + #endif /* CONFIG_EVA */ 68 + 69 + #else /* __ASSEMBLY__ */ 70 + 71 + #define kernel_cache(op, base) cache op, base 72 + #define kernel_ll(reg, addr) ll reg, addr 73 + #define kernel_sc(reg, addr) sc reg, addr 74 + #define kernel_lw(reg, addr) lw reg, addr 75 + #define kernel_lwl(reg, addr) lwl reg, addr 76 + #define kernel_lwr(reg, addr) lwr reg, addr 77 + #define kernel_lh(reg, addr) lh reg, addr 78 + #define kernel_lb(reg, addr) lb reg, addr 79 + #define kernel_lbu(reg, addr) lbu reg, addr 80 + #define kernel_sw(reg, addr) sw reg, addr 81 + #define kernel_swl(reg, addr) swl reg, addr 82 + #define kernel_swr(reg, addr) swr reg, addr 83 + #define kernel_sh(reg, addr) sh reg, addr 84 + #define kernel_sb(reg, addr) sb reg, addr 88 85 89 86 #ifdef CONFIG_32BIT 90 87 /* 91 88 * No 'sd' or 'ld' instructions in 32-bit but the code will 92 89 * do the correct thing 93 90 */ 94 - #define user_sd(reg, addr) user_sw(reg, addr) 95 - #define user_ld(reg, addr) user_lw(reg, addr) 91 + #define kernel_sd(reg, addr) user_sw(reg, addr) 92 + #define kernel_ld(reg, addr) user_lw(reg, addr) 96 93 #else 97 - #define user_sd(reg, addr) "sd " reg", " addr "\n" 98 - #define user_ld(reg, addr) "ld " reg", " addr "\n" 94 + #define kernel_sd(reg, addr) sd reg, addr 95 + #define kernel_ld(reg, addr) ld reg, addr 99 96 #endif /* CONFIG_32BIT */ 100 - 101 - #endif /* CONFIG_EVA */ 102 - 103 - #else /* __ASSEMBLY__ */ 104 97 105 98 #ifdef CONFIG_EVA 106 99 ··· 154 101 #define user_sd(reg, addr) user_sw(reg, addr) 155 102 #else 156 103 157 - #define user_cache(op, base) cache op, base 158 - #define user_ll(reg, addr) ll reg, addr 159 - #define user_sc(reg, addr) sc reg, addr 160 - #define user_lw(reg, addr) lw reg, addr 161 - #define user_lwl(reg, addr) lwl reg, addr 162 - #define user_lwr(reg, addr) lwr reg, addr 163 - #define user_lh(reg, addr) lh reg, addr 164 - #define user_lb(reg, addr) lb reg, addr 165 - #define user_lbu(reg, addr) lbu reg, addr 166 - #define user_sw(reg, addr) sw reg, addr 167 - #define user_swl(reg, addr) swl reg, addr 168 - #define user_swr(reg, addr) swr reg, addr 169 - #define user_sh(reg, addr) sh reg, addr 170 - #define user_sb(reg, addr) sb reg, addr 104 + #define user_cache(op, base) kernel_cache(op, base) 105 + #define user_ll(reg, addr) kernel_ll(reg, addr) 106 + #define user_sc(reg, addr) kernel_sc(reg, addr) 107 + #define user_lw(reg, addr) kernel_lw(reg, addr) 108 + #define user_lwl(reg, addr) kernel_lwl(reg, addr) 109 + #define user_lwr(reg, addr) kernel_lwr(reg, addr) 110 + #define user_lh(reg, addr) kernel_lh(reg, addr) 111 + #define user_lb(reg, addr) kernel_lb(reg, addr) 112 + #define user_lbu(reg, addr) kernel_lbu(reg, addr) 113 + #define user_sw(reg, addr) kernel_sw(reg, addr) 114 + #define user_swl(reg, addr) kernel_swl(reg, addr) 115 + #define user_swr(reg, addr) kernel_swr(reg, addr) 116 + #define user_sh(reg, addr) kernel_sh(reg, addr) 117 + #define user_sb(reg, addr) kernel_sb(reg, addr) 171 118 172 119 #ifdef CONFIG_32BIT 173 - /* 174 - * No 'sd' or 'ld' instructions in 32-bit but the code will 175 - * do the correct thing 176 - */ 177 - #define user_sd(reg, addr) user_sw(reg, addr) 178 - #define user_ld(reg, addr) user_lw(reg, addr) 120 + #define user_sd(reg, addr) kernel_sw(reg, addr) 121 + #define user_ld(reg, addr) kernel_lw(reg, addr) 179 122 #else 180 - #define user_sd(reg, addr) sd reg, addr 181 - #define user_ld(reg, addr) ld reg, addr 123 + #define user_sd(reg, addr) kernel_sd(reg, addr) 124 + #define user_ld(reg, addr) kernel_sd(reg, addr) 182 125 #endif /* CONFIG_32BIT */ 183 126 184 127 #endif /* CONFIG_EVA */

+23 -15

arch/mips/include/asm/cacheflush.h

··· 29 29 * - flush_icache_all() flush the entire instruction cache 30 30 * - flush_data_cache_page() flushes a page from the data cache 31 31 */ 32 + 33 + /* 34 + * This flag is used to indicate that the page pointed to by a pte 35 + * is dirty and requires cleaning before returning it to the user. 36 + */ 37 + #define PG_dcache_dirty PG_arch_1 38 + 39 + #define Page_dcache_dirty(page) \ 40 + test_bit(PG_dcache_dirty, &(page)->flags) 41 + #define SetPageDcacheDirty(page) \ 42 + set_bit(PG_dcache_dirty, &(page)->flags) 43 + #define ClearPageDcacheDirty(page) \ 44 + clear_bit(PG_dcache_dirty, &(page)->flags) 45 + 32 46 extern void (*flush_cache_all)(void); 33 47 extern void (*__flush_cache_all)(void); 34 48 extern void (*flush_cache_mm)(struct mm_struct *mm); ··· 51 37 unsigned long start, unsigned long end); 52 38 extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn); 53 39 extern void __flush_dcache_page(struct page *page); 40 + extern void __flush_icache_page(struct vm_area_struct *vma, struct page *page); 54 41 55 42 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1 56 43 static inline void flush_dcache_page(struct page *page) 57 44 { 58 - if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) 45 + if (cpu_has_dc_aliases) 59 46 __flush_dcache_page(page); 60 - 47 + else if (!cpu_has_ic_fills_f_dc) 48 + SetPageDcacheDirty(page); 61 49 } 62 50 63 51 #define flush_dcache_mmap_lock(mapping) do { } while (0) ··· 77 61 static inline void flush_icache_page(struct vm_area_struct *vma, 78 62 struct page *page) 79 63 { 64 + if (!cpu_has_ic_fills_f_dc && (vma->vm_flags & VM_EXEC) && 65 + Page_dcache_dirty(page)) { 66 + __flush_icache_page(vma, page); 67 + ClearPageDcacheDirty(page); 68 + } 80 69 } 81 70 82 71 extern void (*flush_icache_range)(unsigned long start, unsigned long end); ··· 115 94 extern void (*flush_icache_all)(void); 116 95 extern void (*local_flush_data_cache_page)(void * addr); 117 96 extern void (*flush_data_cache_page)(unsigned long addr); 118 - 119 - /* 120 - * This flag is used to indicate that the page pointed to by a pte 121 - * is dirty and requires cleaning before returning it to the user. 122 - */ 123 - #define PG_dcache_dirty PG_arch_1 124 - 125 - #define Page_dcache_dirty(page) \ 126 - test_bit(PG_dcache_dirty, &(page)->flags) 127 - #define SetPageDcacheDirty(page) \ 128 - set_bit(PG_dcache_dirty, &(page)->flags) 129 - #define ClearPageDcacheDirty(page) \ 130 - clear_bit(PG_dcache_dirty, &(page)->flags) 131 97 132 98 /* Run kernel code uncached, useful for cache probing functions. */ 133 99 unsigned long run_uncached(void *func);

+35 -1

arch/mips/include/asm/cpu-features.h

··· 140 140 # endif 141 141 #endif 142 142 143 + #ifndef cpu_has_xpa 144 + #define cpu_has_xpa (cpu_data[0].options & MIPS_CPU_XPA) 145 + #endif 143 146 #ifndef cpu_has_vtag_icache 144 147 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) 145 148 #endif ··· 242 239 /* MIPSR2 and MIPSR6 have a lot of similarities */ 243 240 #define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r6) 244 241 242 + /* 243 + * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor 244 + * 245 + * Returns non-zero value if the current processor implementation requires 246 + * an IHB instruction to deal with an instruction hazard as per MIPS R2 247 + * architecture specification, zero otherwise. 248 + */ 245 249 #ifndef cpu_has_mips_r2_exec_hazard 246 - #define cpu_has_mips_r2_exec_hazard (cpu_has_mips_r2 | cpu_has_mips_r6) 250 + #define cpu_has_mips_r2_exec_hazard \ 251 + ({ \ 252 + int __res; \ 253 + \ 254 + switch (current_cpu_type()) { \ 255 + case CPU_M14KC: \ 256 + case CPU_74K: \ 257 + case CPU_1074K: \ 258 + case CPU_PROAPTIV: \ 259 + case CPU_P5600: \ 260 + case CPU_M5150: \ 261 + case CPU_QEMU_GENERIC: \ 262 + case CPU_CAVIUM_OCTEON: \ 263 + case CPU_CAVIUM_OCTEON_PLUS: \ 264 + case CPU_CAVIUM_OCTEON2: \ 265 + case CPU_CAVIUM_OCTEON3: \ 266 + __res = 0; \ 267 + break; \ 268 + \ 269 + default: \ 270 + __res = 1; \ 271 + } \ 272 + \ 273 + __res; \ 274 + }) 247 275 #endif 248 276 249 277 /*

+2 -1

arch/mips/include/asm/cpu.h

··· 377 377 #define MIPS_CPU_MAAR 0x400000000ull /* MAAR(I) registers are present */ 378 378 #define MIPS_CPU_FRE 0x800000000ull /* FRE & UFE bits implemented */ 379 379 #define MIPS_CPU_RW_LLB 0x1000000000ull /* LLADDR/LLB writes are allowed */ 380 - #define MIPS_CPU_CDMM 0x2000000000ull /* CPU has Common Device Memory Map */ 380 + #define MIPS_CPU_XPA 0x2000000000ull /* CPU supports Extended Physical Addressing */ 381 + #define MIPS_CPU_CDMM 0x4000000000ull /* CPU has Common Device Memory Map */ 381 382 382 383 /* 383 384 * CPU ASE encodings

+5

arch/mips/include/asm/elf.h

··· 297 297 if (personality(current->personality) != PER_LINUX) \ 298 298 set_personality(PER_LINUX); \ 299 299 \ 300 + clear_thread_flag(TIF_HYBRID_FPREGS); \ 301 + set_thread_flag(TIF_32BIT_FPREGS); \ 302 + \ 300 303 mips_set_personality_fp(state); \ 301 304 \ 302 305 current->thread.abi = &mips_abi; \ ··· 327 324 do { \ 328 325 set_thread_flag(TIF_32BIT_REGS); \ 329 326 set_thread_flag(TIF_32BIT_ADDR); \ 327 + clear_thread_flag(TIF_HYBRID_FPREGS); \ 328 + set_thread_flag(TIF_32BIT_FPREGS); \ 330 329 \ 331 330 mips_set_personality_fp(state); \ 332 331 \

-1

arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h

··· 50 50 #define cpu_has_mips32r2 0 51 51 #define cpu_has_mips64r1 0 52 52 #define cpu_has_mips64r2 1 53 - #define cpu_has_mips_r2_exec_hazard 0 54 53 #define cpu_has_dsp 0 55 54 #define cpu_has_dsp2 0 56 55 #define cpu_has_mipsmt 0

-3

arch/mips/include/asm/octeon/pci-octeon.h

··· 11 11 12 12 #include <linux/pci.h> 13 13 14 - /* Some PCI cards require delays when accessing config space. */ 15 - #define PCI_CONFIG_SPACE_DELAY 10000 16 - 17 14 /* 18 15 * The physical memory base mapped by BAR1. 256MB at the end of the 19 16 * first 4GB.

+9 -6

arch/mips/include/asm/pgtable-32.h

··· 105 105 106 106 #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) 107 107 #define pte_page(x) pfn_to_page(pte_pfn(x)) 108 - #define pte_pfn(x) ((unsigned long)((x).pte_high >> 6)) 108 + #define pte_pfn(x) (((unsigned long)((x).pte_high >> _PFN_SHIFT)) | (unsigned long)((x).pte_low << _PAGE_PRESENT_SHIFT)) 109 109 static inline pte_t 110 110 pfn_pte(unsigned long pfn, pgprot_t prot) 111 111 { 112 112 pte_t pte; 113 - pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f); 114 - pte.pte_low = pgprot_val(prot); 113 + 114 + pte.pte_low = (pfn >> _PAGE_PRESENT_SHIFT) | 115 + (pgprot_val(prot) & ~_PFNX_MASK); 116 + pte.pte_high = (pfn << _PFN_SHIFT) | 117 + (pgprot_val(prot) & ~_PFN_MASK); 115 118 return pte; 116 119 } 117 120 ··· 169 166 #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) 170 167 171 168 /* Swap entries must have VALID and GLOBAL bits cleared. */ 172 - #define __swp_type(x) (((x).val >> 2) & 0x1f) 173 - #define __swp_offset(x) ((x).val >> 7) 174 - #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) | ((offset) << 7) }) 169 + #define __swp_type(x) (((x).val >> 4) & 0x1f) 170 + #define __swp_offset(x) ((x).val >> 9) 171 + #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 4) | ((offset) << 9) }) 175 172 #define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high }) 176 173 #define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val }) 177 174

+66 -30

arch/mips/include/asm/pgtable-bits.h

··· 37 37 /* 38 38 * The following bits are implemented by the TLB hardware 39 39 */ 40 - #define _PAGE_GLOBAL_SHIFT 0 40 + #define _PAGE_NO_EXEC_SHIFT 0 41 + #define _PAGE_NO_EXEC (1 << _PAGE_NO_EXEC_SHIFT) 42 + #define _PAGE_NO_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1) 43 + #define _PAGE_NO_READ (1 << _PAGE_NO_READ_SHIFT) 44 + #define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1) 41 45 #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) 42 46 #define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) 43 47 #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) ··· 53 49 /* 54 50 * The following bits are implemented in software 55 51 */ 56 - #define _PAGE_PRESENT_SHIFT (_CACHE_SHIFT + 3) 52 + #define _PAGE_PRESENT_SHIFT (24) 57 53 #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) 58 54 #define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1) 59 55 #define _PAGE_READ (1 << _PAGE_READ_SHIFT) ··· 65 61 #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) 66 62 67 63 #define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3) 64 + 65 + /* 66 + * Bits for extended EntryLo0/EntryLo1 registers 67 + */ 68 + #define _PFNX_MASK 0xffffff 68 69 69 70 #elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 70 71 ··· 104 95 105 96 #else 106 97 /* 107 - * When using the RI/XI bit support, we have 13 bits of flags below 108 - * the physical address. The RI/XI bits are placed such that a SRL 5 109 - * can strip off the software bits, then a ROTR 2 can move the RI/XI 110 - * into bits [63:62]. This also limits physical address to 56 bits, 111 - * which is more than we need right now. 98 + * Below are the "Normal" R4K cases 112 99 */ 113 100 114 101 /* ··· 112 107 */ 113 108 #define _PAGE_PRESENT_SHIFT 0 114 109 #define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) 115 - #define _PAGE_READ_SHIFT (cpu_has_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1) 116 - #define _PAGE_READ ({BUG_ON(cpu_has_rixi); 1 << _PAGE_READ_SHIFT; }) 110 + /* R2 or later cores check for RI/XI support to determine _PAGE_READ */ 111 + #ifdef CONFIG_CPU_MIPSR2 112 + #define _PAGE_WRITE_SHIFT (_PAGE_PRESENT_SHIFT + 1) 113 + #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) 114 + #else 115 + #define _PAGE_READ_SHIFT (_PAGE_PRESENT_SHIFT + 1) 116 + #define _PAGE_READ (1 << _PAGE_READ_SHIFT) 117 117 #define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) 118 118 #define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) 119 + #endif 119 120 #define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1) 120 121 #define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) 121 122 #define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1) 122 123 #define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) 123 124 124 - #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT 125 - /* huge tlb page */ 125 + #if defined(CONFIG_64BIT) && defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) 126 + /* Huge TLB page */ 126 127 #define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT + 1) 127 128 #define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT) 128 129 #define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT + 1) 129 130 #define _PAGE_SPLITTING (1 << _PAGE_SPLITTING_SHIFT) 131 + 132 + /* Only R2 or newer cores have the XI bit */ 133 + #ifdef CONFIG_CPU_MIPSR2 134 + #define _PAGE_NO_EXEC_SHIFT (_PAGE_SPLITTING_SHIFT + 1) 130 135 #else 131 - #define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT) 132 - #define _PAGE_HUGE ({BUG(); 1; }) /* Dummy value */ 133 - #define _PAGE_SPLITTING_SHIFT (_PAGE_HUGE_SHIFT) 134 - #define _PAGE_SPLITTING ({BUG(); 1; }) /* Dummy value */ 136 + #define _PAGE_GLOBAL_SHIFT (_PAGE_SPLITTING_SHIFT + 1) 137 + #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) 138 + #endif /* CONFIG_CPU_MIPSR2 */ 139 + 140 + #endif /* CONFIG_64BIT && CONFIG_MIPS_HUGE_TLB_SUPPORT */ 141 + 142 + #ifdef CONFIG_CPU_MIPSR2 143 + /* XI - page cannot be executed */ 144 + #ifndef _PAGE_NO_EXEC_SHIFT 145 + #define _PAGE_NO_EXEC_SHIFT (_PAGE_MODIFIED_SHIFT + 1) 135 146 #endif 147 + #define _PAGE_NO_EXEC (cpu_has_rixi ? (1 << _PAGE_NO_EXEC_SHIFT) : 0) 136 148 137 - /* Page cannot be executed */ 138 - #define _PAGE_NO_EXEC_SHIFT (cpu_has_rixi ? _PAGE_SPLITTING_SHIFT + 1 : _PAGE_SPLITTING_SHIFT) 139 - #define _PAGE_NO_EXEC ({BUG_ON(!cpu_has_rixi); 1 << _PAGE_NO_EXEC_SHIFT; }) 140 - 141 - /* Page cannot be read */ 142 - #define _PAGE_NO_READ_SHIFT (cpu_has_rixi ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT) 143 - #define _PAGE_NO_READ ({BUG_ON(!cpu_has_rixi); 1 << _PAGE_NO_READ_SHIFT; }) 149 + /* RI - page cannot be read */ 150 + #define _PAGE_READ_SHIFT (_PAGE_NO_EXEC_SHIFT + 1) 151 + #define _PAGE_READ (cpu_has_rixi ? 0 : (1 << _PAGE_READ_SHIFT)) 152 + #define _PAGE_NO_READ_SHIFT _PAGE_READ_SHIFT 153 + #define _PAGE_NO_READ (cpu_has_rixi ? (1 << _PAGE_READ_SHIFT) : 0) 144 154 145 155 #define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1) 146 156 #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) 157 + 158 + #else /* !CONFIG_CPU_MIPSR2 */ 159 + #define _PAGE_GLOBAL_SHIFT (_PAGE_MODIFIED_SHIFT + 1) 160 + #define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) 161 + #endif /* CONFIG_CPU_MIPSR2 */ 162 + 147 163 #define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) 148 164 #define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) 149 165 #define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1) ··· 176 150 177 151 #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT && defined(CONFIG_CPU_MIPS32) */ 178 152 153 + #ifndef _PAGE_NO_EXEC 154 + #define _PAGE_NO_EXEC 0 155 + #endif 156 + #ifndef _PAGE_NO_READ 157 + #define _PAGE_NO_READ 0 158 + #endif 159 + 179 160 #define _PAGE_SILENT_READ _PAGE_VALID 180 161 #define _PAGE_SILENT_WRITE _PAGE_DIRTY 181 162 182 163 #define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1)) 183 164 184 - #ifndef _PAGE_NO_READ 185 - #define _PAGE_NO_READ ({BUG(); 0; }) 186 - #define _PAGE_NO_READ_SHIFT ({BUG(); 0; }) 187 - #endif 188 - #ifndef _PAGE_NO_EXEC 189 - #define _PAGE_NO_EXEC ({BUG(); 0; }) 190 - #endif 165 + /* 166 + * The final layouts of the PTE bits are: 167 + * 168 + * 64-bit, R1 or earlier: CCC D V G [S H] M A W R P 169 + * 32-bit, R1 or earler: CCC D V G M A W R P 170 + * 64-bit, R2 or later: CCC D V G RI/R XI [S H] M A W P 171 + * 32-bit, R2 or later: CCC D V G RI/R XI M A W P 172 + */ 191 173 192 174 193 175 #ifndef __ASSEMBLY__ ··· 205 171 */ 206 172 static inline uint64_t pte_to_entrylo(unsigned long pte_val) 207 173 { 174 + #ifdef CONFIG_CPU_MIPSR2 208 175 if (cpu_has_rixi) { 209 176 int sa; 210 177 #ifdef CONFIG_32BIT ··· 221 186 return (pte_val >> _PAGE_GLOBAL_SHIFT) | 222 187 ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa); 223 188 } 189 + #endif 224 190 225 191 return pte_val >> _PAGE_GLOBAL_SHIFT; 226 192 } ··· 281 245 #define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT) 282 246 #endif 283 247 284 - #define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED | (cpu_has_rixi ? 0 : _PAGE_READ)) 248 + #define __READABLE (_PAGE_SILENT_READ | _PAGE_READ | _PAGE_ACCESSED) 285 249 #define __WRITEABLE (_PAGE_SILENT_WRITE | _PAGE_WRITE | _PAGE_MODIFIED) 286 250 287 251 #define _PAGE_CHG_MASK (_PAGE_ACCESSED | _PAGE_MODIFIED | \

+38 -45

arch/mips/include/asm/pgtable.h

··· 24 24 struct vm_area_struct; 25 25 26 26 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT) 27 - #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | (cpu_has_rixi ? 0 : _PAGE_READ) | \ 27 + #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | _PAGE_READ | \ 28 28 _page_cachable_default) 29 - #define PAGE_COPY __pgprot(_PAGE_PRESENT | (cpu_has_rixi ? 0 : _PAGE_READ) | \ 30 - (cpu_has_rixi ? _PAGE_NO_EXEC : 0) | _page_cachable_default) 31 - #define PAGE_READONLY __pgprot(_PAGE_PRESENT | (cpu_has_rixi ? 0 : _PAGE_READ) | \ 29 + #define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_NO_EXEC | \ 30 + _page_cachable_default) 31 + #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | \ 32 32 _page_cachable_default) 33 33 #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ 34 34 _PAGE_GLOBAL | _page_cachable_default) 35 35 #define PAGE_KERNEL_NC __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ 36 36 _PAGE_GLOBAL | _CACHE_CACHABLE_NONCOHERENT) 37 - #define PAGE_USERIO __pgprot(_PAGE_PRESENT | (cpu_has_rixi ? 0 : _PAGE_READ) | _PAGE_WRITE | \ 37 + #define PAGE_USERIO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ 38 38 _page_cachable_default) 39 39 #define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \ 40 40 __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED) ··· 127 127 } \ 128 128 } while(0) 129 129 130 - 131 - extern void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, 132 - pte_t pteval); 133 - 134 130 #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) 135 131 136 - #define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL)) 132 + #define pte_none(pte) (!(((pte).pte_high) & ~_PAGE_GLOBAL)) 137 133 #define pte_present(pte) ((pte).pte_low & _PAGE_PRESENT) 138 134 139 135 static inline void set_pte(pte_t *ptep, pte_t pte) ··· 138 142 smp_wmb(); 139 143 ptep->pte_low = pte.pte_low; 140 144 141 - if (pte.pte_low & _PAGE_GLOBAL) { 145 + if (pte.pte_high & _PAGE_GLOBAL) { 142 146 pte_t *buddy = ptep_buddy(ptep); 143 147 /* 144 148 * Make sure the buddy is global too (if it's !none, 145 149 * it better already be global) 146 150 */ 147 - if (pte_none(*buddy)) { 148 - buddy->pte_low |= _PAGE_GLOBAL; 151 + if (pte_none(*buddy)) 149 152 buddy->pte_high |= _PAGE_GLOBAL; 150 - } 151 153 } 152 154 } 155 + #define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval) 153 156 154 157 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 155 158 { ··· 156 161 157 162 htw_stop(); 158 163 /* Preserve global status for the pair */ 159 - if (ptep_buddy(ptep)->pte_low & _PAGE_GLOBAL) 160 - null.pte_low = null.pte_high = _PAGE_GLOBAL; 164 + if (ptep_buddy(ptep)->pte_high & _PAGE_GLOBAL) 165 + null.pte_high = _PAGE_GLOBAL; 161 166 162 167 set_pte_at(mm, addr, ptep, null); 163 168 htw_start(); ··· 187 192 } 188 193 #endif 189 194 } 195 + #define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval) 190 196 191 197 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 192 198 { ··· 238 242 239 243 static inline pte_t pte_wrprotect(pte_t pte) 240 244 { 241 - pte.pte_low &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE); 245 + pte.pte_low &= ~_PAGE_WRITE; 242 246 pte.pte_high &= ~_PAGE_SILENT_WRITE; 243 247 return pte; 244 248 } 245 249 246 250 static inline pte_t pte_mkclean(pte_t pte) 247 251 { 248 - pte.pte_low &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE); 252 + pte.pte_low &= ~_PAGE_MODIFIED; 249 253 pte.pte_high &= ~_PAGE_SILENT_WRITE; 250 254 return pte; 251 255 } 252 256 253 257 static inline pte_t pte_mkold(pte_t pte) 254 258 { 255 - pte.pte_low &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ); 259 + pte.pte_low &= ~_PAGE_ACCESSED; 256 260 pte.pte_high &= ~_PAGE_SILENT_READ; 257 261 return pte; 258 262 } ··· 260 264 static inline pte_t pte_mkwrite(pte_t pte) 261 265 { 262 266 pte.pte_low |= _PAGE_WRITE; 263 - if (pte.pte_low & _PAGE_MODIFIED) { 264 - pte.pte_low |= _PAGE_SILENT_WRITE; 267 + if (pte.pte_low & _PAGE_MODIFIED) 265 268 pte.pte_high |= _PAGE_SILENT_WRITE; 266 - } 267 269 return pte; 268 270 } 269 271 270 272 static inline pte_t pte_mkdirty(pte_t pte) 271 273 { 272 274 pte.pte_low |= _PAGE_MODIFIED; 273 - if (pte.pte_low & _PAGE_WRITE) { 274 - pte.pte_low |= _PAGE_SILENT_WRITE; 275 + if (pte.pte_low & _PAGE_WRITE) 275 276 pte.pte_high |= _PAGE_SILENT_WRITE; 276 - } 277 277 return pte; 278 278 } 279 279 280 280 static inline pte_t pte_mkyoung(pte_t pte) 281 281 { 282 282 pte.pte_low |= _PAGE_ACCESSED; 283 - if (pte.pte_low & _PAGE_READ) { 284 - pte.pte_low |= _PAGE_SILENT_READ; 283 + if (pte.pte_low & _PAGE_READ) 285 284 pte.pte_high |= _PAGE_SILENT_READ; 286 - } 287 285 return pte; 288 286 } 289 287 #else ··· 322 332 static inline pte_t pte_mkyoung(pte_t pte) 323 333 { 324 334 pte_val(pte) |= _PAGE_ACCESSED; 325 - if (cpu_has_rixi) { 326 - if (!(pte_val(pte) & _PAGE_NO_READ)) 327 - pte_val(pte) |= _PAGE_SILENT_READ; 328 - } else { 329 - if (pte_val(pte) & _PAGE_READ) 330 - pte_val(pte) |= _PAGE_SILENT_READ; 331 - } 335 + #ifdef CONFIG_CPU_MIPSR2 336 + if (!(pte_val(pte) & _PAGE_NO_READ)) 337 + pte_val(pte) |= _PAGE_SILENT_READ; 338 + else 339 + #endif 340 + if (pte_val(pte) & _PAGE_READ) 341 + pte_val(pte) |= _PAGE_SILENT_READ; 332 342 return pte; 333 343 } 334 344 ··· 381 391 #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) 382 392 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 383 393 { 384 - pte.pte_low &= _PAGE_CHG_MASK; 394 + pte.pte_low &= (_PAGE_MODIFIED | _PAGE_ACCESSED | _PFNX_MASK); 385 395 pte.pte_high &= (_PFN_MASK | _CACHE_MASK); 386 - pte.pte_low |= pgprot_val(newprot); 387 - pte.pte_high |= pgprot_val(newprot) & ~(_PFN_MASK | _CACHE_MASK); 396 + pte.pte_low |= pgprot_val(newprot) & ~_PFNX_MASK; 397 + pte.pte_high |= pgprot_val(newprot) & ~_PFN_MASK; 388 398 return pte; 389 399 } 390 400 #else ··· 397 407 398 408 extern void __update_tlb(struct vm_area_struct *vma, unsigned long address, 399 409 pte_t pte); 410 + extern void __update_cache(struct vm_area_struct *vma, unsigned long address, 411 + pte_t pte); 400 412 401 413 static inline void update_mmu_cache(struct vm_area_struct *vma, 402 414 unsigned long address, pte_t *ptep) 403 415 { 404 416 pte_t pte = *ptep; 405 417 __update_tlb(vma, address, pte); 418 + __update_cache(vma, address, pte); 406 419 } 407 420 408 421 static inline void update_mmu_cache_pmd(struct vm_area_struct *vma, ··· 527 534 { 528 535 pmd_val(pmd) |= _PAGE_ACCESSED; 529 536 530 - if (cpu_has_rixi) { 531 - if (!(pmd_val(pmd) & _PAGE_NO_READ)) 532 - pmd_val(pmd) |= _PAGE_SILENT_READ; 533 - } else { 534 - if (pmd_val(pmd) & _PAGE_READ) 535 - pmd_val(pmd) |= _PAGE_SILENT_READ; 536 - } 537 + #ifdef CONFIG_CPU_MIPSR2 538 + if (!(pmd_val(pmd) & _PAGE_NO_READ)) 539 + pmd_val(pmd) |= _PAGE_SILENT_READ; 540 + else 541 + #endif 542 + if (pmd_val(pmd) & _PAGE_READ) 543 + pmd_val(pmd) |= _PAGE_SILENT_READ; 537 544 538 545 return pmd; 539 546 }

+45 -44

arch/mips/include/asm/r4kcache.h

··· 12 12 #ifndef _ASM_R4KCACHE_H 13 13 #define _ASM_R4KCACHE_H 14 14 15 + #include <linux/stringify.h> 16 + 15 17 #include <asm/asm.h> 16 18 #include <asm/cacheops.h> 17 19 #include <asm/compiler.h> ··· 346 344 " cache %1, 0x0a0(%0); cache %1, 0x0b0(%0)\n" \ 347 345 " cache %1, 0x0c0(%0); cache %1, 0x0d0(%0)\n" \ 348 346 " cache %1, 0x0e0(%0); cache %1, 0x0f0(%0)\n" \ 349 - " addiu $1, $0, 0x100 \n" \ 347 + " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \ 350 348 " cache %1, 0x000($1); cache %1, 0x010($1)\n" \ 351 349 " cache %1, 0x020($1); cache %1, 0x030($1)\n" \ 352 350 " cache %1, 0x040($1); cache %1, 0x050($1)\n" \ ··· 370 368 " cache %1, 0x040(%0); cache %1, 0x060(%0)\n" \ 371 369 " cache %1, 0x080(%0); cache %1, 0x0a0(%0)\n" \ 372 370 " cache %1, 0x0c0(%0); cache %1, 0x0e0(%0)\n" \ 373 - " addiu $1, %0, 0x100\n" \ 371 + " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \ 374 372 " cache %1, 0x000($1); cache %1, 0x020($1)\n" \ 375 373 " cache %1, 0x040($1); cache %1, 0x060($1)\n" \ 376 374 " cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \ 377 375 " cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n" \ 378 - " addiu $1, $1, 0x100\n" \ 376 + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ 379 377 " cache %1, 0x000($1); cache %1, 0x020($1)\n" \ 380 378 " cache %1, 0x040($1); cache %1, 0x060($1)\n" \ 381 379 " cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \ 382 380 " cache %1, 0x0c0($1); cache %1, 0x0e0($1)\n" \ 383 - " addiu $1, $1, 0x100\n" \ 381 + " "__stringify(LONG_ADDIU)" $1, $1, 0x100\n" \ 384 382 " cache %1, 0x000($1); cache %1, 0x020($1)\n" \ 385 383 " cache %1, 0x040($1); cache %1, 0x060($1)\n" \ 386 384 " cache %1, 0x080($1); cache %1, 0x0a0($1)\n" \ ··· 398 396 " .set noat\n" \ 399 397 " cache %1, 0x000(%0); cache %1, 0x040(%0)\n" \ 400 398 " cache %1, 0x080(%0); cache %1, 0x0c0(%0)\n" \ 401 - " addiu $1, %0, 0x100\n" \ 399 + " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \ 402 400 " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ 403 401 " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ 404 - " addiu $1, %0, 0x100\n" \ 402 + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ 405 403 " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ 406 404 " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ 407 - " addiu $1, %0, 0x100\n" \ 405 + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ 408 406 " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ 409 407 " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ 410 - " addiu $1, %0, 0x100\n" \ 408 + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ 411 409 " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ 412 410 " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ 413 - " addiu $1, %0, 0x100\n" \ 411 + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ 414 412 " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ 415 413 " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ 416 - " addiu $1, %0, 0x100\n" \ 414 + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ 417 415 " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ 418 416 " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ 419 - " addiu $1, %0, 0x100\n" \ 417 + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ 420 418 " cache %1, 0x000($1); cache %1, 0x040($1)\n" \ 421 419 " cache %1, 0x080($1); cache %1, 0x0c0($1)\n" \ 422 420 " .set pop\n" \ ··· 431 429 " .set mips64r6\n" \ 432 430 " .set noat\n" \ 433 431 " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 434 - " addiu $1, %0, 0x100\n" \ 435 - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 436 - " addiu $1, %0, 0x100\n" \ 437 - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 438 - " addiu $1, %0, 0x100\n" \ 439 - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 440 - " addiu $1, %0, 0x100\n" \ 441 - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 442 - " addiu $1, %0, 0x100\n" \ 443 - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 444 - " addiu $1, %0, 0x100\n" \ 445 - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 446 - " addiu $1, %0, 0x100\n" \ 447 - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 448 - " addiu $1, %0, 0x100\n" \ 449 - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 450 - " addiu $1, %0, 0x100\n" \ 451 - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 452 - " addiu $1, %0, 0x100\n" \ 453 - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 454 - " addiu $1, %0, 0x100\n" \ 455 - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 456 - " addiu $1, %0, 0x100\n" \ 457 - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 458 - " addiu $1, %0, 0x100\n" \ 459 - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 460 - " addiu $1, %0, 0x100\n" \ 461 - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 462 - " addiu $1, %0, 0x100\n" \ 463 - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 464 - " addiu $1, %0, 0x100\n" \ 465 - " cache %1, 0x000(%0); cache %1, 0x080(%0)\n" \ 466 - " addiu $1, %0, 0x100\n" \ 432 + " "__stringify(LONG_ADDIU)" $1, %0, 0x100 \n" \ 433 + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ 434 + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ 435 + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ 436 + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ 437 + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ 438 + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ 439 + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ 440 + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ 441 + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ 442 + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ 443 + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ 444 + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ 445 + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ 446 + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ 447 + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ 448 + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ 449 + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ 450 + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ 451 + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ 452 + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ 453 + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ 454 + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ 455 + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ 456 + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ 457 + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ 458 + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ 459 + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ 460 + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ 461 + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ 462 + " "__stringify(LONG_ADDIU)" $1, $1, 0x100 \n" \ 463 + " cache %1, 0x000($1); cache %1, 0x080($1)\n" \ 467 464 " .set pop\n" \ 468 465 : \ 469 466 : "r" (base), \

+1 -1

arch/mips/include/asm/spinlock.h

··· 263 263 if (R10000_LLSC_WAR) { 264 264 __asm__ __volatile__( 265 265 "1: ll %1, %2 # arch_read_unlock \n" 266 - " addiu %1, 1 \n" 266 + " addiu %1, -1 \n" 267 267 " sc %1, %0 \n" 268 268 " beqzl %1, 1b \n" 269 269 : "=" GCC_OFF_SMALL_ASM() (rw->lock), "=&r" (tmp)

+4

arch/mips/kernel/cpu-probe.c

··· 600 600 c->options |= MIPS_CPU_MAAR; 601 601 if (config5 & MIPS_CONF5_LLB) 602 602 c->options |= MIPS_CPU_RW_LLB; 603 + #ifdef CONFIG_XPA 604 + if (config5 & MIPS_CONF5_MVH) 605 + c->options |= MIPS_CPU_XPA; 606 + #endif 603 607 604 608 return config5 & MIPS_CONF_M; 605 609 }

+2 -1

arch/mips/kernel/entry.S

··· 10 10 11 11 #include <asm/asm.h> 12 12 #include <asm/asmmacro.h> 13 + #include <asm/compiler.h> 13 14 #include <asm/regdef.h> 14 15 #include <asm/mipsregs.h> 15 16 #include <asm/stackframe.h> ··· 186 185 * For C code use the inline version named instruction_hazard(). 187 186 */ 188 187 LEAF(mips_ihb) 189 - .set mips32r2 188 + .set MIPS_ISA_LEVEL_RAW 190 189 jr.hb ra 191 190 nop 192 191 END(mips_ihb)

+1

arch/mips/kernel/proc.c

··· 120 120 if (cpu_has_msa) seq_printf(m, "%s", " msa"); 121 121 if (cpu_has_eva) seq_printf(m, "%s", " eva"); 122 122 if (cpu_has_htw) seq_printf(m, "%s", " htw"); 123 + if (cpu_has_xpa) seq_printf(m, "%s", " xpa"); 123 124 seq_printf(m, "\n"); 124 125 125 126 if (cpu_has_mmips) {

+6

arch/mips/kernel/smp-cps.c

··· 88 88 89 89 /* Make core 0 coherent with everything */ 90 90 write_gcr_cl_coherence(0xff); 91 + 92 + #ifdef CONFIG_MIPS_MT_FPAFF 93 + /* If we have an FPU, enroll ourselves in the FPU-full mask */ 94 + if (cpu_has_fpu) 95 + cpu_set(0, mt_fpu_cpumask); 96 + #endif /* CONFIG_MIPS_MT_FPAFF */ 91 97 } 92 98 93 99 static void __init cps_prepare_cpus(unsigned int max_cpus)

+231 -109

arch/mips/kernel/unaligned.c

··· 107 107 extern void show_registers(struct pt_regs *regs); 108 108 109 109 #ifdef __BIG_ENDIAN 110 - #define LoadHW(addr, value, res) \ 110 + #define _LoadHW(addr, value, res, type) \ 111 + do { \ 111 112 __asm__ __volatile__ (".set\tnoat\n" \ 112 - "1:\t"user_lb("%0", "0(%2)")"\n" \ 113 - "2:\t"user_lbu("$1", "1(%2)")"\n\t" \ 113 + "1:\t"type##_lb("%0", "0(%2)")"\n" \ 114 + "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\ 114 115 "sll\t%0, 0x8\n\t" \ 115 116 "or\t%0, $1\n\t" \ 116 117 "li\t%1, 0\n" \ ··· 126 125 STR(PTR)"\t2b, 4b\n\t" \ 127 126 ".previous" \ 128 127 : "=&r" (value), "=r" (res) \ 129 - : "r" (addr), "i" (-EFAULT)); 128 + : "r" (addr), "i" (-EFAULT)); \ 129 + } while(0) 130 130 131 131 #ifndef CONFIG_CPU_MIPSR6 132 - #define LoadW(addr, value, res) \ 132 + #define _LoadW(addr, value, res, type) \ 133 + do { \ 133 134 __asm__ __volatile__ ( \ 134 - "1:\t"user_lwl("%0", "(%2)")"\n" \ 135 - "2:\t"user_lwr("%0", "3(%2)")"\n\t" \ 135 + "1:\t"type##_lwl("%0", "(%2)")"\n" \ 136 + "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\ 136 137 "li\t%1, 0\n" \ 137 138 "3:\n\t" \ 138 139 ".insn\n\t" \ ··· 147 144 STR(PTR)"\t2b, 4b\n\t" \ 148 145 ".previous" \ 149 146 : "=&r" (value), "=r" (res) \ 150 - : "r" (addr), "i" (-EFAULT)); 147 + : "r" (addr), "i" (-EFAULT)); \ 148 + } while(0) 149 + 151 150 #else 152 151 /* MIPSR6 has no lwl instruction */ 153 - #define LoadW(addr, value, res) \ 152 + #define _LoadW(addr, value, res, type) \ 153 + do { \ 154 154 __asm__ __volatile__ ( \ 155 155 ".set\tpush\n" \ 156 156 ".set\tnoat\n\t" \ 157 - "1:"user_lb("%0", "0(%2)")"\n\t" \ 158 - "2:"user_lbu("$1", "1(%2)")"\n\t" \ 157 + "1:"type##_lb("%0", "0(%2)")"\n\t" \ 158 + "2:"type##_lbu("$1", "1(%2)")"\n\t" \ 159 159 "sll\t%0, 0x8\n\t" \ 160 160 "or\t%0, $1\n\t" \ 161 - "3:"user_lbu("$1", "2(%2)")"\n\t" \ 161 + "3:"type##_lbu("$1", "2(%2)")"\n\t" \ 162 162 "sll\t%0, 0x8\n\t" \ 163 163 "or\t%0, $1\n\t" \ 164 - "4:"user_lbu("$1", "3(%2)")"\n\t" \ 164 + "4:"type##_lbu("$1", "3(%2)")"\n\t" \ 165 165 "sll\t%0, 0x8\n\t" \ 166 166 "or\t%0, $1\n\t" \ 167 167 "li\t%1, 0\n" \ ··· 182 176 STR(PTR)"\t4b, 11b\n\t" \ 183 177 ".previous" \ 184 178 : "=&r" (value), "=r" (res) \ 185 - : "r" (addr), "i" (-EFAULT)); 179 + : "r" (addr), "i" (-EFAULT)); \ 180 + } while(0) 181 + 186 182 #endif /* CONFIG_CPU_MIPSR6 */ 187 183 188 - #define LoadHWU(addr, value, res) \ 184 + #define _LoadHWU(addr, value, res, type) \ 185 + do { \ 189 186 __asm__ __volatile__ ( \ 190 187 ".set\tnoat\n" \ 191 - "1:\t"user_lbu("%0", "0(%2)")"\n" \ 192 - "2:\t"user_lbu("$1", "1(%2)")"\n\t" \ 188 + "1:\t"type##_lbu("%0", "0(%2)")"\n" \ 189 + "2:\t"type##_lbu("$1", "1(%2)")"\n\t"\ 193 190 "sll\t%0, 0x8\n\t" \ 194 191 "or\t%0, $1\n\t" \ 195 192 "li\t%1, 0\n" \ ··· 208 199 STR(PTR)"\t2b, 4b\n\t" \ 209 200 ".previous" \ 210 201 : "=&r" (value), "=r" (res) \ 211 - : "r" (addr), "i" (-EFAULT)); 202 + : "r" (addr), "i" (-EFAULT)); \ 203 + } while(0) 212 204 213 205 #ifndef CONFIG_CPU_MIPSR6 214 - #define LoadWU(addr, value, res) \ 206 + #define _LoadWU(addr, value, res, type) \ 207 + do { \ 215 208 __asm__ __volatile__ ( \ 216 - "1:\t"user_lwl("%0", "(%2)")"\n" \ 217 - "2:\t"user_lwr("%0", "3(%2)")"\n\t" \ 209 + "1:\t"type##_lwl("%0", "(%2)")"\n" \ 210 + "2:\t"type##_lwr("%0", "3(%2)")"\n\t"\ 218 211 "dsll\t%0, %0, 32\n\t" \ 219 212 "dsrl\t%0, %0, 32\n\t" \ 220 213 "li\t%1, 0\n" \ ··· 231 220 STR(PTR)"\t2b, 4b\n\t" \ 232 221 ".previous" \ 233 222 : "=&r" (value), "=r" (res) \ 234 - : "r" (addr), "i" (-EFAULT)); 223 + : "r" (addr), "i" (-EFAULT)); \ 224 + } while(0) 235 225 236 - #define LoadDW(addr, value, res) \ 226 + #define _LoadDW(addr, value, res) \ 227 + do { \ 237 228 __asm__ __volatile__ ( \ 238 229 "1:\tldl\t%0, (%2)\n" \ 239 230 "2:\tldr\t%0, 7(%2)\n\t" \ ··· 251 238 STR(PTR)"\t2b, 4b\n\t" \ 252 239 ".previous" \ 253 240 : "=&r" (value), "=r" (res) \ 254 - : "r" (addr), "i" (-EFAULT)); 241 + : "r" (addr), "i" (-EFAULT)); \ 242 + } while(0) 243 + 255 244 #else 256 245 /* MIPSR6 has not lwl and ldl instructions */ 257 - #define LoadWU(addr, value, res) \ 246 + #define _LoadWU(addr, value, res, type) \ 247 + do { \ 258 248 __asm__ __volatile__ ( \ 259 249 ".set\tpush\n\t" \ 260 250 ".set\tnoat\n\t" \ 261 - "1:"user_lbu("%0", "0(%2)")"\n\t" \ 262 - "2:"user_lbu("$1", "1(%2)")"\n\t" \ 251 + "1:"type##_lbu("%0", "0(%2)")"\n\t" \ 252 + "2:"type##_lbu("$1", "1(%2)")"\n\t" \ 263 253 "sll\t%0, 0x8\n\t" \ 264 254 "or\t%0, $1\n\t" \ 265 - "3:"user_lbu("$1", "2(%2)")"\n\t" \ 255 + "3:"type##_lbu("$1", "2(%2)")"\n\t" \ 266 256 "sll\t%0, 0x8\n\t" \ 267 257 "or\t%0, $1\n\t" \ 268 - "4:"user_lbu("$1", "3(%2)")"\n\t" \ 258 + "4:"type##_lbu("$1", "3(%2)")"\n\t" \ 269 259 "sll\t%0, 0x8\n\t" \ 270 260 "or\t%0, $1\n\t" \ 271 261 "li\t%1, 0\n" \ ··· 286 270 STR(PTR)"\t4b, 11b\n\t" \ 287 271 ".previous" \ 288 272 : "=&r" (value), "=r" (res) \ 289 - : "r" (addr), "i" (-EFAULT)); 273 + : "r" (addr), "i" (-EFAULT)); \ 274 + } while(0) 290 275 291 - #define LoadDW(addr, value, res) \ 276 + #define _LoadDW(addr, value, res) \ 277 + do { \ 292 278 __asm__ __volatile__ ( \ 293 279 ".set\tpush\n\t" \ 294 280 ".set\tnoat\n\t" \ ··· 335 317 STR(PTR)"\t8b, 11b\n\t" \ 336 318 ".previous" \ 337 319 : "=&r" (value), "=r" (res) \ 338 - : "r" (addr), "i" (-EFAULT)); 320 + : "r" (addr), "i" (-EFAULT)); \ 321 + } while(0) 322 + 339 323 #endif /* CONFIG_CPU_MIPSR6 */ 340 324 341 325 342 - #define StoreHW(addr, value, res) \ 326 + #define _StoreHW(addr, value, res, type) \ 327 + do { \ 343 328 __asm__ __volatile__ ( \ 344 329 ".set\tnoat\n" \ 345 - "1:\t"user_sb("%1", "1(%2)")"\n" \ 330 + "1:\t"type##_sb("%1", "1(%2)")"\n" \ 346 331 "srl\t$1, %1, 0x8\n" \ 347 - "2:\t"user_sb("$1", "0(%2)")"\n" \ 332 + "2:\t"type##_sb("$1", "0(%2)")"\n" \ 348 333 ".set\tat\n\t" \ 349 334 "li\t%0, 0\n" \ 350 335 "3:\n\t" \ ··· 361 340 STR(PTR)"\t2b, 4b\n\t" \ 362 341 ".previous" \ 363 342 : "=r" (res) \ 364 - : "r" (value), "r" (addr), "i" (-EFAULT)); 343 + : "r" (value), "r" (addr), "i" (-EFAULT));\ 344 + } while(0) 365 345 366 346 #ifndef CONFIG_CPU_MIPSR6 367 - #define StoreW(addr, value, res) \ 347 + #define _StoreW(addr, value, res, type) \ 348 + do { \ 368 349 __asm__ __volatile__ ( \ 369 - "1:\t"user_swl("%1", "(%2)")"\n" \ 370 - "2:\t"user_swr("%1", "3(%2)")"\n\t" \ 350 + "1:\t"type##_swl("%1", "(%2)")"\n" \ 351 + "2:\t"type##_swr("%1", "3(%2)")"\n\t"\ 371 352 "li\t%0, 0\n" \ 372 353 "3:\n\t" \ 373 354 ".insn\n\t" \ ··· 382 359 STR(PTR)"\t2b, 4b\n\t" \ 383 360 ".previous" \ 384 361 : "=r" (res) \ 385 - : "r" (value), "r" (addr), "i" (-EFAULT)); 362 + : "r" (value), "r" (addr), "i" (-EFAULT)); \ 363 + } while(0) 386 364 387 - #define StoreDW(addr, value, res) \ 365 + #define _StoreDW(addr, value, res) \ 366 + do { \ 388 367 __asm__ __volatile__ ( \ 389 368 "1:\tsdl\t%1,(%2)\n" \ 390 369 "2:\tsdr\t%1, 7(%2)\n\t" \ ··· 402 377 STR(PTR)"\t2b, 4b\n\t" \ 403 378 ".previous" \ 404 379 : "=r" (res) \ 405 - : "r" (value), "r" (addr), "i" (-EFAULT)); 380 + : "r" (value), "r" (addr), "i" (-EFAULT)); \ 381 + } while(0) 382 + 406 383 #else 407 384 /* MIPSR6 has no swl and sdl instructions */ 408 - #define StoreW(addr, value, res) \ 385 + #define _StoreW(addr, value, res, type) \ 386 + do { \ 409 387 __asm__ __volatile__ ( \ 410 388 ".set\tpush\n\t" \ 411 389 ".set\tnoat\n\t" \ 412 - "1:"user_sb("%1", "3(%2)")"\n\t" \ 390 + "1:"type##_sb("%1", "3(%2)")"\n\t" \ 413 391 "srl\t$1, %1, 0x8\n\t" \ 414 - "2:"user_sb("$1", "2(%2)")"\n\t" \ 392 + "2:"type##_sb("$1", "2(%2)")"\n\t" \ 415 393 "srl\t$1, $1, 0x8\n\t" \ 416 - "3:"user_sb("$1", "1(%2)")"\n\t" \ 394 + "3:"type##_sb("$1", "1(%2)")"\n\t" \ 417 395 "srl\t$1, $1, 0x8\n\t" \ 418 - "4:"user_sb("$1", "0(%2)")"\n\t" \ 396 + "4:"type##_sb("$1", "0(%2)")"\n\t" \ 419 397 ".set\tpop\n\t" \ 420 398 "li\t%0, 0\n" \ 421 399 "10:\n\t" \ ··· 435 407 ".previous" \ 436 408 : "=&r" (res) \ 437 409 : "r" (value), "r" (addr), "i" (-EFAULT) \ 438 - : "memory"); 410 + : "memory"); \ 411 + } while(0) 439 412 440 413 #define StoreDW(addr, value, res) \ 414 + do { \ 441 415 __asm__ __volatile__ ( \ 442 416 ".set\tpush\n\t" \ 443 417 ".set\tnoat\n\t" \ ··· 479 449 ".previous" \ 480 450 : "=&r" (res) \ 481 451 : "r" (value), "r" (addr), "i" (-EFAULT) \ 482 - : "memory"); 452 + : "memory"); \ 453 + } while(0) 454 + 483 455 #endif /* CONFIG_CPU_MIPSR6 */ 484 456 485 457 #else /* __BIG_ENDIAN */ 486 458 487 - #define LoadHW(addr, value, res) \ 459 + #define _LoadHW(addr, value, res, type) \ 460 + do { \ 488 461 __asm__ __volatile__ (".set\tnoat\n" \ 489 - "1:\t"user_lb("%0", "1(%2)")"\n" \ 490 - "2:\t"user_lbu("$1", "0(%2)")"\n\t" \ 462 + "1:\t"type##_lb("%0", "1(%2)")"\n" \ 463 + "2:\t"type##_lbu("$1", "0(%2)")"\n\t"\ 491 464 "sll\t%0, 0x8\n\t" \ 492 465 "or\t%0, $1\n\t" \ 493 466 "li\t%1, 0\n" \ ··· 505 472 STR(PTR)"\t2b, 4b\n\t" \ 506 473 ".previous" \ 507 474 : "=&r" (value), "=r" (res) \ 508 - : "r" (addr), "i" (-EFAULT)); 475 + : "r" (addr), "i" (-EFAULT)); \ 476 + } while(0) 509 477 510 478 #ifndef CONFIG_CPU_MIPSR6 511 - #define LoadW(addr, value, res) \ 479 + #define _LoadW(addr, value, res, type) \ 480 + do { \ 512 481 __asm__ __volatile__ ( \ 513 - "1:\t"user_lwl("%0", "3(%2)")"\n" \ 514 - "2:\t"user_lwr("%0", "(%2)")"\n\t" \ 482 + "1:\t"type##_lwl("%0", "3(%2)")"\n" \ 483 + "2:\t"type##_lwr("%0", "(%2)")"\n\t"\ 515 484 "li\t%1, 0\n" \ 516 485 "3:\n\t" \ 517 486 ".insn\n\t" \ ··· 526 491 STR(PTR)"\t2b, 4b\n\t" \ 527 492 ".previous" \ 528 493 : "=&r" (value), "=r" (res) \ 529 - : "r" (addr), "i" (-EFAULT)); 494 + : "r" (addr), "i" (-EFAULT)); \ 495 + } while(0) 496 + 530 497 #else 531 498 /* MIPSR6 has no lwl instruction */ 532 - #define LoadW(addr, value, res) \ 499 + #define _LoadW(addr, value, res, type) \ 500 + do { \ 533 501 __asm__ __volatile__ ( \ 534 502 ".set\tpush\n" \ 535 503 ".set\tnoat\n\t" \ 536 - "1:"user_lb("%0", "3(%2)")"\n\t" \ 537 - "2:"user_lbu("$1", "2(%2)")"\n\t" \ 504 + "1:"type##_lb("%0", "3(%2)")"\n\t" \ 505 + "2:"type##_lbu("$1", "2(%2)")"\n\t" \ 538 506 "sll\t%0, 0x8\n\t" \ 539 507 "or\t%0, $1\n\t" \ 540 - "3:"user_lbu("$1", "1(%2)")"\n\t" \ 508 + "3:"type##_lbu("$1", "1(%2)")"\n\t" \ 541 509 "sll\t%0, 0x8\n\t" \ 542 510 "or\t%0, $1\n\t" \ 543 - "4:"user_lbu("$1", "0(%2)")"\n\t" \ 511 + "4:"type##_lbu("$1", "0(%2)")"\n\t" \ 544 512 "sll\t%0, 0x8\n\t" \ 545 513 "or\t%0, $1\n\t" \ 546 514 "li\t%1, 0\n" \ ··· 561 523 STR(PTR)"\t4b, 11b\n\t" \ 562 524 ".previous" \ 563 525 : "=&r" (value), "=r" (res) \ 564 - : "r" (addr), "i" (-EFAULT)); 526 + : "r" (addr), "i" (-EFAULT)); \ 527 + } while(0) 528 + 565 529 #endif /* CONFIG_CPU_MIPSR6 */ 566 530 567 531 568 - #define LoadHWU(addr, value, res) \ 532 + #define _LoadHWU(addr, value, res, type) \ 533 + do { \ 569 534 __asm__ __volatile__ ( \ 570 535 ".set\tnoat\n" \ 571 - "1:\t"user_lbu("%0", "1(%2)")"\n" \ 572 - "2:\t"user_lbu("$1", "0(%2)")"\n\t" \ 536 + "1:\t"type##_lbu("%0", "1(%2)")"\n" \ 537 + "2:\t"type##_lbu("$1", "0(%2)")"\n\t"\ 573 538 "sll\t%0, 0x8\n\t" \ 574 539 "or\t%0, $1\n\t" \ 575 540 "li\t%1, 0\n" \ ··· 588 547 STR(PTR)"\t2b, 4b\n\t" \ 589 548 ".previous" \ 590 549 : "=&r" (value), "=r" (res) \ 591 - : "r" (addr), "i" (-EFAULT)); 550 + : "r" (addr), "i" (-EFAULT)); \ 551 + } while(0) 592 552 593 553 #ifndef CONFIG_CPU_MIPSR6 594 - #define LoadWU(addr, value, res) \ 554 + #define _LoadWU(addr, value, res, type) \ 555 + do { \ 595 556 __asm__ __volatile__ ( \ 596 - "1:\t"user_lwl("%0", "3(%2)")"\n" \ 597 - "2:\t"user_lwr("%0", "(%2)")"\n\t" \ 557 + "1:\t"type##_lwl("%0", "3(%2)")"\n" \ 558 + "2:\t"type##_lwr("%0", "(%2)")"\n\t"\ 598 559 "dsll\t%0, %0, 32\n\t" \ 599 560 "dsrl\t%0, %0, 32\n\t" \ 600 561 "li\t%1, 0\n" \ ··· 611 568 STR(PTR)"\t2b, 4b\n\t" \ 612 569 ".previous" \ 613 570 : "=&r" (value), "=r" (res) \ 614 - : "r" (addr), "i" (-EFAULT)); 571 + : "r" (addr), "i" (-EFAULT)); \ 572 + } while(0) 615 573 616 - #define LoadDW(addr, value, res) \ 574 + #define _LoadDW(addr, value, res) \ 575 + do { \ 617 576 __asm__ __volatile__ ( \ 618 577 "1:\tldl\t%0, 7(%2)\n" \ 619 578 "2:\tldr\t%0, (%2)\n\t" \ ··· 631 586 STR(PTR)"\t2b, 4b\n\t" \ 632 587 ".previous" \ 633 588 : "=&r" (value), "=r" (res) \ 634 - : "r" (addr), "i" (-EFAULT)); 589 + : "r" (addr), "i" (-EFAULT)); \ 590 + } while(0) 591 + 635 592 #else 636 593 /* MIPSR6 has not lwl and ldl instructions */ 637 - #define LoadWU(addr, value, res) \ 594 + #define _LoadWU(addr, value, res, type) \ 595 + do { \ 638 596 __asm__ __volatile__ ( \ 639 597 ".set\tpush\n\t" \ 640 598 ".set\tnoat\n\t" \ 641 - "1:"user_lbu("%0", "3(%2)")"\n\t" \ 642 - "2:"user_lbu("$1", "2(%2)")"\n\t" \ 599 + "1:"type##_lbu("%0", "3(%2)")"\n\t" \ 600 + "2:"type##_lbu("$1", "2(%2)")"\n\t" \ 643 601 "sll\t%0, 0x8\n\t" \ 644 602 "or\t%0, $1\n\t" \ 645 - "3:"user_lbu("$1", "1(%2)")"\n\t" \ 603 + "3:"type##_lbu("$1", "1(%2)")"\n\t" \ 646 604 "sll\t%0, 0x8\n\t" \ 647 605 "or\t%0, $1\n\t" \ 648 - "4:"user_lbu("$1", "0(%2)")"\n\t" \ 606 + "4:"type##_lbu("$1", "0(%2)")"\n\t" \ 649 607 "sll\t%0, 0x8\n\t" \ 650 608 "or\t%0, $1\n\t" \ 651 609 "li\t%1, 0\n" \ ··· 666 618 STR(PTR)"\t4b, 11b\n\t" \ 667 619 ".previous" \ 668 620 : "=&r" (value), "=r" (res) \ 669 - : "r" (addr), "i" (-EFAULT)); 621 + : "r" (addr), "i" (-EFAULT)); \ 622 + } while(0) 670 623 671 - #define LoadDW(addr, value, res) \ 624 + #define _LoadDW(addr, value, res) \ 625 + do { \ 672 626 __asm__ __volatile__ ( \ 673 627 ".set\tpush\n\t" \ 674 628 ".set\tnoat\n\t" \ ··· 715 665 STR(PTR)"\t8b, 11b\n\t" \ 716 666 ".previous" \ 717 667 : "=&r" (value), "=r" (res) \ 718 - : "r" (addr), "i" (-EFAULT)); 668 + : "r" (addr), "i" (-EFAULT)); \ 669 + } while(0) 719 670 #endif /* CONFIG_CPU_MIPSR6 */ 720 671 721 - #define StoreHW(addr, value, res) \ 672 + #define _StoreHW(addr, value, res, type) \ 673 + do { \ 722 674 __asm__ __volatile__ ( \ 723 675 ".set\tnoat\n" \ 724 - "1:\t"user_sb("%1", "0(%2)")"\n" \ 676 + "1:\t"type##_sb("%1", "0(%2)")"\n" \ 725 677 "srl\t$1,%1, 0x8\n" \ 726 - "2:\t"user_sb("$1", "1(%2)")"\n" \ 678 + "2:\t"type##_sb("$1", "1(%2)")"\n" \ 727 679 ".set\tat\n\t" \ 728 680 "li\t%0, 0\n" \ 729 681 "3:\n\t" \ ··· 739 687 STR(PTR)"\t2b, 4b\n\t" \ 740 688 ".previous" \ 741 689 : "=r" (res) \ 742 - : "r" (value), "r" (addr), "i" (-EFAULT)); 690 + : "r" (value), "r" (addr), "i" (-EFAULT));\ 691 + } while(0) 692 + 743 693 #ifndef CONFIG_CPU_MIPSR6 744 - #define StoreW(addr, value, res) \ 694 + #define _StoreW(addr, value, res, type) \ 695 + do { \ 745 696 __asm__ __volatile__ ( \ 746 - "1:\t"user_swl("%1", "3(%2)")"\n" \ 747 - "2:\t"user_swr("%1", "(%2)")"\n\t" \ 697 + "1:\t"type##_swl("%1", "3(%2)")"\n" \ 698 + "2:\t"type##_swr("%1", "(%2)")"\n\t"\ 748 699 "li\t%0, 0\n" \ 749 700 "3:\n\t" \ 750 701 ".insn\n\t" \ ··· 760 705 STR(PTR)"\t2b, 4b\n\t" \ 761 706 ".previous" \ 762 707 : "=r" (res) \ 763 - : "r" (value), "r" (addr), "i" (-EFAULT)); 708 + : "r" (value), "r" (addr), "i" (-EFAULT)); \ 709 + } while(0) 764 710 765 - #define StoreDW(addr, value, res) \ 711 + #define _StoreDW(addr, value, res) \ 712 + do { \ 766 713 __asm__ __volatile__ ( \ 767 714 "1:\tsdl\t%1, 7(%2)\n" \ 768 715 "2:\tsdr\t%1, (%2)\n\t" \ ··· 780 723 STR(PTR)"\t2b, 4b\n\t" \ 781 724 ".previous" \ 782 725 : "=r" (res) \ 783 - : "r" (value), "r" (addr), "i" (-EFAULT)); 726 + : "r" (value), "r" (addr), "i" (-EFAULT)); \ 727 + } while(0) 728 + 784 729 #else 785 730 /* MIPSR6 has no swl and sdl instructions */ 786 - #define StoreW(addr, value, res) \ 731 + #define _StoreW(addr, value, res, type) \ 732 + do { \ 787 733 __asm__ __volatile__ ( \ 788 734 ".set\tpush\n\t" \ 789 735 ".set\tnoat\n\t" \ 790 - "1:"user_sb("%1", "0(%2)")"\n\t" \ 736 + "1:"type##_sb("%1", "0(%2)")"\n\t" \ 791 737 "srl\t$1, %1, 0x8\n\t" \ 792 - "2:"user_sb("$1", "1(%2)")"\n\t" \ 738 + "2:"type##_sb("$1", "1(%2)")"\n\t" \ 793 739 "srl\t$1, $1, 0x8\n\t" \ 794 - "3:"user_sb("$1", "2(%2)")"\n\t" \ 740 + "3:"type##_sb("$1", "2(%2)")"\n\t" \ 795 741 "srl\t$1, $1, 0x8\n\t" \ 796 - "4:"user_sb("$1", "3(%2)")"\n\t" \ 742 + "4:"type##_sb("$1", "3(%2)")"\n\t" \ 797 743 ".set\tpop\n\t" \ 798 744 "li\t%0, 0\n" \ 799 745 "10:\n\t" \ ··· 813 753 ".previous" \ 814 754 : "=&r" (res) \ 815 755 : "r" (value), "r" (addr), "i" (-EFAULT) \ 816 - : "memory"); 756 + : "memory"); \ 757 + } while(0) 817 758 818 - #define StoreDW(addr, value, res) \ 759 + #define _StoreDW(addr, value, res) \ 760 + do { \ 819 761 __asm__ __volatile__ ( \ 820 762 ".set\tpush\n\t" \ 821 763 ".set\tnoat\n\t" \ ··· 857 795 ".previous" \ 858 796 : "=&r" (res) \ 859 797 : "r" (value), "r" (addr), "i" (-EFAULT) \ 860 - : "memory"); 798 + : "memory"); \ 799 + } while(0) 800 + 861 801 #endif /* CONFIG_CPU_MIPSR6 */ 862 802 #endif 803 + 804 + #define LoadHWU(addr, value, res) _LoadHWU(addr, value, res, kernel) 805 + #define LoadHWUE(addr, value, res) _LoadHWU(addr, value, res, user) 806 + #define LoadWU(addr, value, res) _LoadWU(addr, value, res, kernel) 807 + #define LoadWUE(addr, value, res) _LoadWU(addr, value, res, user) 808 + #define LoadHW(addr, value, res) _LoadHW(addr, value, res, kernel) 809 + #define LoadHWE(addr, value, res) _LoadHW(addr, value, res, user) 810 + #define LoadW(addr, value, res) _LoadW(addr, value, res, kernel) 811 + #define LoadWE(addr, value, res) _LoadW(addr, value, res, user) 812 + #define LoadDW(addr, value, res) _LoadDW(addr, value, res) 813 + 814 + #define StoreHW(addr, value, res) _StoreHW(addr, value, res, kernel) 815 + #define StoreHWE(addr, value, res) _StoreHW(addr, value, res, user) 816 + #define StoreW(addr, value, res) _StoreW(addr, value, res, kernel) 817 + #define StoreWE(addr, value, res) _StoreW(addr, value, res, user) 818 + #define StoreDW(addr, value, res) _StoreDW(addr, value, res) 863 819 864 820 static void emulate_load_store_insn(struct pt_regs *regs, 865 821 void __user *addr, unsigned int __user *pc) ··· 950 870 set_fs(seg); 951 871 goto sigbus; 952 872 } 953 - LoadHW(addr, value, res); 873 + LoadHWE(addr, value, res); 954 874 if (res) { 955 875 set_fs(seg); 956 876 goto fault; ··· 963 883 set_fs(seg); 964 884 goto sigbus; 965 885 } 966 - LoadW(addr, value, res); 886 + LoadWE(addr, value, res); 967 887 if (res) { 968 888 set_fs(seg); 969 889 goto fault; ··· 976 896 set_fs(seg); 977 897 goto sigbus; 978 898 } 979 - LoadHWU(addr, value, res); 899 + LoadHWUE(addr, value, res); 980 900 if (res) { 981 901 set_fs(seg); 982 902 goto fault; ··· 991 911 } 992 912 compute_return_epc(regs); 993 913 value = regs->regs[insn.spec3_format.rt]; 994 - StoreHW(addr, value, res); 914 + StoreHWE(addr, value, res); 995 915 if (res) { 996 916 set_fs(seg); 997 917 goto fault; ··· 1004 924 } 1005 925 compute_return_epc(regs); 1006 926 value = regs->regs[insn.spec3_format.rt]; 1007 - StoreW(addr, value, res); 927 + StoreWE(addr, value, res); 1008 928 if (res) { 1009 929 set_fs(seg); 1010 930 goto fault; ··· 1021 941 if (!access_ok(VERIFY_READ, addr, 2)) 1022 942 goto sigbus; 1023 943 1024 - LoadHW(addr, value, res); 944 + if (config_enabled(CONFIG_EVA)) { 945 + if (segment_eq(get_fs(), get_ds())) 946 + LoadHW(addr, value, res); 947 + else 948 + LoadHWE(addr, value, res); 949 + } else { 950 + LoadHW(addr, value, res); 951 + } 952 + 1025 953 if (res) 1026 954 goto fault; 1027 955 compute_return_epc(regs); ··· 1040 952 if (!access_ok(VERIFY_READ, addr, 4)) 1041 953 goto sigbus; 1042 954 1043 - LoadW(addr, value, res); 955 + if (config_enabled(CONFIG_EVA)) { 956 + if (segment_eq(get_fs(), get_ds())) 957 + LoadW(addr, value, res); 958 + else 959 + LoadWE(addr, value, res); 960 + } else { 961 + LoadW(addr, value, res); 962 + } 963 + 1044 964 if (res) 1045 965 goto fault; 1046 966 compute_return_epc(regs); ··· 1059 963 if (!access_ok(VERIFY_READ, addr, 2)) 1060 964 goto sigbus; 1061 965 1062 - LoadHWU(addr, value, res); 966 + if (config_enabled(CONFIG_EVA)) { 967 + if (segment_eq(get_fs(), get_ds())) 968 + LoadHWU(addr, value, res); 969 + else 970 + LoadHWUE(addr, value, res); 971 + } else { 972 + LoadHWU(addr, value, res); 973 + } 974 + 1063 975 if (res) 1064 976 goto fault; 1065 977 compute_return_epc(regs); ··· 1126 1022 1127 1023 compute_return_epc(regs); 1128 1024 value = regs->regs[insn.i_format.rt]; 1129 - StoreHW(addr, value, res); 1025 + 1026 + if (config_enabled(CONFIG_EVA)) { 1027 + if (segment_eq(get_fs(), get_ds())) 1028 + StoreHW(addr, value, res); 1029 + else 1030 + StoreHWE(addr, value, res); 1031 + } else { 1032 + StoreHW(addr, value, res); 1033 + } 1034 + 1130 1035 if (res) 1131 1036 goto fault; 1132 1037 break; ··· 1146 1033 1147 1034 compute_return_epc(regs); 1148 1035 value = regs->regs[insn.i_format.rt]; 1149 - StoreW(addr, value, res); 1036 + 1037 + if (config_enabled(CONFIG_EVA)) { 1038 + if (segment_eq(get_fs(), get_ds())) 1039 + StoreW(addr, value, res); 1040 + else 1041 + StoreWE(addr, value, res); 1042 + } else { 1043 + StoreW(addr, value, res); 1044 + } 1045 + 1150 1046 if (res) 1151 1047 goto fault; 1152 1048 break;

+1

arch/mips/loongson/loongson-3/irq.c

··· 44 44 45 45 static struct irqaction cascade_irqaction = { 46 46 .handler = no_action, 47 + .flags = IRQF_NO_SUSPEND, 47 48 .name = "cascade", 48 49 }; 49 50

+21 -20

arch/mips/mm/cache.c

··· 119 119 120 120 EXPORT_SYMBOL(__flush_anon_page); 121 121 122 - static void mips_flush_dcache_from_pte(pte_t pteval, unsigned long address) 122 + void __flush_icache_page(struct vm_area_struct *vma, struct page *page) 123 123 { 124 - struct page *page; 125 - unsigned long pfn = pte_pfn(pteval); 124 + unsigned long addr; 126 125 127 - if (unlikely(!pfn_valid(pfn))) 126 + if (PageHighMem(page)) 128 127 return; 129 128 129 + addr = (unsigned long) page_address(page); 130 + flush_data_cache_page(addr); 131 + } 132 + EXPORT_SYMBOL_GPL(__flush_icache_page); 133 + 134 + void __update_cache(struct vm_area_struct *vma, unsigned long address, 135 + pte_t pte) 136 + { 137 + struct page *page; 138 + unsigned long pfn, addr; 139 + int exec = (vma->vm_flags & VM_EXEC) && !cpu_has_ic_fills_f_dc; 140 + 141 + pfn = pte_pfn(pte); 142 + if (unlikely(!pfn_valid(pfn))) 143 + return; 130 144 page = pfn_to_page(pfn); 131 145 if (page_mapping(page) && Page_dcache_dirty(page)) { 132 - unsigned long page_addr = (unsigned long) page_address(page); 133 - 134 - if (!cpu_has_ic_fills_f_dc || 135 - pages_do_alias(page_addr, address & PAGE_MASK)) 136 - flush_data_cache_page(page_addr); 146 + addr = (unsigned long) page_address(page); 147 + if (exec || pages_do_alias(addr, address & PAGE_MASK)) 148 + flush_data_cache_page(addr); 137 149 ClearPageDcacheDirty(page); 138 150 } 139 - } 140 - 141 - void set_pte_at(struct mm_struct *mm, unsigned long addr, 142 - pte_t *ptep, pte_t pteval) 143 - { 144 - if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc) { 145 - if (pte_present(pteval)) 146 - mips_flush_dcache_from_pte(pteval, addr); 147 - } 148 - 149 - set_pte(ptep, pteval); 150 151 } 151 152 152 153 unsigned long _page_cachable_default;

+6 -1

arch/mips/mm/init.c

··· 96 96 vaddr = __fix_to_virt(FIX_CMAP_END - idx); 97 97 pte = mk_pte(page, prot); 98 98 #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) 99 - entrylo = pte.pte_high; 99 + entrylo = pte_to_entrylo(pte.pte_high); 100 100 #else 101 101 entrylo = pte_to_entrylo(pte_val(pte)); 102 102 #endif ··· 106 106 write_c0_entryhi(vaddr & (PAGE_MASK << 1)); 107 107 write_c0_entrylo0(entrylo); 108 108 write_c0_entrylo1(entrylo); 109 + #ifdef CONFIG_XPA 110 + entrylo = (pte.pte_low & _PFNX_MASK); 111 + writex_c0_entrylo0(entrylo); 112 + writex_c0_entrylo1(entrylo); 113 + #endif 109 114 tlbidx = read_c0_wired(); 110 115 write_c0_wired(tlbidx + 1); 111 116 write_c0_index(tlbidx);

+12

arch/mips/mm/tlb-r4k.c

··· 333 333 ptep = pte_offset_map(pmdp, address); 334 334 335 335 #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) 336 + #ifdef CONFIG_XPA 337 + write_c0_entrylo0(pte_to_entrylo(ptep->pte_high)); 338 + writex_c0_entrylo0(ptep->pte_low & _PFNX_MASK); 339 + ptep++; 340 + write_c0_entrylo1(pte_to_entrylo(ptep->pte_high)); 341 + writex_c0_entrylo1(ptep->pte_low & _PFNX_MASK); 342 + #else 336 343 write_c0_entrylo0(ptep->pte_high); 337 344 ptep++; 338 345 write_c0_entrylo1(ptep->pte_high); 346 + #endif 339 347 #else 340 348 write_c0_entrylo0(pte_to_entrylo(pte_val(*ptep++))); 341 349 write_c0_entrylo1(pte_to_entrylo(pte_val(*ptep))); ··· 363 355 void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, 364 356 unsigned long entryhi, unsigned long pagemask) 365 357 { 358 + #ifdef CONFIG_XPA 359 + panic("Broken for XPA kernels"); 360 + #else 366 361 unsigned long flags; 367 362 unsigned long wired; 368 363 unsigned long old_pagemask; ··· 394 383 write_c0_pagemask(old_pagemask); 395 384 local_flush_tlb_all(); 396 385 local_irq_restore(flags); 386 + #endif 397 387 } 398 388 399 389 #ifdef CONFIG_TRANSPARENT_HUGEPAGE

+81 -34

arch/mips/mm/tlbex.c

··· 35 35 #include <asm/uasm.h> 36 36 #include <asm/setup.h> 37 37 38 + static int __cpuinitdata mips_xpa_disabled; 39 + 40 + static int __init xpa_disable(char *s) 41 + { 42 + mips_xpa_disabled = 1; 43 + 44 + return 1; 45 + } 46 + 47 + __setup("noxpa", xpa_disable); 48 + 38 49 /* 39 50 * TLB load/store/modify handlers. 40 51 * ··· 242 231 pr_define("_PAGE_HUGE_SHIFT %d\n", _PAGE_HUGE_SHIFT); 243 232 pr_define("_PAGE_SPLITTING_SHIFT %d\n", _PAGE_SPLITTING_SHIFT); 244 233 #endif 234 + #ifdef CONFIG_CPU_MIPSR2 245 235 if (cpu_has_rixi) { 246 236 #ifdef _PAGE_NO_EXEC_SHIFT 247 237 pr_define("_PAGE_NO_EXEC_SHIFT %d\n", _PAGE_NO_EXEC_SHIFT); 248 - #endif 249 - #ifdef _PAGE_NO_READ_SHIFT 250 238 pr_define("_PAGE_NO_READ_SHIFT %d\n", _PAGE_NO_READ_SHIFT); 251 239 #endif 252 240 } 241 + #endif 253 242 pr_define("_PAGE_GLOBAL_SHIFT %d\n", _PAGE_GLOBAL_SHIFT); 254 243 pr_define("_PAGE_VALID_SHIFT %d\n", _PAGE_VALID_SHIFT); 255 244 pr_define("_PAGE_DIRTY_SHIFT %d\n", _PAGE_DIRTY_SHIFT); ··· 512 501 case tlb_indexed: tlbw = uasm_i_tlbwi; break; 513 502 } 514 503 515 - if (cpu_has_mips_r2_exec_hazard) { 516 - /* 517 - * The architecture spec says an ehb is required here, 518 - * but a number of cores do not have the hazard and 519 - * using an ehb causes an expensive pipeline stall. 520 - */ 521 - switch (current_cpu_type()) { 522 - case CPU_M14KC: 523 - case CPU_74K: 524 - case CPU_1074K: 525 - case CPU_PROAPTIV: 526 - case CPU_P5600: 527 - case CPU_M5150: 528 - case CPU_QEMU_GENERIC: 529 - break; 530 - 531 - default: 504 + if (cpu_has_mips_r2_r6) { 505 + if (cpu_has_mips_r2_exec_hazard) 532 506 uasm_i_ehb(p); 533 - break; 534 - } 535 507 tlbw(p); 536 508 return; 537 509 } ··· 1022 1028 } else { 1023 1029 int pte_off_even = sizeof(pte_t) / 2; 1024 1030 int pte_off_odd = pte_off_even + sizeof(pte_t); 1031 + #ifdef CONFIG_XPA 1032 + const int scratch = 1; /* Our extra working register */ 1025 1033 1026 - /* The pte entries are pre-shifted */ 1027 - uasm_i_lw(p, tmp, pte_off_even, ptep); /* get even pte */ 1028 - UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ 1029 - uasm_i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */ 1030 - UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ 1034 + uasm_i_addu(p, scratch, 0, ptep); 1035 + #endif 1036 + uasm_i_lw(p, tmp, pte_off_even, ptep); /* even pte */ 1037 + uasm_i_lw(p, ptep, pte_off_odd, ptep); /* odd pte */ 1038 + UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); 1039 + UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); 1040 + UASM_i_MTC0(p, tmp, C0_ENTRYLO0); 1041 + UASM_i_MTC0(p, ptep, C0_ENTRYLO1); 1042 + #ifdef CONFIG_XPA 1043 + uasm_i_lw(p, tmp, 0, scratch); 1044 + uasm_i_lw(p, ptep, sizeof(pte_t), scratch); 1045 + uasm_i_lui(p, scratch, 0xff); 1046 + uasm_i_ori(p, scratch, scratch, 0xffff); 1047 + uasm_i_and(p, tmp, scratch, tmp); 1048 + uasm_i_and(p, ptep, scratch, ptep); 1049 + uasm_i_mthc0(p, tmp, C0_ENTRYLO0); 1050 + uasm_i_mthc0(p, ptep, C0_ENTRYLO1); 1051 + #endif 1031 1052 } 1032 1053 #else 1033 1054 UASM_i_LW(p, tmp, 0, ptep); /* get even pte */ ··· 1543 1534 { 1544 1535 #ifdef CONFIG_PHYS_ADDR_T_64BIT 1545 1536 unsigned int hwmode = mode & (_PAGE_VALID | _PAGE_DIRTY); 1546 - #endif 1547 1537 1538 + if (!cpu_has_64bits) { 1539 + const int scratch = 1; /* Our extra working register */ 1540 + 1541 + uasm_i_lui(p, scratch, (mode >> 16)); 1542 + uasm_i_or(p, pte, pte, scratch); 1543 + } else 1544 + #endif 1548 1545 uasm_i_ori(p, pte, pte, mode); 1549 1546 #ifdef CONFIG_SMP 1550 1547 # ifdef CONFIG_PHYS_ADDR_T_64BIT ··· 1614 1599 uasm_il_bbit0(p, r, pte, ilog2(_PAGE_PRESENT), lid); 1615 1600 uasm_i_nop(p); 1616 1601 } else { 1617 - uasm_i_andi(p, t, pte, _PAGE_PRESENT); 1602 + uasm_i_srl(p, t, pte, _PAGE_PRESENT_SHIFT); 1603 + uasm_i_andi(p, t, t, 1); 1618 1604 uasm_il_beqz(p, r, t, lid); 1619 1605 if (pte == t) 1620 1606 /* You lose the SMP race :-(*/ 1621 1607 iPTE_LW(p, pte, ptr); 1622 1608 } 1623 1609 } else { 1624 - uasm_i_andi(p, t, pte, _PAGE_PRESENT | _PAGE_READ); 1625 - uasm_i_xori(p, t, t, _PAGE_PRESENT | _PAGE_READ); 1610 + uasm_i_srl(p, t, pte, _PAGE_PRESENT_SHIFT); 1611 + uasm_i_andi(p, t, t, 3); 1612 + uasm_i_xori(p, t, t, 3); 1626 1613 uasm_il_bnez(p, r, t, lid); 1627 1614 if (pte == t) 1628 1615 /* You lose the SMP race :-(*/ ··· 1653 1636 { 1654 1637 int t = scratch >= 0 ? scratch : pte; 1655 1638 1656 - uasm_i_andi(p, t, pte, _PAGE_PRESENT | _PAGE_WRITE); 1657 - uasm_i_xori(p, t, t, _PAGE_PRESENT | _PAGE_WRITE); 1639 + uasm_i_srl(p, t, pte, _PAGE_PRESENT_SHIFT); 1640 + uasm_i_andi(p, t, t, 5); 1641 + uasm_i_xori(p, t, t, 5); 1658 1642 uasm_il_bnez(p, r, t, lid); 1659 1643 if (pte == t) 1660 1644 /* You lose the SMP race :-(*/ ··· 1691 1673 uasm_i_nop(p); 1692 1674 } else { 1693 1675 int t = scratch >= 0 ? scratch : pte; 1694 - uasm_i_andi(p, t, pte, _PAGE_WRITE); 1676 + uasm_i_srl(p, t, pte, _PAGE_WRITE_SHIFT); 1677 + uasm_i_andi(p, t, t, 1); 1695 1678 uasm_il_beqz(p, r, t, lid); 1696 1679 if (pte == t) 1697 1680 /* You lose the SMP race :-(*/ ··· 2305 2286 2306 2287 pwsize = ilog2(PTRS_PER_PGD) << MIPS_PWSIZE_GDW_SHIFT; 2307 2288 pwsize |= ilog2(PTRS_PER_PTE) << MIPS_PWSIZE_PTW_SHIFT; 2289 + 2290 + /* If XPA has been enabled, PTEs are 64-bit in size. */ 2291 + if (read_c0_pagegrain() & PG_ELPA) 2292 + pwsize |= 1; 2293 + 2308 2294 write_c0_pwsize(pwsize); 2309 2295 2310 2296 /* Make sure everything is set before we enable the HTW */ ··· 2321 2297 pr_info("Hardware Page Table Walker enabled\n"); 2322 2298 2323 2299 print_htw_config(); 2300 + } 2301 + 2302 + static void config_xpa_params(void) 2303 + { 2304 + #ifdef CONFIG_XPA 2305 + unsigned int pagegrain; 2306 + 2307 + if (mips_xpa_disabled) { 2308 + pr_info("Extended Physical Addressing (XPA) disabled\n"); 2309 + return; 2310 + } 2311 + 2312 + pagegrain = read_c0_pagegrain(); 2313 + write_c0_pagegrain(pagegrain | PG_ELPA); 2314 + back_to_back_c0_hazard(); 2315 + pagegrain = read_c0_pagegrain(); 2316 + 2317 + if (pagegrain & PG_ELPA) 2318 + pr_info("Extended Physical Addressing (XPA) enabled\n"); 2319 + else 2320 + panic("Extended Physical Addressing (XPA) disabled"); 2321 + #endif 2324 2322 } 2325 2323 2326 2324 void build_tlb_refill_handler(void) ··· 2409 2363 } 2410 2364 if (cpu_has_local_ebase) 2411 2365 build_r4000_tlb_refill_handler(); 2366 + if (cpu_has_xpa) 2367 + config_xpa_params(); 2412 2368 if (cpu_has_htw) 2413 2369 config_htw_params(); 2414 - 2415 2370 } 2416 2371 }

+6

arch/mips/mti-malta/malta-memory.c

··· 54 54 pr_warn("memsize not set in YAMON, set to default (32Mb)\n"); 55 55 physical_memsize = 0x02000000; 56 56 } else { 57 + if (memsize > (256 << 20)) { /* memsize should be capped to 256M */ 58 + pr_warn("Unsupported memsize value (0x%lx) detected! " 59 + "Using 0x10000000 (256M) instead\n", 60 + memsize); 61 + memsize = 256 << 20; 62 + } 57 63 /* If ememsize is set, then set physical_memsize to that */ 58 64 physical_memsize = ememsize ? : memsize; 59 65 }

+13

arch/mips/netlogic/xlp/ahci-init-xlp2.c

··· 203 203 static void config_sata_phy(u64 regbase) 204 204 { 205 205 u32 port, i, reg; 206 + u8 val; 206 207 207 208 for (port = 0; port < 2; port++) { 208 209 for (i = 0, reg = RXCDRCALFOSC0; reg <= CALDUTY; reg++, i++) ··· 211 210 212 211 for (i = 0, reg = RXDPIF; reg <= PPMDRIFTMAX_HI; reg++, i++) 213 212 write_phy_reg(regbase, reg, port, sata_phy_config2[i]); 213 + 214 + /* Fix for PHY link up failures at lower temperatures */ 215 + write_phy_reg(regbase, 0x800F, port, 0x1f); 216 + 217 + val = read_phy_reg(regbase, 0x0029, port); 218 + write_phy_reg(regbase, 0x0029, port, val | (0x7 << 1)); 219 + 220 + val = read_phy_reg(regbase, 0x0056, port); 221 + write_phy_reg(regbase, 0x0056, port, val & ~(1 << 3)); 222 + 223 + val = read_phy_reg(regbase, 0x0018, port); 224 + write_phy_reg(regbase, 0x0018, port, val & ~(0x7 << 0)); 214 225 } 215 226 } 216 227

+1 -1

arch/mips/pci/Makefile

··· 43 43 obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o 44 44 obj-$(CONFIG_LANTIQ) += fixup-lantiq.o 45 45 obj-$(CONFIG_PCI_LANTIQ) += pci-lantiq.o ops-lantiq.o 46 - obj-$(CONFIG_SOC_RT2880) += pci-rt2880.o 46 + obj-$(CONFIG_SOC_RT288X) += pci-rt2880.o 47 47 obj-$(CONFIG_SOC_RT3883) += pci-rt3883.o 48 48 obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o 49 49 obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o

+2 -6

arch/mips/pci/pci-octeon.c

··· 214 214 return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA"; 215 215 case CVMX_BOARD_TYPE_BBGW_REF: 216 216 return "AABCD"; 217 + case CVMX_BOARD_TYPE_CUST_DSR1000N: 218 + return "CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC"; 217 219 case CVMX_BOARD_TYPE_THUNDER: 218 220 case CVMX_BOARD_TYPE_EBH3000: 219 221 default: ··· 273 271 pci_addr.s.func = devfn & 0x7; 274 272 pci_addr.s.reg = reg; 275 273 276 - #if PCI_CONFIG_SPACE_DELAY 277 - udelay(PCI_CONFIG_SPACE_DELAY); 278 - #endif 279 274 switch (size) { 280 275 case 4: 281 276 *val = le32_to_cpu(cvmx_read64_uint32(pci_addr.u64)); ··· 307 308 pci_addr.s.func = devfn & 0x7; 308 309 pci_addr.s.reg = reg; 309 310 310 - #if PCI_CONFIG_SPACE_DELAY 311 - udelay(PCI_CONFIG_SPACE_DELAY); 312 - #endif 313 311 switch (size) { 314 312 case 4: 315 313 cvmx_write64_uint32(pci_addr.u64, cpu_to_le32(val));

-8

arch/mips/pci/pcie-octeon.c

··· 1762 1762 default: 1763 1763 return PCIBIOS_FUNC_NOT_SUPPORTED; 1764 1764 } 1765 - #if PCI_CONFIG_SPACE_DELAY 1766 - /* 1767 - * Delay on writes so that devices have time to come up. Some 1768 - * bridges need this to allow time for the secondary busses to 1769 - * work 1770 - */ 1771 - udelay(PCI_CONFIG_SPACE_DELAY); 1772 - #endif 1773 1765 return PCIBIOS_SUCCESSFUL; 1774 1766 } 1775 1767

+5

arch/mips/ralink/Kconfig

··· 7 7 select CLKSRC_OF 8 8 select CLKSRC_MMIO 9 9 10 + config RALINK_ILL_ACC 11 + bool 12 + depends on SOC_RT305X 13 + default y 14 + 10 15 choice 11 16 prompt "Ralink SoC selection" 12 17 default SOC_RT305X

+1

drivers/ssb/Kconfig

··· 130 130 bool "SSB Broadcom MIPS core driver" 131 131 depends on SSB && MIPS 132 132 select SSB_SERIAL 133 + select SSB_SFLASH 133 134 help 134 135 Driver for the Sonics Silicon Backplane attached 135 136 Broadcom MIPS core.