Merge branch '4.1-fp' into mips-for-linux-next

+32 -32

arch/mips/include/asm/asmmacro-32.h

··· 16 16 .set push 17 17 SET_HARDFLOAT 18 18 cfc1 \tmp, fcr31 19 - s.d $f0, THREAD_FPR0_LS64(\thread) 20 - s.d $f2, THREAD_FPR2_LS64(\thread) 21 - s.d $f4, THREAD_FPR4_LS64(\thread) 22 - s.d $f6, THREAD_FPR6_LS64(\thread) 23 - s.d $f8, THREAD_FPR8_LS64(\thread) 24 - s.d $f10, THREAD_FPR10_LS64(\thread) 25 - s.d $f12, THREAD_FPR12_LS64(\thread) 26 - s.d $f14, THREAD_FPR14_LS64(\thread) 27 - s.d $f16, THREAD_FPR16_LS64(\thread) 28 - s.d $f18, THREAD_FPR18_LS64(\thread) 29 - s.d $f20, THREAD_FPR20_LS64(\thread) 30 - s.d $f22, THREAD_FPR22_LS64(\thread) 31 - s.d $f24, THREAD_FPR24_LS64(\thread) 32 - s.d $f26, THREAD_FPR26_LS64(\thread) 33 - s.d $f28, THREAD_FPR28_LS64(\thread) 34 - s.d $f30, THREAD_FPR30_LS64(\thread) 19 + s.d $f0, THREAD_FPR0(\thread) 20 + s.d $f2, THREAD_FPR2(\thread) 21 + s.d $f4, THREAD_FPR4(\thread) 22 + s.d $f6, THREAD_FPR6(\thread) 23 + s.d $f8, THREAD_FPR8(\thread) 24 + s.d $f10, THREAD_FPR10(\thread) 25 + s.d $f12, THREAD_FPR12(\thread) 26 + s.d $f14, THREAD_FPR14(\thread) 27 + s.d $f16, THREAD_FPR16(\thread) 28 + s.d $f18, THREAD_FPR18(\thread) 29 + s.d $f20, THREAD_FPR20(\thread) 30 + s.d $f22, THREAD_FPR22(\thread) 31 + s.d $f24, THREAD_FPR24(\thread) 32 + s.d $f26, THREAD_FPR26(\thread) 33 + s.d $f28, THREAD_FPR28(\thread) 34 + s.d $f30, THREAD_FPR30(\thread) 35 35 sw \tmp, THREAD_FCR31(\thread) 36 36 .set pop 37 37 .endm ··· 40 40 .set push 41 41 SET_HARDFLOAT 42 42 lw \tmp, THREAD_FCR31(\thread) 43 - l.d $f0, THREAD_FPR0_LS64(\thread) 44 - l.d $f2, THREAD_FPR2_LS64(\thread) 45 - l.d $f4, THREAD_FPR4_LS64(\thread) 46 - l.d $f6, THREAD_FPR6_LS64(\thread) 47 - l.d $f8, THREAD_FPR8_LS64(\thread) 48 - l.d $f10, THREAD_FPR10_LS64(\thread) 49 - l.d $f12, THREAD_FPR12_LS64(\thread) 50 - l.d $f14, THREAD_FPR14_LS64(\thread) 51 - l.d $f16, THREAD_FPR16_LS64(\thread) 52 - l.d $f18, THREAD_FPR18_LS64(\thread) 53 - l.d $f20, THREAD_FPR20_LS64(\thread) 54 - l.d $f22, THREAD_FPR22_LS64(\thread) 55 - l.d $f24, THREAD_FPR24_LS64(\thread) 56 - l.d $f26, THREAD_FPR26_LS64(\thread) 57 - l.d $f28, THREAD_FPR28_LS64(\thread) 58 - l.d $f30, THREAD_FPR30_LS64(\thread) 43 + l.d $f0, THREAD_FPR0(\thread) 44 + l.d $f2, THREAD_FPR2(\thread) 45 + l.d $f4, THREAD_FPR4(\thread) 46 + l.d $f6, THREAD_FPR6(\thread) 47 + l.d $f8, THREAD_FPR8(\thread) 48 + l.d $f10, THREAD_FPR10(\thread) 49 + l.d $f12, THREAD_FPR12(\thread) 50 + l.d $f14, THREAD_FPR14(\thread) 51 + l.d $f16, THREAD_FPR16(\thread) 52 + l.d $f18, THREAD_FPR18(\thread) 53 + l.d $f20, THREAD_FPR20(\thread) 54 + l.d $f22, THREAD_FPR22(\thread) 55 + l.d $f24, THREAD_FPR24(\thread) 56 + l.d $f26, THREAD_FPR26(\thread) 57 + l.d $f28, THREAD_FPR28(\thread) 58 + l.d $f30, THREAD_FPR30(\thread) 59 59 ctc1 \tmp, fcr31 60 60 .set pop 61 61 .endm

+127 -91

arch/mips/include/asm/asmmacro.h

··· 60 60 .set push 61 61 SET_HARDFLOAT 62 62 cfc1 \tmp, fcr31 63 - sdc1 $f0, THREAD_FPR0_LS64(\thread) 64 - sdc1 $f2, THREAD_FPR2_LS64(\thread) 65 - sdc1 $f4, THREAD_FPR4_LS64(\thread) 66 - sdc1 $f6, THREAD_FPR6_LS64(\thread) 67 - sdc1 $f8, THREAD_FPR8_LS64(\thread) 68 - sdc1 $f10, THREAD_FPR10_LS64(\thread) 69 - sdc1 $f12, THREAD_FPR12_LS64(\thread) 70 - sdc1 $f14, THREAD_FPR14_LS64(\thread) 71 - sdc1 $f16, THREAD_FPR16_LS64(\thread) 72 - sdc1 $f18, THREAD_FPR18_LS64(\thread) 73 - sdc1 $f20, THREAD_FPR20_LS64(\thread) 74 - sdc1 $f22, THREAD_FPR22_LS64(\thread) 75 - sdc1 $f24, THREAD_FPR24_LS64(\thread) 76 - sdc1 $f26, THREAD_FPR26_LS64(\thread) 77 - sdc1 $f28, THREAD_FPR28_LS64(\thread) 78 - sdc1 $f30, THREAD_FPR30_LS64(\thread) 63 + sdc1 $f0, THREAD_FPR0(\thread) 64 + sdc1 $f2, THREAD_FPR2(\thread) 65 + sdc1 $f4, THREAD_FPR4(\thread) 66 + sdc1 $f6, THREAD_FPR6(\thread) 67 + sdc1 $f8, THREAD_FPR8(\thread) 68 + sdc1 $f10, THREAD_FPR10(\thread) 69 + sdc1 $f12, THREAD_FPR12(\thread) 70 + sdc1 $f14, THREAD_FPR14(\thread) 71 + sdc1 $f16, THREAD_FPR16(\thread) 72 + sdc1 $f18, THREAD_FPR18(\thread) 73 + sdc1 $f20, THREAD_FPR20(\thread) 74 + sdc1 $f22, THREAD_FPR22(\thread) 75 + sdc1 $f24, THREAD_FPR24(\thread) 76 + sdc1 $f26, THREAD_FPR26(\thread) 77 + sdc1 $f28, THREAD_FPR28(\thread) 78 + sdc1 $f30, THREAD_FPR30(\thread) 79 79 sw \tmp, THREAD_FCR31(\thread) 80 80 .set pop 81 81 .endm ··· 84 84 .set push 85 85 .set mips64r2 86 86 SET_HARDFLOAT 87 - sdc1 $f1, THREAD_FPR1_LS64(\thread) 88 - sdc1 $f3, THREAD_FPR3_LS64(\thread) 89 - sdc1 $f5, THREAD_FPR5_LS64(\thread) 90 - sdc1 $f7, THREAD_FPR7_LS64(\thread) 91 - sdc1 $f9, THREAD_FPR9_LS64(\thread) 92 - sdc1 $f11, THREAD_FPR11_LS64(\thread) 93 - sdc1 $f13, THREAD_FPR13_LS64(\thread) 94 - sdc1 $f15, THREAD_FPR15_LS64(\thread) 95 - sdc1 $f17, THREAD_FPR17_LS64(\thread) 96 - sdc1 $f19, THREAD_FPR19_LS64(\thread) 97 - sdc1 $f21, THREAD_FPR21_LS64(\thread) 98 - sdc1 $f23, THREAD_FPR23_LS64(\thread) 99 - sdc1 $f25, THREAD_FPR25_LS64(\thread) 100 - sdc1 $f27, THREAD_FPR27_LS64(\thread) 101 - sdc1 $f29, THREAD_FPR29_LS64(\thread) 102 - sdc1 $f31, THREAD_FPR31_LS64(\thread) 87 + sdc1 $f1, THREAD_FPR1(\thread) 88 + sdc1 $f3, THREAD_FPR3(\thread) 89 + sdc1 $f5, THREAD_FPR5(\thread) 90 + sdc1 $f7, THREAD_FPR7(\thread) 91 + sdc1 $f9, THREAD_FPR9(\thread) 92 + sdc1 $f11, THREAD_FPR11(\thread) 93 + sdc1 $f13, THREAD_FPR13(\thread) 94 + sdc1 $f15, THREAD_FPR15(\thread) 95 + sdc1 $f17, THREAD_FPR17(\thread) 96 + sdc1 $f19, THREAD_FPR19(\thread) 97 + sdc1 $f21, THREAD_FPR21(\thread) 98 + sdc1 $f23, THREAD_FPR23(\thread) 99 + sdc1 $f25, THREAD_FPR25(\thread) 100 + sdc1 $f27, THREAD_FPR27(\thread) 101 + sdc1 $f29, THREAD_FPR29(\thread) 102 + sdc1 $f31, THREAD_FPR31(\thread) 103 103 .set pop 104 104 .endm 105 105 ··· 118 118 .set push 119 119 SET_HARDFLOAT 120 120 lw \tmp, THREAD_FCR31(\thread) 121 - ldc1 $f0, THREAD_FPR0_LS64(\thread) 122 - ldc1 $f2, THREAD_FPR2_LS64(\thread) 123 - ldc1 $f4, THREAD_FPR4_LS64(\thread) 124 - ldc1 $f6, THREAD_FPR6_LS64(\thread) 125 - ldc1 $f8, THREAD_FPR8_LS64(\thread) 126 - ldc1 $f10, THREAD_FPR10_LS64(\thread) 127 - ldc1 $f12, THREAD_FPR12_LS64(\thread) 128 - ldc1 $f14, THREAD_FPR14_LS64(\thread) 129 - ldc1 $f16, THREAD_FPR16_LS64(\thread) 130 - ldc1 $f18, THREAD_FPR18_LS64(\thread) 131 - ldc1 $f20, THREAD_FPR20_LS64(\thread) 132 - ldc1 $f22, THREAD_FPR22_LS64(\thread) 133 - ldc1 $f24, THREAD_FPR24_LS64(\thread) 134 - ldc1 $f26, THREAD_FPR26_LS64(\thread) 135 - ldc1 $f28, THREAD_FPR28_LS64(\thread) 136 - ldc1 $f30, THREAD_FPR30_LS64(\thread) 121 + ldc1 $f0, THREAD_FPR0(\thread) 122 + ldc1 $f2, THREAD_FPR2(\thread) 123 + ldc1 $f4, THREAD_FPR4(\thread) 124 + ldc1 $f6, THREAD_FPR6(\thread) 125 + ldc1 $f8, THREAD_FPR8(\thread) 126 + ldc1 $f10, THREAD_FPR10(\thread) 127 + ldc1 $f12, THREAD_FPR12(\thread) 128 + ldc1 $f14, THREAD_FPR14(\thread) 129 + ldc1 $f16, THREAD_FPR16(\thread) 130 + ldc1 $f18, THREAD_FPR18(\thread) 131 + ldc1 $f20, THREAD_FPR20(\thread) 132 + ldc1 $f22, THREAD_FPR22(\thread) 133 + ldc1 $f24, THREAD_FPR24(\thread) 134 + ldc1 $f26, THREAD_FPR26(\thread) 135 + ldc1 $f28, THREAD_FPR28(\thread) 136 + ldc1 $f30, THREAD_FPR30(\thread) 137 137 ctc1 \tmp, fcr31 138 138 .endm 139 139 ··· 141 141 .set push 142 142 .set mips64r2 143 143 SET_HARDFLOAT 144 - ldc1 $f1, THREAD_FPR1_LS64(\thread) 145 - ldc1 $f3, THREAD_FPR3_LS64(\thread) 146 - ldc1 $f5, THREAD_FPR5_LS64(\thread) 147 - ldc1 $f7, THREAD_FPR7_LS64(\thread) 148 - ldc1 $f9, THREAD_FPR9_LS64(\thread) 149 - ldc1 $f11, THREAD_FPR11_LS64(\thread) 150 - ldc1 $f13, THREAD_FPR13_LS64(\thread) 151 - ldc1 $f15, THREAD_FPR15_LS64(\thread) 152 - ldc1 $f17, THREAD_FPR17_LS64(\thread) 153 - ldc1 $f19, THREAD_FPR19_LS64(\thread) 154 - ldc1 $f21, THREAD_FPR21_LS64(\thread) 155 - ldc1 $f23, THREAD_FPR23_LS64(\thread) 156 - ldc1 $f25, THREAD_FPR25_LS64(\thread) 157 - ldc1 $f27, THREAD_FPR27_LS64(\thread) 158 - ldc1 $f29, THREAD_FPR29_LS64(\thread) 159 - ldc1 $f31, THREAD_FPR31_LS64(\thread) 144 + ldc1 $f1, THREAD_FPR1(\thread) 145 + ldc1 $f3, THREAD_FPR3(\thread) 146 + ldc1 $f5, THREAD_FPR5(\thread) 147 + ldc1 $f7, THREAD_FPR7(\thread) 148 + ldc1 $f9, THREAD_FPR9(\thread) 149 + ldc1 $f11, THREAD_FPR11(\thread) 150 + ldc1 $f13, THREAD_FPR13(\thread) 151 + ldc1 $f15, THREAD_FPR15(\thread) 152 + ldc1 $f17, THREAD_FPR17(\thread) 153 + ldc1 $f19, THREAD_FPR19(\thread) 154 + ldc1 $f21, THREAD_FPR21(\thread) 155 + ldc1 $f23, THREAD_FPR23(\thread) 156 + ldc1 $f25, THREAD_FPR25(\thread) 157 + ldc1 $f27, THREAD_FPR27(\thread) 158 + ldc1 $f29, THREAD_FPR29(\thread) 159 + ldc1 $f31, THREAD_FPR31(\thread) 160 160 .set pop 161 161 .endm 162 162 ··· 211 211 .endm 212 212 213 213 #ifdef TOOLCHAIN_SUPPORTS_MSA 214 + .macro _cfcmsa rd, cs 215 + .set push 216 + .set mips32r2 217 + .set msa 218 + cfcmsa \rd, $\cs 219 + .set pop 220 + .endm 221 + 222 + .macro _ctcmsa cd, rs 223 + .set push 224 + .set mips32r2 225 + .set msa 226 + ctcmsa $\cd, \rs 227 + .set pop 228 + .endm 229 + 214 230 .macro ld_d wd, off, base 215 231 .set push 216 232 .set mips32r2 ··· 243 227 .set pop 244 228 .endm 245 229 246 - .macro copy_u_w rd, ws, n 230 + .macro copy_u_w ws, n 247 231 .set push 248 232 .set mips32r2 249 233 .set msa 250 - copy_u.w \rd, $w\ws[\n] 234 + copy_u.w $1, $w\ws[\n] 251 235 .set pop 252 236 .endm 253 237 254 - .macro copy_u_d rd, ws, n 238 + .macro copy_u_d ws, n 255 239 .set push 256 240 .set mips64r2 257 241 .set msa 258 - copy_u.d \rd, $w\ws[\n] 242 + copy_u.d $1, $w\ws[\n] 259 243 .set pop 260 244 .endm 261 245 262 - .macro insert_w wd, n, rs 246 + .macro insert_w wd, n 263 247 .set push 264 248 .set mips32r2 265 249 .set msa 266 - insert.w $w\wd[\n], \rs 250 + insert.w $w\wd[\n], $1 267 251 .set pop 268 252 .endm 269 253 270 - .macro insert_d wd, n, rs 254 + .macro insert_d wd, n 271 255 .set push 272 256 .set mips64r2 273 257 .set msa 274 - insert.d $w\wd[\n], \rs 258 + insert.d $w\wd[\n], $1 275 259 .set pop 276 260 .endm 277 261 #else ··· 299 283 /* 300 284 * Temporary until all toolchains in use include MSA support. 301 285 */ 302 - .macro cfcmsa rd, cs 286 + .macro _cfcmsa rd, cs 303 287 .set push 304 288 .set noat 305 289 SET_HARDFLOAT ··· 309 293 .set pop 310 294 .endm 311 295 312 - .macro ctcmsa cd, rs 296 + .macro _ctcmsa cd, rs 313 297 .set push 314 298 .set noat 315 299 SET_HARDFLOAT ··· 336 320 .set pop 337 321 .endm 338 322 339 - .macro copy_u_w rd, ws, n 323 + .macro copy_u_w ws, n 340 324 .set push 341 325 .set noat 342 326 SET_HARDFLOAT 343 327 .insn 344 328 .word COPY_UW_MSA_INSN | (\n << 16) | (\ws << 11) 345 - /* move triggers an assembler bug... */ 346 - or \rd, $1, zero 347 329 .set pop 348 330 .endm 349 331 350 - .macro copy_u_d rd, ws, n 332 + .macro copy_u_d ws, n 351 333 .set push 352 334 .set noat 353 335 SET_HARDFLOAT 354 336 .insn 355 337 .word COPY_UD_MSA_INSN | (\n << 16) | (\ws << 11) 356 - /* move triggers an assembler bug... */ 357 - or \rd, $1, zero 358 338 .set pop 359 339 .endm 360 340 361 - .macro insert_w wd, n, rs 341 + .macro insert_w wd, n 362 342 .set push 363 343 .set noat 364 344 SET_HARDFLOAT 365 - /* move triggers an assembler bug... */ 366 - or $1, \rs, zero 367 345 .word INSERT_W_MSA_INSN | (\n << 16) | (\wd << 6) 368 346 .set pop 369 347 .endm 370 348 371 - .macro insert_d wd, n, rs 349 + .macro insert_d wd, n 372 350 .set push 373 351 .set noat 374 352 SET_HARDFLOAT 375 - /* move triggers an assembler bug... */ 376 - or $1, \rs, zero 377 353 .word INSERT_D_MSA_INSN | (\n << 16) | (\wd << 6) 378 354 .set pop 379 355 .endm ··· 407 399 .set push 408 400 .set noat 409 401 SET_HARDFLOAT 410 - cfcmsa $1, MSA_CSR 402 + _cfcmsa $1, MSA_CSR 411 403 sw $1, THREAD_MSA_CSR(\thread) 412 404 .set pop 413 405 .endm ··· 417 409 .set noat 418 410 SET_HARDFLOAT 419 411 lw $1, THREAD_MSA_CSR(\thread) 420 - ctcmsa MSA_CSR, $1 412 + _ctcmsa MSA_CSR, $1 421 413 .set pop 422 414 ld_d 0, THREAD_FPR0, \thread 423 415 ld_d 1, THREAD_FPR1, \thread ··· 460 452 insert_w \wd, 2 461 453 insert_w \wd, 3 462 454 #endif 463 - .if 31-\wd 464 - msa_init_upper (\wd+1) 465 - .endif 466 455 .endm 467 456 468 457 .macro msa_init_all_upper ··· 468 463 SET_HARDFLOAT 469 464 not $1, zero 470 465 msa_init_upper 0 466 + msa_init_upper 1 467 + msa_init_upper 2 468 + msa_init_upper 3 469 + msa_init_upper 4 470 + msa_init_upper 5 471 + msa_init_upper 6 472 + msa_init_upper 7 473 + msa_init_upper 8 474 + msa_init_upper 9 475 + msa_init_upper 10 476 + msa_init_upper 11 477 + msa_init_upper 12 478 + msa_init_upper 13 479 + msa_init_upper 14 480 + msa_init_upper 15 481 + msa_init_upper 16 482 + msa_init_upper 17 483 + msa_init_upper 18 484 + msa_init_upper 19 485 + msa_init_upper 20 486 + msa_init_upper 21 487 + msa_init_upper 22 488 + msa_init_upper 23 489 + msa_init_upper 24 490 + msa_init_upper 25 491 + msa_init_upper 26 492 + msa_init_upper 27 493 + msa_init_upper 28 494 + msa_init_upper 29 495 + msa_init_upper 30 496 + msa_init_upper 31 471 497 .set pop 472 498 .endm 473 499

+13 -7

arch/mips/include/asm/fpu.h

··· 48 48 #define FPU_FR_MASK 0x1 49 49 }; 50 50 51 + #define __disable_fpu() \ 52 + do { \ 53 + clear_c0_status(ST0_CU1); \ 54 + disable_fpu_hazard(); \ 55 + } while (0) 56 + 51 57 static inline int __enable_fpu(enum fpu_mode mode) 52 58 { 53 59 int fr; ··· 92 86 enable_fpu_hazard(); 93 87 94 88 /* check FR has the desired value */ 95 - return (!!(read_c0_status() & ST0_FR) == !!fr) ? 0 : SIGFPE; 89 + if (!!(read_c0_status() & ST0_FR) == !!fr) 90 + return 0; 91 + 92 + /* unsupported FR value */ 93 + __disable_fpu(); 94 + return SIGFPE; 96 95 97 96 default: 98 97 BUG(); ··· 105 94 106 95 return SIGFPE; 107 96 } 108 - 109 - #define __disable_fpu() \ 110 - do { \ 111 - clear_c0_status(ST0_CU1); \ 112 - disable_fpu_hazard(); \ 113 - } while (0) 114 97 115 98 #define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU) 116 99 ··· 175 170 } 176 171 disable_msa(); 177 172 clear_thread_flag(TIF_USEDMSA); 173 + __disable_fpu(); 178 174 } else if (is_fpu_owner()) { 179 175 if (save) 180 176 _save_fp(current);

+1 -1

arch/mips/include/asm/processor.h

··· 105 105 #ifdef CONFIG_CPU_LITTLE_ENDIAN 106 106 # define FPR_IDX(width, idx) (idx) 107 107 #else 108 - # define FPR_IDX(width, idx) ((FPU_REG_WIDTH / (width)) - 1 - (idx)) 108 + # define FPR_IDX(width, idx) ((idx) ^ ((64 / (width)) - 1)) 109 109 #endif 110 110 111 111 #define BUILD_FPR_ACCESS(width) \

-66

arch/mips/kernel/asm-offsets.c

··· 167 167 OFFSET(THREAD_FPR30, task_struct, thread.fpu.fpr[30]); 168 168 OFFSET(THREAD_FPR31, task_struct, thread.fpu.fpr[31]); 169 169 170 - /* the least significant 64 bits of each FP register */ 171 - OFFSET(THREAD_FPR0_LS64, task_struct, 172 - thread.fpu.fpr[0].val64[FPR_IDX(64, 0)]); 173 - OFFSET(THREAD_FPR1_LS64, task_struct, 174 - thread.fpu.fpr[1].val64[FPR_IDX(64, 0)]); 175 - OFFSET(THREAD_FPR2_LS64, task_struct, 176 - thread.fpu.fpr[2].val64[FPR_IDX(64, 0)]); 177 - OFFSET(THREAD_FPR3_LS64, task_struct, 178 - thread.fpu.fpr[3].val64[FPR_IDX(64, 0)]); 179 - OFFSET(THREAD_FPR4_LS64, task_struct, 180 - thread.fpu.fpr[4].val64[FPR_IDX(64, 0)]); 181 - OFFSET(THREAD_FPR5_LS64, task_struct, 182 - thread.fpu.fpr[5].val64[FPR_IDX(64, 0)]); 183 - OFFSET(THREAD_FPR6_LS64, task_struct, 184 - thread.fpu.fpr[6].val64[FPR_IDX(64, 0)]); 185 - OFFSET(THREAD_FPR7_LS64, task_struct, 186 - thread.fpu.fpr[7].val64[FPR_IDX(64, 0)]); 187 - OFFSET(THREAD_FPR8_LS64, task_struct, 188 - thread.fpu.fpr[8].val64[FPR_IDX(64, 0)]); 189 - OFFSET(THREAD_FPR9_LS64, task_struct, 190 - thread.fpu.fpr[9].val64[FPR_IDX(64, 0)]); 191 - OFFSET(THREAD_FPR10_LS64, task_struct, 192 - thread.fpu.fpr[10].val64[FPR_IDX(64, 0)]); 193 - OFFSET(THREAD_FPR11_LS64, task_struct, 194 - thread.fpu.fpr[11].val64[FPR_IDX(64, 0)]); 195 - OFFSET(THREAD_FPR12_LS64, task_struct, 196 - thread.fpu.fpr[12].val64[FPR_IDX(64, 0)]); 197 - OFFSET(THREAD_FPR13_LS64, task_struct, 198 - thread.fpu.fpr[13].val64[FPR_IDX(64, 0)]); 199 - OFFSET(THREAD_FPR14_LS64, task_struct, 200 - thread.fpu.fpr[14].val64[FPR_IDX(64, 0)]); 201 - OFFSET(THREAD_FPR15_LS64, task_struct, 202 - thread.fpu.fpr[15].val64[FPR_IDX(64, 0)]); 203 - OFFSET(THREAD_FPR16_LS64, task_struct, 204 - thread.fpu.fpr[16].val64[FPR_IDX(64, 0)]); 205 - OFFSET(THREAD_FPR17_LS64, task_struct, 206 - thread.fpu.fpr[17].val64[FPR_IDX(64, 0)]); 207 - OFFSET(THREAD_FPR18_LS64, task_struct, 208 - thread.fpu.fpr[18].val64[FPR_IDX(64, 0)]); 209 - OFFSET(THREAD_FPR19_LS64, task_struct, 210 - thread.fpu.fpr[19].val64[FPR_IDX(64, 0)]); 211 - OFFSET(THREAD_FPR20_LS64, task_struct, 212 - thread.fpu.fpr[20].val64[FPR_IDX(64, 0)]); 213 - OFFSET(THREAD_FPR21_LS64, task_struct, 214 - thread.fpu.fpr[21].val64[FPR_IDX(64, 0)]); 215 - OFFSET(THREAD_FPR22_LS64, task_struct, 216 - thread.fpu.fpr[22].val64[FPR_IDX(64, 0)]); 217 - OFFSET(THREAD_FPR23_LS64, task_struct, 218 - thread.fpu.fpr[23].val64[FPR_IDX(64, 0)]); 219 - OFFSET(THREAD_FPR24_LS64, task_struct, 220 - thread.fpu.fpr[24].val64[FPR_IDX(64, 0)]); 221 - OFFSET(THREAD_FPR25_LS64, task_struct, 222 - thread.fpu.fpr[25].val64[FPR_IDX(64, 0)]); 223 - OFFSET(THREAD_FPR26_LS64, task_struct, 224 - thread.fpu.fpr[26].val64[FPR_IDX(64, 0)]); 225 - OFFSET(THREAD_FPR27_LS64, task_struct, 226 - thread.fpu.fpr[27].val64[FPR_IDX(64, 0)]); 227 - OFFSET(THREAD_FPR28_LS64, task_struct, 228 - thread.fpu.fpr[28].val64[FPR_IDX(64, 0)]); 229 - OFFSET(THREAD_FPR29_LS64, task_struct, 230 - thread.fpu.fpr[29].val64[FPR_IDX(64, 0)]); 231 - OFFSET(THREAD_FPR30_LS64, task_struct, 232 - thread.fpu.fpr[30].val64[FPR_IDX(64, 0)]); 233 - OFFSET(THREAD_FPR31_LS64, task_struct, 234 - thread.fpu.fpr[31].val64[FPR_IDX(64, 0)]); 235 - 236 170 OFFSET(THREAD_FCR31, task_struct, thread.fpu.fcr31); 237 171 OFFSET(THREAD_MSA_CSR, task_struct, thread.fpu.msacsr); 238 172 BLANK();

+10 -1

arch/mips/kernel/genex.S

··· 368 368 STI 369 369 .endm 370 370 371 + .macro __build_clear_msa_fpe 372 + _cfcmsa a1, MSA_CSR 373 + li a2, ~(0x3f << 12) 374 + and a1, a1, a2 375 + _ctcmsa MSA_CSR, a1 376 + TRACE_IRQS_ON 377 + STI 378 + .endm 379 + 371 380 .macro __build_clear_ade 372 381 MFC0 t0, CP0_BADVADDR 373 382 PTR_S t0, PT_BVADDR(sp) ··· 435 426 BUILD_HANDLER cpu cpu sti silent /* #11 */ 436 427 BUILD_HANDLER ov ov sti silent /* #12 */ 437 428 BUILD_HANDLER tr tr sti silent /* #13 */ 438 - BUILD_HANDLER msa_fpe msa_fpe sti silent /* #14 */ 429 + BUILD_HANDLER msa_fpe msa_fpe msa_fpe silent /* #14 */ 439 430 BUILD_HANDLER fpe fpe fpe silent /* #15 */ 440 431 BUILD_HANDLER ftlb ftlb none silent /* #16 */ 441 432 BUILD_HANDLER msa msa sti silent /* #21 */

+24 -6

arch/mips/kernel/ptrace.c

··· 47 47 #define CREATE_TRACE_POINTS 48 48 #include <trace/events/syscalls.h> 49 49 50 + static void init_fp_ctx(struct task_struct *target) 51 + { 52 + /* If FP has been used then the target already has context */ 53 + if (tsk_used_math(target)) 54 + return; 55 + 56 + /* Begin with data registers set to all 1s... */ 57 + memset(&target->thread.fpu.fpr, ~0, sizeof(target->thread.fpu.fpr)); 58 + 59 + /* ...and FCSR zeroed */ 60 + target->thread.fpu.fcr31 = 0; 61 + 62 + /* 63 + * Record that the target has "used" math, such that the context 64 + * just initialised, and any modifications made by the caller, 65 + * aren't discarded. 66 + */ 67 + set_stopped_child_used_math(target); 68 + } 69 + 50 70 /* 51 71 * Called by kernel/ptrace.c when detaching.. 52 72 * ··· 166 146 if (!access_ok(VERIFY_READ, data, 33 * 8)) 167 147 return -EIO; 168 148 149 + init_fp_ctx(child); 169 150 fregs = get_fpu_regs(child); 170 151 171 152 for (i = 0; i < 32; i++) { ··· 466 445 467 446 /* XXX fcr31 */ 468 447 448 + init_fp_ctx(target); 449 + 469 450 if (sizeof(target->thread.fpu.fpr[i]) == sizeof(elf_fpreg_t)) 470 451 return user_regset_copyin(&pos, &count, &kbuf, &ubuf, 471 452 &target->thread.fpu, ··· 689 666 case FPR_BASE ... FPR_BASE + 31: { 690 667 union fpureg *fregs = get_fpu_regs(child); 691 668 692 - if (!tsk_used_math(child)) { 693 - /* FP not yet used */ 694 - memset(&child->thread.fpu, ~0, 695 - sizeof(child->thread.fpu)); 696 - child->thread.fpu.fcr31 = 0; 697 - } 669 + init_fp_ctx(child); 698 670 #ifdef CONFIG_32BIT 699 671 if (test_thread_flag(TIF_32BIT_FPREGS)) { 700 672 /*

+1 -1

arch/mips/kernel/r4k_fpu.S

··· 34 34 .endm 35 35 36 36 .set noreorder 37 - .set MIPS_ISA_ARCH_LEVEL_RAW 38 37 39 38 LEAF(_save_fp_context) 40 39 .set push ··· 102 103 /* Save 32-bit process floating point context */ 103 104 LEAF(_save_fp_context32) 104 105 .set push 106 + .set MIPS_ISA_ARCH_LEVEL_RAW 105 107 SET_HARDFLOAT 106 108 cfc1 t1, fcr31 107 109