drm/amd/display: Remove unnecessary code

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

This commit groups many parts of the code that are redundant or not used
and drops all of them.

Reviewed-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Rodrigo Siqueira and committed by

Alex Deucher 2 years ago 3854887b 71866b72

-30

5 changed files

expand all

drivers

gpu

drm

amd

display

dc.h

dce

dce_i2c_hw.c

dcn10

dcn10_link_encoder.h

dcn30

dcn30_dccg.h

dcn30_dwb.c

-1

drivers/gpu/drm/amd/display/dc/dc.h

··· 1006 1006 unsigned int force_cositing; 1007 1007 }; 1008 1008 1009 - struct gpu_info_soc_bounding_box_v1_0; 1010 1009 1011 1010 /* Generic structure that can be used to query properties of DC. More fields 1012 1011 * can be added as required.

-3

drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c

··· 312 312 /* we have checked I2c not used by DMCU, set SW use I2C REQ to 1 to indicate SW using it*/ 313 313 REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1); 314 314 315 - /* we have checked I2c not used by DMCU, set SW use I2C REQ to 1 to indicate SW using it*/ 316 - REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1); 317 - 318 315 /*set SW requested I2c speed to default, if API calls in it will be override later*/ 319 316 set_speed(dce_i2c_hw, dce_i2c_hw->ctx->dc->caps.i2c_speed_in_khz); 320 317

-6

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h

··· 167 167 uint32_t DIO_LINKD_CNTL; 168 168 uint32_t DIO_LINKE_CNTL; 169 169 uint32_t DIO_LINKF_CNTL; 170 - uint32_t DIG_FIFO_CTRL0; 171 170 uint32_t DIO_CLK_CNTL; 172 171 uint32_t DIG_BE_CLK_CNTL; 173 172 }; ··· 474 475 type HPO_DP_ENC_SEL;\ 475 476 type HPO_HDMI_ENC_SEL 476 477 477 - #define DCN32_LINK_ENCODER_REG_FIELD_LIST(type) \ 478 - type DIG_FIFO_OUTPUT_PIXEL_MODE 479 - 480 478 #define DCN35_LINK_ENCODER_REG_FIELD_LIST(type) \ 481 479 type DIG_BE_ENABLE;\ 482 480 type DIG_RB_SWITCH_EN;\ ··· 508 512 DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t); 509 513 DCN30_LINK_ENCODER_REG_FIELD_LIST(uint8_t); 510 514 DCN31_LINK_ENCODER_REG_FIELD_LIST(uint8_t); 511 - DCN32_LINK_ENCODER_REG_FIELD_LIST(uint8_t); 512 515 DCN35_LINK_ENCODER_REG_FIELD_LIST(uint8_t); 513 516 }; 514 517 ··· 516 521 DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t); 517 522 DCN30_LINK_ENCODER_REG_FIELD_LIST(uint32_t); 518 523 DCN31_LINK_ENCODER_REG_FIELD_LIST(uint32_t); 519 - DCN32_LINK_ENCODER_REG_FIELD_LIST(uint32_t); 520 524 DCN35_LINK_ENCODER_REG_FIELD_LIST(uint32_t); 521 525 }; 522 526

-18

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dccg.h

··· 29 29 #include "dcn20/dcn20_dccg.h" 30 30 31 31 32 - #define DCCG_REG_LIST_DCN3AG() \ 33 - DCCG_COMMON_REG_LIST_DCN_BASE(),\ 34 - SR(PHYASYMCLK_CLOCK_CNTL),\ 35 - SR(PHYBSYMCLK_CLOCK_CNTL),\ 36 - SR(PHYCSYMCLK_CLOCK_CNTL) 37 - 38 - 39 32 #define DCCG_REG_LIST_DCN30() \ 40 33 DCCG_REG_LIST_DCN2(),\ 41 34 DCCG_SRII(PIXEL_RATE_CNTL, OTG, 2),\ ··· 38 45 SR(PHYASYMCLK_CLOCK_CNTL),\ 39 46 SR(PHYBSYMCLK_CLOCK_CNTL),\ 40 47 SR(PHYCSYMCLK_CLOCK_CNTL) 41 - 42 - #define DCCG_MASK_SH_LIST_DCN3AG(mask_sh) \ 43 - DCCG_MASK_SH_LIST_DCN2_1(mask_sh),\ 44 - DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_EN, mask_sh),\ 45 - DCCG_SF(HDMICHARCLK0_CLOCK_CNTL, HDMICHARCLK0_SRC_SEL, mask_sh),\ 46 - DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_EN, mask_sh),\ 47 - DCCG_SF(PHYASYMCLK_CLOCK_CNTL, PHYASYMCLK_FORCE_SRC_SEL, mask_sh),\ 48 - DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_EN, mask_sh),\ 49 - DCCG_SF(PHYBSYMCLK_CLOCK_CNTL, PHYBSYMCLK_FORCE_SRC_SEL, mask_sh),\ 50 - DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_EN, mask_sh),\ 51 - DCCG_SF(PHYCSYMCLK_CLOCK_CNTL, PHYCSYMCLK_FORCE_SRC_SEL, mask_sh) 52 48 53 49 #define DCCG_MASK_SH_LIST_DCN3(mask_sh) \ 54 50 DCCG_MASK_SH_LIST_DCN2(mask_sh),\

-2

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_dwb.c

··· 251 251 .set_fc_enable = dwb3_set_fc_enable, 252 252 .set_stereo = dwb3_set_stereo, 253 253 .set_new_content = dwb3_set_new_content, 254 - .dwb_program_output_csc = NULL, 255 254 .dwb_ogam_set_input_transfer_func = dwb3_ogam_set_input_transfer_func, //TODO: rename 256 - .dwb_set_scaler = NULL, 257 255 }; 258 256 259 257 void dcn30_dwbc_construct(struct dcn30_dwbc *dwbc30,