tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

Merge branch 'ib-amlogic-t7' into devel

Linus Walleij 34d7c484 44da5bf4

+1798
+1
Documentation/devicetree/bindings/pinctrl/amlogic,meson-pinctrl-a1.yaml
··· 16 16 compatible: 17 17 enum: 18 18 - amlogic,c3-periphs-pinctrl 19 + - amlogic,t7-periphs-pinctrl 19 20 - amlogic,meson-a1-periphs-pinctrl 20 21 - amlogic,meson-s4-periphs-pinctrl 21 22
+6
drivers/pinctrl/meson/Kconfig
··· 73 73 select PINCTRL_MESON_AXG_PMX 74 74 default y 75 75 76 + config PINCTRL_AMLOGIC_T7 77 + tristate "Amlogic T7 SoC pinctrl driver" 78 + depends on ARM64 79 + select PINCTRL_MESON_AXG_PMX 80 + default y 81 + 76 82 endif
+1
drivers/pinctrl/meson/Makefile
··· 11 11 obj-$(CONFIG_PINCTRL_MESON_A1) += pinctrl-meson-a1.o 12 12 obj-$(CONFIG_PINCTRL_MESON_S4) += pinctrl-meson-s4.o 13 13 obj-$(CONFIG_PINCTRL_AMLOGIC_C3) += pinctrl-amlogic-c3.o 14 + obj-$(CONFIG_PINCTRL_AMLOGIC_T7) += pinctrl-amlogic-t7.o
+1611
drivers/pinctrl/meson/pinctrl-amlogic-t7.c
··· 1 + // SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2 + /* 3 + * Pin controller and GPIO driver for Amlogic T7 SoC. 4 + * 5 + * Copyright (c) 2023 Amlogic, Inc. All rights reserved. 6 + * Author: Huqiang Qin <huqiang.qin@amlogic.com> 7 + */ 8 + 9 + #include <dt-bindings/gpio/amlogic,t7-periphs-pinctrl.h> 10 + #include "pinctrl-meson.h" 11 + #include "pinctrl-meson-axg-pmx.h" 12 + 13 + static const struct pinctrl_pin_desc t7_periphs_pins[] = { 14 + MESON_PIN(GPIOB_0), 15 + MESON_PIN(GPIOB_1), 16 + MESON_PIN(GPIOB_2), 17 + MESON_PIN(GPIOB_3), 18 + MESON_PIN(GPIOB_4), 19 + MESON_PIN(GPIOB_5), 20 + MESON_PIN(GPIOB_6), 21 + MESON_PIN(GPIOB_7), 22 + MESON_PIN(GPIOB_8), 23 + MESON_PIN(GPIOB_9), 24 + MESON_PIN(GPIOB_10), 25 + MESON_PIN(GPIOB_11), 26 + MESON_PIN(GPIOB_12), 27 + 28 + MESON_PIN(GPIOC_0), 29 + MESON_PIN(GPIOC_1), 30 + MESON_PIN(GPIOC_2), 31 + MESON_PIN(GPIOC_3), 32 + MESON_PIN(GPIOC_4), 33 + MESON_PIN(GPIOC_5), 34 + MESON_PIN(GPIOC_6), 35 + 36 + MESON_PIN(GPIOX_0), 37 + MESON_PIN(GPIOX_1), 38 + MESON_PIN(GPIOX_2), 39 + MESON_PIN(GPIOX_3), 40 + MESON_PIN(GPIOX_4), 41 + MESON_PIN(GPIOX_5), 42 + MESON_PIN(GPIOX_6), 43 + MESON_PIN(GPIOX_7), 44 + MESON_PIN(GPIOX_8), 45 + MESON_PIN(GPIOX_9), 46 + MESON_PIN(GPIOX_10), 47 + MESON_PIN(GPIOX_11), 48 + MESON_PIN(GPIOX_12), 49 + MESON_PIN(GPIOX_13), 50 + MESON_PIN(GPIOX_14), 51 + MESON_PIN(GPIOX_15), 52 + MESON_PIN(GPIOX_16), 53 + MESON_PIN(GPIOX_17), 54 + MESON_PIN(GPIOX_18), 55 + MESON_PIN(GPIOX_19), 56 + 57 + MESON_PIN(GPIOW_0), 58 + MESON_PIN(GPIOW_1), 59 + MESON_PIN(GPIOW_2), 60 + MESON_PIN(GPIOW_3), 61 + MESON_PIN(GPIOW_4), 62 + MESON_PIN(GPIOW_5), 63 + MESON_PIN(GPIOW_6), 64 + MESON_PIN(GPIOW_7), 65 + MESON_PIN(GPIOW_8), 66 + MESON_PIN(GPIOW_9), 67 + MESON_PIN(GPIOW_10), 68 + MESON_PIN(GPIOW_11), 69 + MESON_PIN(GPIOW_12), 70 + MESON_PIN(GPIOW_13), 71 + MESON_PIN(GPIOW_14), 72 + MESON_PIN(GPIOW_15), 73 + MESON_PIN(GPIOW_16), 74 + 75 + MESON_PIN(GPIOD_0), 76 + MESON_PIN(GPIOD_1), 77 + MESON_PIN(GPIOD_2), 78 + MESON_PIN(GPIOD_3), 79 + MESON_PIN(GPIOD_4), 80 + MESON_PIN(GPIOD_5), 81 + MESON_PIN(GPIOD_6), 82 + MESON_PIN(GPIOD_7), 83 + MESON_PIN(GPIOD_8), 84 + MESON_PIN(GPIOD_9), 85 + MESON_PIN(GPIOD_10), 86 + MESON_PIN(GPIOD_11), 87 + MESON_PIN(GPIOD_12), 88 + 89 + MESON_PIN(GPIOE_0), 90 + MESON_PIN(GPIOE_1), 91 + MESON_PIN(GPIOE_2), 92 + MESON_PIN(GPIOE_3), 93 + MESON_PIN(GPIOE_4), 94 + MESON_PIN(GPIOE_5), 95 + MESON_PIN(GPIOE_6), 96 + 97 + MESON_PIN(GPIOZ_0), 98 + MESON_PIN(GPIOZ_1), 99 + MESON_PIN(GPIOZ_2), 100 + MESON_PIN(GPIOZ_3), 101 + MESON_PIN(GPIOZ_4), 102 + MESON_PIN(GPIOZ_5), 103 + MESON_PIN(GPIOZ_6), 104 + MESON_PIN(GPIOZ_7), 105 + MESON_PIN(GPIOZ_8), 106 + MESON_PIN(GPIOZ_9), 107 + MESON_PIN(GPIOZ_10), 108 + MESON_PIN(GPIOZ_11), 109 + MESON_PIN(GPIOZ_12), 110 + MESON_PIN(GPIOZ_13), 111 + 112 + MESON_PIN(GPIOT_0), 113 + MESON_PIN(GPIOT_1), 114 + MESON_PIN(GPIOT_2), 115 + MESON_PIN(GPIOT_3), 116 + MESON_PIN(GPIOT_4), 117 + MESON_PIN(GPIOT_5), 118 + MESON_PIN(GPIOT_6), 119 + MESON_PIN(GPIOT_7), 120 + MESON_PIN(GPIOT_8), 121 + MESON_PIN(GPIOT_9), 122 + MESON_PIN(GPIOT_10), 123 + MESON_PIN(GPIOT_11), 124 + MESON_PIN(GPIOT_12), 125 + MESON_PIN(GPIOT_13), 126 + MESON_PIN(GPIOT_14), 127 + MESON_PIN(GPIOT_15), 128 + MESON_PIN(GPIOT_16), 129 + MESON_PIN(GPIOT_17), 130 + MESON_PIN(GPIOT_18), 131 + MESON_PIN(GPIOT_19), 132 + MESON_PIN(GPIOT_20), 133 + MESON_PIN(GPIOT_21), 134 + MESON_PIN(GPIOT_22), 135 + MESON_PIN(GPIOT_23), 136 + 137 + MESON_PIN(GPIOM_0), 138 + MESON_PIN(GPIOM_1), 139 + MESON_PIN(GPIOM_2), 140 + MESON_PIN(GPIOM_3), 141 + MESON_PIN(GPIOM_4), 142 + MESON_PIN(GPIOM_5), 143 + MESON_PIN(GPIOM_6), 144 + MESON_PIN(GPIOM_7), 145 + MESON_PIN(GPIOM_8), 146 + MESON_PIN(GPIOM_9), 147 + MESON_PIN(GPIOM_10), 148 + MESON_PIN(GPIOM_11), 149 + MESON_PIN(GPIOM_12), 150 + MESON_PIN(GPIOM_13), 151 + 152 + MESON_PIN(GPIOY_0), 153 + MESON_PIN(GPIOY_1), 154 + MESON_PIN(GPIOY_2), 155 + MESON_PIN(GPIOY_3), 156 + MESON_PIN(GPIOY_4), 157 + MESON_PIN(GPIOY_5), 158 + MESON_PIN(GPIOY_6), 159 + MESON_PIN(GPIOY_7), 160 + MESON_PIN(GPIOY_8), 161 + MESON_PIN(GPIOY_9), 162 + MESON_PIN(GPIOY_10), 163 + MESON_PIN(GPIOY_11), 164 + MESON_PIN(GPIOY_12), 165 + MESON_PIN(GPIOY_13), 166 + MESON_PIN(GPIOY_14), 167 + MESON_PIN(GPIOY_15), 168 + MESON_PIN(GPIOY_16), 169 + MESON_PIN(GPIOY_17), 170 + MESON_PIN(GPIOY_18), 171 + 172 + MESON_PIN(GPIOH_0), 173 + MESON_PIN(GPIOH_1), 174 + MESON_PIN(GPIOH_2), 175 + MESON_PIN(GPIOH_3), 176 + MESON_PIN(GPIOH_4), 177 + MESON_PIN(GPIOH_5), 178 + MESON_PIN(GPIOH_6), 179 + MESON_PIN(GPIOH_7), 180 + 181 + MESON_PIN(GPIO_TEST_N), 182 + }; 183 + 184 + /* Bank B func1 */ 185 + static const unsigned int emmc_nand_d0_pins[] = { GPIOB_0 }; 186 + static const unsigned int emmc_nand_d1_pins[] = { GPIOB_1 }; 187 + static const unsigned int emmc_nand_d2_pins[] = { GPIOB_2 }; 188 + static const unsigned int emmc_nand_d3_pins[] = { GPIOB_3 }; 189 + static const unsigned int emmc_nand_d4_pins[] = { GPIOB_4 }; 190 + static const unsigned int emmc_nand_d5_pins[] = { GPIOB_5 }; 191 + static const unsigned int emmc_nand_d6_pins[] = { GPIOB_6 }; 192 + static const unsigned int emmc_nand_d7_pins[] = { GPIOB_7 }; 193 + static const unsigned int emmc_clk_pins[] = { GPIOB_8 }; 194 + static const unsigned int emmc_cmd_pins[] = { GPIOB_10 }; 195 + static const unsigned int emmc_nand_ds_pins[] = { GPIOB_11 }; 196 + 197 + /* Bank B func2 */ 198 + static const unsigned int nor_hold_pins[] = { GPIOB_3 }; 199 + static const unsigned int nor_d_pins[] = { GPIOB_4 }; 200 + static const unsigned int nor_q_pins[] = { GPIOB_5 }; 201 + static const unsigned int nor_c_pins[] = { GPIOB_6 }; 202 + static const unsigned int nor_wp_pins[] = { GPIOB_7 }; 203 + static const unsigned int nor_cs_pins[] = { GPIOB_12 }; 204 + 205 + /* Bank C func1 */ 206 + static const unsigned int sdcard_d0_pins[] = { GPIOC_0 }; 207 + static const unsigned int sdcard_d1_pins[] = { GPIOC_1 }; 208 + static const unsigned int sdcard_d2_pins[] = { GPIOC_2 }; 209 + static const unsigned int sdcard_d3_pins[] = { GPIOC_3 }; 210 + static const unsigned int sdcard_clk_pins[] = { GPIOC_4 }; 211 + static const unsigned int sdcard_cmd_pins[] = { GPIOC_5 }; 212 + static const unsigned int gen_clk_out_c_pins[] = { GPIOC_6 }; 213 + 214 + /* Bank C func2 */ 215 + static const unsigned int jtag_b_tdo_pins[] = { GPIOC_0 }; 216 + static const unsigned int jtag_b_tdi_pins[] = { GPIOC_1 }; 217 + static const unsigned int uart_ao_a_rx_c_pins[] = { GPIOC_2 }; 218 + static const unsigned int uart_ao_a_tx_c_pins[] = { GPIOC_3 }; 219 + static const unsigned int jtag_b_clk_pins[] = { GPIOC_4 }; 220 + static const unsigned int jtag_b_tms_pins[] = { GPIOC_5 }; 221 + 222 + /* Bank C func3 */ 223 + static const unsigned int spi1_mosi_c_pins[] = { GPIOC_0 }; 224 + static const unsigned int spi1_miso_c_pins[] = { GPIOC_1 }; 225 + static const unsigned int spi1_sclk_c_pins[] = { GPIOC_2 }; 226 + static const unsigned int spi1_ss0_c_pins[] = { GPIOC_3 }; 227 + 228 + /* Bank X func1 */ 229 + static const unsigned int sdio_d0_pins[] = { GPIOX_0 }; 230 + static const unsigned int sdio_d1_pins[] = { GPIOX_1 }; 231 + static const unsigned int sdio_d2_pins[] = { GPIOX_2 }; 232 + static const unsigned int sdio_d3_pins[] = { GPIOX_3 }; 233 + static const unsigned int sdio_clk_pins[] = { GPIOX_4 }; 234 + static const unsigned int sdio_cmd_pins[] = { GPIOX_5 }; 235 + static const unsigned int pwm_b_pins[] = { GPIOX_6 }; 236 + static const unsigned int pwm_c_pins[] = { GPIOX_7 }; 237 + static const unsigned int tdm_d0_pins[] = { GPIOX_8 }; 238 + static const unsigned int tdm_d1_pins[] = { GPIOX_9 }; 239 + static const unsigned int tdm_fs0_pins[] = { GPIOX_10 }; 240 + static const unsigned int tdm_sclk0_pins[] = { GPIOX_11 }; 241 + static const unsigned int uart_c_tx_pins[] = { GPIOX_12 }; 242 + static const unsigned int uart_c_rx_pins[] = { GPIOX_13 }; 243 + static const unsigned int uart_c_cts_pins[] = { GPIOX_14 }; 244 + static const unsigned int uart_c_rts_pins[] = { GPIOX_15 }; 245 + static const unsigned int pwm_a_pins[] = { GPIOX_16 }; 246 + static const unsigned int i2c2_sda_x_pins[] = { GPIOX_17 }; 247 + static const unsigned int i2c2_sck_x_pins[] = { GPIOX_18 }; 248 + static const unsigned int pwm_d_pins[] = { GPIOX_19 }; 249 + 250 + /* Bank X func2 */ 251 + static const unsigned int clk12_24_x_pins[] = { GPIOX_14 }; 252 + 253 + /* Bank W func1 */ 254 + static const unsigned int hdmirx_a_hpd_pins[] = { GPIOW_0 }; 255 + static const unsigned int hdmirx_a_det_pins[] = { GPIOW_1 }; 256 + static const unsigned int hdmirx_a_sda_pins[] = { GPIOW_2 }; 257 + static const unsigned int hdmirx_a_sck_pins[] = { GPIOW_3 }; 258 + static const unsigned int hdmirx_c_hpd_pins[] = { GPIOW_4 }; 259 + static const unsigned int hdmirx_c_det_pins[] = { GPIOW_5 }; 260 + static const unsigned int hdmirx_c_sda_pins[] = { GPIOW_6 }; 261 + static const unsigned int hdmirx_c_sck_pins[] = { GPIOW_7 }; 262 + static const unsigned int hdmirx_b_hpd_pins[] = { GPIOW_8 }; 263 + static const unsigned int hdmirx_b_det_pins[] = { GPIOW_9 }; 264 + static const unsigned int hdmirx_b_sda_pins[] = { GPIOW_10 }; 265 + static const unsigned int hdmirx_b_sck_pins[] = { GPIOW_11 }; 266 + static const unsigned int cec_a_pins[] = { GPIOW_12 }; 267 + static const unsigned int hdmitx_sda_w13_pins[] = { GPIOW_13 }; 268 + static const unsigned int hdmitx_sck_w14_pins[] = { GPIOW_14 }; 269 + static const unsigned int hdmitx_hpd_in_pins[] = { GPIOW_15 }; 270 + static const unsigned int cec_b_pins[] = { GPIOW_16 }; 271 + 272 + /* Bank W func2 */ 273 + static const unsigned int uart_ao_a_tx_w2_pins[] = { GPIOW_2 }; 274 + static const unsigned int uart_ao_a_rx_w3_pins[] = { GPIOW_3 }; 275 + static const unsigned int uart_ao_a_tx_w6_pins[] = { GPIOW_6 }; 276 + static const unsigned int uart_ao_a_rx_w7_pins[] = { GPIOW_7 }; 277 + static const unsigned int uart_ao_a_tx_w10_pins[] = { GPIOW_10 }; 278 + static const unsigned int uart_ao_a_rx_w11_pins[] = { GPIOW_11 }; 279 + 280 + /* Bank W func3 */ 281 + static const unsigned int hdmitx_sda_w2_pins[] = { GPIOW_2 }; 282 + static const unsigned int hdmitx_sck_w3_pins[] = { GPIOW_3 }; 283 + 284 + /* Bank D func1 */ 285 + static const unsigned int uart_ao_a_tx_d0_pins[] = { GPIOD_0 }; 286 + static const unsigned int uart_ao_a_rx_d1_pins[] = { GPIOD_1 }; 287 + static const unsigned int i2c0_ao_sck_d_pins[] = { GPIOD_2 }; 288 + static const unsigned int i2c0_ao_sda_d_pins[] = { GPIOD_3 }; 289 + static const unsigned int remote_out_d4_pins[] = { GPIOD_4 }; 290 + static const unsigned int remote_in_pins[] = { GPIOD_5 }; 291 + static const unsigned int jtag_a_clk_pins[] = { GPIOD_6 }; 292 + static const unsigned int jtag_a_tms_pins[] = { GPIOD_7 }; 293 + static const unsigned int jtag_a_tdi_pins[] = { GPIOD_8 }; 294 + static const unsigned int jtag_a_tdo_pins[] = { GPIOD_9 }; 295 + static const unsigned int gen_clk_out_d_pins[] = { GPIOD_10 }; 296 + static const unsigned int pwm_ao_g_d11_pins[] = { GPIOD_11 }; 297 + static const unsigned int wd_rsto_pins[] = { GPIOD_12 }; 298 + 299 + /* Bank D func2 */ 300 + static const unsigned int i2c0_slave_ao_sck_pins[] = { GPIOD_2 }; 301 + static const unsigned int i2c0_slave_ao_sda_pins[] = { GPIOD_3 }; 302 + static const unsigned int rtc_clk_in_pins[] = { GPIOD_4 }; 303 + static const unsigned int pwm_ao_h_d5_pins[] = { GPIOD_5 }; 304 + static const unsigned int pwm_ao_c_d_pins[] = { GPIOD_6 }; 305 + static const unsigned int pwm_ao_g_d7_pins[] = { GPIOD_7 }; 306 + static const unsigned int spdif_out_d_pins[] = { GPIOD_8 }; 307 + static const unsigned int spdif_in_d_pins[] = { GPIOD_9 }; 308 + static const unsigned int pwm_ao_h_d10_pins[] = { GPIOD_10 }; 309 + 310 + /* Bank D func3 */ 311 + static const unsigned int uart_ao_b_tx_pins[] = { GPIOD_2 }; 312 + static const unsigned int uart_ao_b_rx_pins[] = { GPIOD_3 }; 313 + static const unsigned int uart_ao_b_cts_pins[] = { GPIOD_4 }; 314 + static const unsigned int pwm_ao_c_hiz_pins[] = { GPIOD_6 }; 315 + static const unsigned int pwm_ao_g_hiz_pins[] = { GPIOD_7 }; 316 + static const unsigned int uart_ao_b_rts_pins[] = { GPIOD_10 }; 317 + 318 + /* Bank D func4 */ 319 + static const unsigned int remote_out_d6_pins[] = { GPIOD_6 }; 320 + 321 + /* Bank E func1 */ 322 + static const unsigned int pwm_ao_a_pins[] = { GPIOE_0 }; 323 + static const unsigned int pwm_ao_b_pins[] = { GPIOE_1 }; 324 + static const unsigned int pwm_ao_c_e_pins[] = { GPIOE_2 }; 325 + static const unsigned int pwm_ao_d_pins[] = { GPIOE_3 }; 326 + static const unsigned int pwm_ao_e_pins[] = { GPIOE_4 }; 327 + static const unsigned int pwm_ao_f_pins[] = { GPIOE_5 }; 328 + static const unsigned int pwm_ao_g_e_pins[] = { GPIOE_6 }; 329 + 330 + /* Bank E func2 */ 331 + static const unsigned int i2c0_ao_sck_e_pins[] = { GPIOE_0 }; 332 + static const unsigned int i2c0_ao_sda_e_pins[] = { GPIOE_1 }; 333 + static const unsigned int clk25m_pins[] = { GPIOE_2 }; 334 + static const unsigned int i2c1_ao_sck_pins[] = { GPIOE_3 }; 335 + static const unsigned int i2c1_ao_sda_pins[] = { GPIOE_4 }; 336 + static const unsigned int rtc_clk_out_pins[] = { GPIOD_5 }; 337 + 338 + /* Bank E func3 */ 339 + static const unsigned int clk12_24_e_pins[] = { GPIOE_4 }; 340 + 341 + /* Bank Z func1 */ 342 + static const unsigned int eth_mdio_pins[] = { GPIOZ_0 }; 343 + static const unsigned int eth_mdc_pins[] = { GPIOZ_1 }; 344 + static const unsigned int eth_rgmii_rx_clk_pins[] = { GPIOZ_2 }; 345 + static const unsigned int eth_rx_dv_pins[] = { GPIOZ_3 }; 346 + static const unsigned int eth_rxd0_pins[] = { GPIOZ_4 }; 347 + static const unsigned int eth_rxd1_pins[] = { GPIOZ_5 }; 348 + static const unsigned int eth_rxd2_rgmii_pins[] = { GPIOZ_6 }; 349 + static const unsigned int eth_rxd3_rgmii_pins[] = { GPIOZ_7 }; 350 + static const unsigned int eth_rgmii_tx_clk_pins[] = { GPIOZ_8 }; 351 + static const unsigned int eth_txen_pins[] = { GPIOZ_9 }; 352 + static const unsigned int eth_txd0_pins[] = { GPIOZ_10 }; 353 + static const unsigned int eth_txd1_pins[] = { GPIOZ_11 }; 354 + static const unsigned int eth_txd2_rgmii_pins[] = { GPIOZ_12 }; 355 + static const unsigned int eth_txd3_rgmii_pins[] = { GPIOZ_13 }; 356 + 357 + /* Bank Z func2 */ 358 + static const unsigned int iso7816_clk_z_pins[] = { GPIOZ_0 }; 359 + static const unsigned int iso7816_data_z_pins[] = { GPIOZ_1 }; 360 + static const unsigned int tsin_b_valid_pins[] = { GPIOZ_2 }; 361 + static const unsigned int tsin_b_sop_pins[] = { GPIOZ_3 }; 362 + static const unsigned int tsin_b_din0_pins[] = { GPIOZ_4 }; 363 + static const unsigned int tsin_b_clk_pins[] = { GPIOZ_5 }; 364 + static const unsigned int tsin_b_fail_pins[] = { GPIOZ_6 }; 365 + static const unsigned int tsin_b_din1_pins[] = { GPIOZ_7 }; 366 + static const unsigned int tsin_b_din2_pins[] = { GPIOZ_8 }; 367 + static const unsigned int tsin_b_din3_pins[] = { GPIOZ_9 }; 368 + static const unsigned int tsin_b_din4_pins[] = { GPIOZ_10 }; 369 + static const unsigned int tsin_b_din5_pins[] = { GPIOZ_11 }; 370 + static const unsigned int tsin_b_din6_pins[] = { GPIOZ_12 }; 371 + static const unsigned int tsin_b_din7_pins[] = { GPIOZ_13 }; 372 + 373 + /* Bank Z func3 */ 374 + static const unsigned int tsin_c_z_valid_pins[] = { GPIOZ_6 }; 375 + static const unsigned int tsin_c_z_sop_pins[] = { GPIOZ_7 }; 376 + static const unsigned int tsin_c_z_din0_pins[] = { GPIOZ_8 }; 377 + static const unsigned int tsin_c_z_clk_pins[] = { GPIOZ_9 }; 378 + static const unsigned int tsin_d_z_valid_pins[] = { GPIOZ_10 }; 379 + static const unsigned int tsin_d_z_sop_pins[] = { GPIOZ_11 }; 380 + static const unsigned int tsin_d_z_din0_pins[] = { GPIOZ_12 }; 381 + static const unsigned int tsin_d_z_clk_pins[] = { GPIOZ_13 }; 382 + 383 + /* Bank Z func4 */ 384 + static const unsigned int spi4_mosi_pins[] = { GPIOZ_0 }; 385 + static const unsigned int spi4_miso_pins[] = { GPIOZ_1 }; 386 + static const unsigned int spi4_sclk_pins[] = { GPIOZ_2 }; 387 + static const unsigned int spi4_ss0_pins[] = { GPIOZ_3 }; 388 + static const unsigned int spi5_mosi_pins[] = { GPIOZ_4 }; 389 + static const unsigned int spi5_miso_pins[] = { GPIOZ_5 }; 390 + static const unsigned int spi5_sclk_pins[] = { GPIOZ_6 }; 391 + static const unsigned int spi5_ss0_pins[] = { GPIOZ_7 }; 392 + 393 + /* Bank T func1 */ 394 + static const unsigned int mclk1_pins[] = { GPIOT_0 }; 395 + static const unsigned int tdm_sclk1_pins[] = { GPIOT_1 }; 396 + static const unsigned int tdm_fs1_pins[] = { GPIOT_2 }; 397 + static const unsigned int tdm_d2_pins[] = { GPIOT_3 }; 398 + static const unsigned int tdm_d3_pins[] = { GPIOT_4 }; 399 + static const unsigned int tdm_d4_pins[] = { GPIOT_5 }; 400 + static const unsigned int tdm_d5_pins[] = { GPIOT_6 }; 401 + static const unsigned int tdm_d6_pins[] = { GPIOT_7 }; 402 + static const unsigned int tdm_d7_pins[] = { GPIOT_8 }; 403 + static const unsigned int tdm_d8_pins[] = { GPIOT_9 }; 404 + static const unsigned int tdm_d9_pins[] = { GPIOT_10 }; 405 + static const unsigned int tdm_d10_pins[] = { GPIOT_11 }; 406 + static const unsigned int tdm_d11_pins[] = { GPIOT_12 }; 407 + static const unsigned int mclk2_pins[] = { GPIOT_13 }; 408 + static const unsigned int tdm_sclk2_pins[] = { GPIOT_14 }; 409 + static const unsigned int tdm_fs2_pins[] = { GPIOT_15 }; 410 + static const unsigned int i2c1_sck_pins[] = { GPIOT_16 }; 411 + static const unsigned int i2c1_sda_pins[] = { GPIOT_17 }; 412 + static const unsigned int spi0_mosi_pins[] = { GPIOT_18 }; 413 + static const unsigned int spi0_miso_pins[] = { GPIOT_19 }; 414 + static const unsigned int spi0_sclk_pins[] = { GPIOT_20 }; 415 + static const unsigned int spi0_ss0_pins[] = { GPIOT_21 }; 416 + static const unsigned int spi0_ss1_pins[] = { GPIOT_22 }; 417 + static const unsigned int spi0_ss2_pins[] = { GPIOT_23 }; 418 + 419 + /* Bank T func2 */ 420 + static const unsigned int spdif_in_t_pins[] = { GPIOT_3 }; 421 + static const unsigned int spdif_out_t_pins[] = { GPIOT_4 }; 422 + static const unsigned int iso7816_clk_t_pins[] = { GPIOT_5 }; 423 + static const unsigned int iso7816_data_t_pins[] = { GPIOT_6 }; 424 + static const unsigned int tsin_a_sop_t_pins[] = { GPIOT_7 }; 425 + static const unsigned int tsin_a_din0_t_pins[] = { GPIOT_8 }; 426 + static const unsigned int tsin_a_clk_t_pins[] = { GPIOT_9 }; 427 + static const unsigned int tsin_a_valid_t_pins[] = { GPIOT_10 }; 428 + static const unsigned int i2c0_sck_t_pins[] = { GPIOT_20 }; 429 + static const unsigned int i2c0_sda_t_pins[] = { GPIOT_21 }; 430 + static const unsigned int i2c2_sck_t_pins[] = { GPIOT_22 }; 431 + static const unsigned int i2c2_sda_t_pins[] = { GPIOT_23 }; 432 + 433 + /* Bank T func3 */ 434 + static const unsigned int spi3_mosi_pins[] = { GPIOT_6 }; 435 + static const unsigned int spi3_miso_pins[] = { GPIOT_7 }; 436 + static const unsigned int spi3_sclk_pins[] = { GPIOT_8 }; 437 + static const unsigned int spi3_ss0_pins[] = { GPIOT_9 }; 438 + 439 + /* Bank M func1 */ 440 + static const unsigned int tdm_d12_pins[] = { GPIOM_0 }; 441 + static const unsigned int tdm_d13_pins[] = { GPIOM_1 }; 442 + static const unsigned int tdm_d14_pins[] = { GPIOM_2 }; 443 + static const unsigned int tdm_d15_pins[] = { GPIOM_3 }; 444 + static const unsigned int tdm_sclk3_pins[] = { GPIOM_4 }; 445 + static const unsigned int tdm_fs3_pins[] = { GPIOM_5 }; 446 + static const unsigned int i2c3_sda_m_pins[] = { GPIOM_6 }; 447 + static const unsigned int i2c3_sck_m_pins[] = { GPIOM_7 }; 448 + static const unsigned int spi1_mosi_m_pins[] = { GPIOM_8 }; 449 + static const unsigned int spi1_miso_m_pins[] = { GPIOM_9 }; 450 + static const unsigned int spi1_sclk_m_pins[] = { GPIOM_10 }; 451 + static const unsigned int spi1_ss0_m_pins[] = { GPIOM_11 }; 452 + static const unsigned int spi1_ss1_m_pins[] = { GPIOM_12 }; 453 + static const unsigned int spi1_ss2_m_pins[] = { GPIOM_13 }; 454 + 455 + /* Bank M func2 */ 456 + static const unsigned int pdm_din1_m0_pins[] = { GPIOM_0 }; 457 + static const unsigned int pdm_din2_pins[] = { GPIOM_1 }; 458 + static const unsigned int pdm_din3_pins[] = { GPIOM_2 }; 459 + static const unsigned int pdm_dclk_pins[] = { GPIOM_3 }; 460 + static const unsigned int pdm_din0_pins[] = { GPIOM_4 }; 461 + static const unsigned int pdm_din1_m5_pins[] = { GPIOM_5 }; 462 + static const unsigned int uart_d_tx_m_pins[] = { GPIOM_8 }; 463 + static const unsigned int uart_d_rx_m_pins[] = { GPIOM_9 }; 464 + static const unsigned int uart_d_cts_m_pins[] = { GPIOM_10 }; 465 + static const unsigned int uart_d_rts_m_pins[] = { GPIOM_11 }; 466 + static const unsigned int i2c2_sda_m_pins[] = { GPIOM_12 }; 467 + static const unsigned int i2c2_sck_m_pins[] = { GPIOM_13 }; 468 + 469 + /* Bank Y func1 */ 470 + static const unsigned int spi2_mosi_pins[] = { GPIOY_0 }; 471 + static const unsigned int spi2_miso_pins[] = { GPIOY_1 }; 472 + static const unsigned int spi2_sclk_pins[] = { GPIOY_2 }; 473 + static const unsigned int spi2_ss0_pins[] = { GPIOY_3 }; 474 + static const unsigned int spi2_ss1_pins[] = { GPIOY_4 }; 475 + static const unsigned int spi2_ss2_pins[] = { GPIOY_5 }; 476 + static const unsigned int uart_e_tx_pins[] = { GPIOY_6 }; 477 + static const unsigned int uart_e_rx_pins[] = { GPIOY_7 }; 478 + static const unsigned int uart_e_cts_pins[] = { GPIOY_8 }; 479 + static const unsigned int uart_e_rts_pins[] = { GPIOY_9 }; 480 + static const unsigned int uart_d_cts_y_pins[] = { GPIOY_10 }; 481 + static const unsigned int uart_d_rts_y_pins[] = { GPIOY_11 }; 482 + static const unsigned int uart_d_tx_y_pins[] = { GPIOY_12 }; 483 + static const unsigned int uart_d_rx_y_pins[] = { GPIOY_13 }; 484 + static const unsigned int i2c4_sck_y_pins[] = { GPIOY_15 }; 485 + static const unsigned int i2c4_sda_y_pins[] = { GPIOY_16 }; 486 + static const unsigned int i2c5_sck_pins[] = { GPIOY_17 }; 487 + static const unsigned int i2c5_sda_pins[] = { GPIOY_18 }; 488 + 489 + /* Bank Y func2 */ 490 + static const unsigned int tsin_c_y_sop_pins[] = { GPIOY_4 }; 491 + static const unsigned int tsin_c_y_din0_pins[] = { GPIOY_5 }; 492 + static const unsigned int tsin_c_y_clk_pins[] = { GPIOY_6 }; 493 + static const unsigned int tsin_c_y_valid_pins[] = { GPIOY_7 }; 494 + static const unsigned int tsin_d_y_sop_pins[] = { GPIOY_8 }; 495 + static const unsigned int tsin_d_y_din0_pins[] = { GPIOY_9 }; 496 + static const unsigned int tsin_d_y_clk_pins[] = { GPIOY_10 }; 497 + static const unsigned int tsin_d_y_valid_pins[] = { GPIOY_11 }; 498 + static const unsigned int pcieck_reqn_y_pins[] = { GPIOY_18 }; 499 + 500 + /* Bank Y func3 */ 501 + static const unsigned int pwm_e_pins[] = { GPIOY_1 }; 502 + static const unsigned int hsync_pins[] = { GPIOY_4 }; 503 + static const unsigned int vsync_pins[] = { GPIOY_5 }; 504 + static const unsigned int pwm_f_pins[] = { GPIOY_8 }; 505 + static const unsigned int sync_3d_out_pins[] = { GPIOY_9 }; 506 + static const unsigned int vx1_a_htpdn_pins[] = { GPIOY_10 }; 507 + static const unsigned int vx1_b_htpdn_pins[] = { GPIOY_11 }; 508 + static const unsigned int vx1_a_lockn_pins[] = { GPIOY_12 }; 509 + static const unsigned int vx1_b_lockn_pins[] = { GPIOY_13 }; 510 + static const unsigned int pwm_vs_y_pins[] = { GPIOY_14 }; 511 + 512 + /* Bank Y func4 */ 513 + static const unsigned int edp_a_hpd_pins[] = { GPIOY_10 }; 514 + static const unsigned int edp_b_hpd_pins[] = { GPIOY_11 }; 515 + 516 + /* Bank H func1 */ 517 + static const unsigned int mic_mute_key_pins[] = { GPIOH_0 }; 518 + static const unsigned int mic_mute_led_pins[] = { GPIOH_1 }; 519 + static const unsigned int i2c3_sck_h_pins[] = { GPIOH_2 }; 520 + static const unsigned int i2c3_sda_h_pins[] = { GPIOH_3 }; 521 + static const unsigned int i2c4_sck_h_pins[] = { GPIOH_4 }; 522 + static const unsigned int i2c4_sda_h_pins[] = { GPIOH_5 }; 523 + static const unsigned int eth_link_led_pins[] = { GPIOH_6 }; 524 + static const unsigned int eth_act_led_pins[] = { GPIOH_7 }; 525 + 526 + /* Bank H func2 */ 527 + static const unsigned int pwm_vs_h_pins[] = { GPIOH_1 }; 528 + static const unsigned int uart_f_tx_pins[] = { GPIOH_2 }; 529 + static const unsigned int uart_f_rx_pins[] = { GPIOH_3 }; 530 + static const unsigned int uart_f_cts_pins[] = { GPIOH_4 }; 531 + static const unsigned int uart_f_rts_pins[] = { GPIOH_5 }; 532 + static const unsigned int i2c0_sda_h_pins[] = { GPIOH_6 }; 533 + static const unsigned int i2c0_sck_h_pins[] = { GPIOH_7 }; 534 + 535 + /* Bank H func3 */ 536 + static const unsigned int pcieck_reqn_h_pins[] = { GPIOH_2 }; 537 + 538 + static struct meson_pmx_group t7_periphs_groups[] = { 539 + GPIO_GROUP(GPIOB_0), 540 + GPIO_GROUP(GPIOB_1), 541 + GPIO_GROUP(GPIOB_2), 542 + GPIO_GROUP(GPIOB_3), 543 + GPIO_GROUP(GPIOB_4), 544 + GPIO_GROUP(GPIOB_5), 545 + GPIO_GROUP(GPIOB_6), 546 + GPIO_GROUP(GPIOB_7), 547 + GPIO_GROUP(GPIOB_8), 548 + GPIO_GROUP(GPIOB_9), 549 + GPIO_GROUP(GPIOB_10), 550 + GPIO_GROUP(GPIOB_11), 551 + GPIO_GROUP(GPIOB_12), 552 + 553 + GPIO_GROUP(GPIOC_0), 554 + GPIO_GROUP(GPIOC_1), 555 + GPIO_GROUP(GPIOC_2), 556 + GPIO_GROUP(GPIOC_3), 557 + GPIO_GROUP(GPIOC_4), 558 + GPIO_GROUP(GPIOC_5), 559 + GPIO_GROUP(GPIOC_6), 560 + 561 + GPIO_GROUP(GPIOX_0), 562 + GPIO_GROUP(GPIOX_1), 563 + GPIO_GROUP(GPIOX_2), 564 + GPIO_GROUP(GPIOX_3), 565 + GPIO_GROUP(GPIOX_4), 566 + GPIO_GROUP(GPIOX_5), 567 + GPIO_GROUP(GPIOX_6), 568 + GPIO_GROUP(GPIOX_7), 569 + GPIO_GROUP(GPIOX_8), 570 + GPIO_GROUP(GPIOX_9), 571 + GPIO_GROUP(GPIOX_10), 572 + GPIO_GROUP(GPIOX_11), 573 + GPIO_GROUP(GPIOX_12), 574 + GPIO_GROUP(GPIOX_13), 575 + GPIO_GROUP(GPIOX_14), 576 + GPIO_GROUP(GPIOX_15), 577 + GPIO_GROUP(GPIOX_16), 578 + GPIO_GROUP(GPIOX_17), 579 + GPIO_GROUP(GPIOX_18), 580 + GPIO_GROUP(GPIOX_19), 581 + 582 + GPIO_GROUP(GPIOW_0), 583 + GPIO_GROUP(GPIOW_1), 584 + GPIO_GROUP(GPIOW_2), 585 + GPIO_GROUP(GPIOW_3), 586 + GPIO_GROUP(GPIOW_4), 587 + GPIO_GROUP(GPIOW_5), 588 + GPIO_GROUP(GPIOW_6), 589 + GPIO_GROUP(GPIOW_7), 590 + GPIO_GROUP(GPIOW_8), 591 + GPIO_GROUP(GPIOW_9), 592 + GPIO_GROUP(GPIOW_10), 593 + GPIO_GROUP(GPIOW_11), 594 + GPIO_GROUP(GPIOW_12), 595 + GPIO_GROUP(GPIOW_13), 596 + GPIO_GROUP(GPIOW_14), 597 + GPIO_GROUP(GPIOW_15), 598 + GPIO_GROUP(GPIOW_16), 599 + 600 + GPIO_GROUP(GPIOD_0), 601 + GPIO_GROUP(GPIOD_1), 602 + GPIO_GROUP(GPIOD_2), 603 + GPIO_GROUP(GPIOD_3), 604 + GPIO_GROUP(GPIOD_4), 605 + GPIO_GROUP(GPIOD_5), 606 + GPIO_GROUP(GPIOD_6), 607 + GPIO_GROUP(GPIOD_7), 608 + GPIO_GROUP(GPIOD_8), 609 + GPIO_GROUP(GPIOD_9), 610 + GPIO_GROUP(GPIOD_10), 611 + GPIO_GROUP(GPIOD_11), 612 + GPIO_GROUP(GPIOD_12), 613 + 614 + GPIO_GROUP(GPIOE_0), 615 + GPIO_GROUP(GPIOE_1), 616 + GPIO_GROUP(GPIOE_2), 617 + GPIO_GROUP(GPIOE_3), 618 + GPIO_GROUP(GPIOE_4), 619 + GPIO_GROUP(GPIOE_5), 620 + GPIO_GROUP(GPIOE_6), 621 + 622 + GPIO_GROUP(GPIOZ_0), 623 + GPIO_GROUP(GPIOZ_1), 624 + GPIO_GROUP(GPIOZ_2), 625 + GPIO_GROUP(GPIOZ_3), 626 + GPIO_GROUP(GPIOZ_4), 627 + GPIO_GROUP(GPIOZ_5), 628 + GPIO_GROUP(GPIOZ_6), 629 + GPIO_GROUP(GPIOZ_7), 630 + GPIO_GROUP(GPIOZ_8), 631 + GPIO_GROUP(GPIOZ_9), 632 + GPIO_GROUP(GPIOZ_10), 633 + GPIO_GROUP(GPIOZ_11), 634 + GPIO_GROUP(GPIOZ_12), 635 + GPIO_GROUP(GPIOZ_13), 636 + 637 + GPIO_GROUP(GPIOT_0), 638 + GPIO_GROUP(GPIOT_1), 639 + GPIO_GROUP(GPIOT_2), 640 + GPIO_GROUP(GPIOT_3), 641 + GPIO_GROUP(GPIOT_4), 642 + GPIO_GROUP(GPIOT_5), 643 + GPIO_GROUP(GPIOT_6), 644 + GPIO_GROUP(GPIOT_7), 645 + GPIO_GROUP(GPIOT_8), 646 + GPIO_GROUP(GPIOT_9), 647 + GPIO_GROUP(GPIOT_10), 648 + GPIO_GROUP(GPIOT_11), 649 + GPIO_GROUP(GPIOT_12), 650 + GPIO_GROUP(GPIOT_13), 651 + GPIO_GROUP(GPIOT_14), 652 + GPIO_GROUP(GPIOT_15), 653 + GPIO_GROUP(GPIOT_16), 654 + GPIO_GROUP(GPIOT_17), 655 + GPIO_GROUP(GPIOT_18), 656 + GPIO_GROUP(GPIOT_19), 657 + GPIO_GROUP(GPIOT_20), 658 + GPIO_GROUP(GPIOT_21), 659 + GPIO_GROUP(GPIOT_22), 660 + GPIO_GROUP(GPIOT_23), 661 + 662 + GPIO_GROUP(GPIOM_0), 663 + GPIO_GROUP(GPIOM_1), 664 + GPIO_GROUP(GPIOM_2), 665 + GPIO_GROUP(GPIOM_3), 666 + GPIO_GROUP(GPIOM_4), 667 + GPIO_GROUP(GPIOM_5), 668 + GPIO_GROUP(GPIOM_6), 669 + GPIO_GROUP(GPIOM_7), 670 + GPIO_GROUP(GPIOM_8), 671 + GPIO_GROUP(GPIOM_9), 672 + GPIO_GROUP(GPIOM_10), 673 + GPIO_GROUP(GPIOM_11), 674 + GPIO_GROUP(GPIOM_12), 675 + GPIO_GROUP(GPIOM_13), 676 + 677 + GPIO_GROUP(GPIOY_0), 678 + GPIO_GROUP(GPIOY_1), 679 + GPIO_GROUP(GPIOY_2), 680 + GPIO_GROUP(GPIOY_3), 681 + GPIO_GROUP(GPIOY_4), 682 + GPIO_GROUP(GPIOY_5), 683 + GPIO_GROUP(GPIOY_6), 684 + GPIO_GROUP(GPIOY_7), 685 + GPIO_GROUP(GPIOY_8), 686 + GPIO_GROUP(GPIOY_9), 687 + GPIO_GROUP(GPIOY_10), 688 + GPIO_GROUP(GPIOY_11), 689 + GPIO_GROUP(GPIOY_12), 690 + GPIO_GROUP(GPIOY_13), 691 + GPIO_GROUP(GPIOY_14), 692 + GPIO_GROUP(GPIOY_15), 693 + GPIO_GROUP(GPIOY_16), 694 + GPIO_GROUP(GPIOY_17), 695 + GPIO_GROUP(GPIOY_18), 696 + 697 + GPIO_GROUP(GPIOH_0), 698 + GPIO_GROUP(GPIOH_1), 699 + GPIO_GROUP(GPIOH_2), 700 + GPIO_GROUP(GPIOH_3), 701 + GPIO_GROUP(GPIOH_4), 702 + GPIO_GROUP(GPIOH_5), 703 + GPIO_GROUP(GPIOH_6), 704 + GPIO_GROUP(GPIOH_7), 705 + GPIO_GROUP(GPIO_TEST_N), 706 + 707 + /* Bank B func1 */ 708 + GROUP(emmc_nand_d0, 1), 709 + GROUP(emmc_nand_d1, 1), 710 + GROUP(emmc_nand_d2, 1), 711 + GROUP(emmc_nand_d3, 1), 712 + GROUP(emmc_nand_d4, 1), 713 + GROUP(emmc_nand_d5, 1), 714 + GROUP(emmc_nand_d6, 1), 715 + GROUP(emmc_nand_d7, 1), 716 + GROUP(emmc_clk, 1), 717 + GROUP(emmc_cmd, 1), 718 + GROUP(emmc_nand_ds, 1), 719 + 720 + /* Bank B func1 */ 721 + GROUP(nor_hold, 2), 722 + GROUP(nor_d, 2), 723 + GROUP(nor_q, 2), 724 + GROUP(nor_c, 2), 725 + GROUP(nor_wp, 2), 726 + GROUP(nor_cs, 2), 727 + 728 + /* Bank C func1 */ 729 + GROUP(sdcard_d0, 1), 730 + GROUP(sdcard_d1, 1), 731 + GROUP(sdcard_d2, 1), 732 + GROUP(sdcard_d3, 1), 733 + GROUP(sdcard_clk, 1), 734 + GROUP(sdcard_cmd, 1), 735 + GROUP(gen_clk_out_c, 1), 736 + 737 + /* Bank C func2 */ 738 + GROUP(jtag_b_tdo, 2), 739 + GROUP(jtag_b_tdi, 2), 740 + GROUP(uart_ao_a_rx_c, 2), 741 + GROUP(uart_ao_a_tx_c, 2), 742 + GROUP(jtag_b_clk, 2), 743 + GROUP(jtag_b_tms, 2), 744 + 745 + /* Bank C func3 */ 746 + GROUP(spi1_mosi_c, 3), 747 + GROUP(spi1_miso_c, 3), 748 + GROUP(spi1_sclk_c, 3), 749 + GROUP(spi1_ss0_c, 3), 750 + 751 + /* Bank X func1 */ 752 + GROUP(sdio_d0, 1), 753 + GROUP(sdio_d1, 1), 754 + GROUP(sdio_d2, 1), 755 + GROUP(sdio_d3, 1), 756 + GROUP(sdio_clk, 1), 757 + GROUP(sdio_cmd, 1), 758 + GROUP(pwm_b, 1), 759 + GROUP(pwm_c, 1), 760 + GROUP(tdm_d0, 1), 761 + GROUP(tdm_d1, 1), 762 + GROUP(tdm_fs0, 1), 763 + GROUP(tdm_sclk0, 1), 764 + GROUP(uart_c_tx, 1), 765 + GROUP(uart_c_rx, 1), 766 + GROUP(uart_c_cts, 1), 767 + GROUP(uart_c_rts, 1), 768 + GROUP(pwm_a, 1), 769 + GROUP(i2c2_sda_x, 1), 770 + GROUP(i2c2_sck_x, 1), 771 + GROUP(pwm_d, 1), 772 + 773 + /* Bank X func2 */ 774 + GROUP(clk12_24_x, 2), 775 + 776 + /* Bank W func1 */ 777 + GROUP(hdmirx_a_hpd, 1), 778 + GROUP(hdmirx_a_det, 1), 779 + GROUP(hdmirx_a_sda, 1), 780 + GROUP(hdmirx_a_sck, 1), 781 + GROUP(hdmirx_c_hpd, 1), 782 + GROUP(hdmirx_c_det, 1), 783 + GROUP(hdmirx_c_sda, 1), 784 + GROUP(hdmirx_c_sck, 1), 785 + GROUP(hdmirx_b_hpd, 1), 786 + GROUP(hdmirx_b_det, 1), 787 + GROUP(hdmirx_b_sda, 1), 788 + GROUP(hdmirx_b_sck, 1), 789 + GROUP(cec_a, 1), 790 + GROUP(hdmitx_sda_w13, 1), 791 + GROUP(hdmitx_sck_w14, 1), 792 + GROUP(hdmitx_hpd_in, 1), 793 + GROUP(cec_b, 1), 794 + 795 + /* Bank W func2 */ 796 + GROUP(uart_ao_a_tx_w2, 2), 797 + GROUP(uart_ao_a_rx_w3, 2), 798 + GROUP(uart_ao_a_tx_w6, 2), 799 + GROUP(uart_ao_a_rx_w7, 2), 800 + GROUP(uart_ao_a_tx_w10, 2), 801 + GROUP(uart_ao_a_rx_w11, 2), 802 + 803 + /* Bank W func3 */ 804 + GROUP(hdmitx_sda_w2, 3), 805 + GROUP(hdmitx_sck_w3, 3), 806 + 807 + /* Bank D func1 */ 808 + GROUP(uart_ao_a_tx_d0, 1), 809 + GROUP(uart_ao_a_rx_d1, 1), 810 + GROUP(i2c0_ao_sck_d, 1), 811 + GROUP(i2c0_ao_sda_d, 1), 812 + GROUP(remote_out_d4, 1), 813 + GROUP(remote_in, 1), 814 + GROUP(jtag_a_clk, 1), 815 + GROUP(jtag_a_tms, 1), 816 + GROUP(jtag_a_tdi, 1), 817 + GROUP(jtag_a_tdo, 1), 818 + GROUP(gen_clk_out_d, 1), 819 + GROUP(pwm_ao_g_d11, 1), 820 + GROUP(wd_rsto, 1), 821 + 822 + /* Bank D func2 */ 823 + GROUP(i2c0_slave_ao_sck, 2), 824 + GROUP(i2c0_slave_ao_sda, 2), 825 + GROUP(rtc_clk_in, 2), 826 + GROUP(pwm_ao_h_d5, 2), 827 + GROUP(pwm_ao_c_d, 2), 828 + GROUP(pwm_ao_g_d7, 2), 829 + GROUP(spdif_out_d, 2), 830 + GROUP(spdif_in_d, 2), 831 + GROUP(pwm_ao_h_d10, 2), 832 + 833 + /* Bank D func3 */ 834 + GROUP(uart_ao_b_tx, 3), 835 + GROUP(uart_ao_b_rx, 3), 836 + GROUP(uart_ao_b_cts, 3), 837 + GROUP(pwm_ao_c_hiz, 3), 838 + GROUP(pwm_ao_g_hiz, 3), 839 + GROUP(uart_ao_b_rts, 3), 840 + 841 + /* Bank D func4 */ 842 + GROUP(remote_out_d6, 4), 843 + 844 + /* Bank E func1 */ 845 + GROUP(pwm_ao_a, 1), 846 + GROUP(pwm_ao_b, 1), 847 + GROUP(pwm_ao_c_e, 1), 848 + GROUP(pwm_ao_d, 1), 849 + GROUP(pwm_ao_e, 1), 850 + GROUP(pwm_ao_f, 1), 851 + GROUP(pwm_ao_g_e, 1), 852 + 853 + /* Bank E func2 */ 854 + GROUP(i2c0_ao_sck_e, 2), 855 + GROUP(i2c0_ao_sda_e, 2), 856 + GROUP(clk25m, 2), 857 + GROUP(i2c1_ao_sck, 2), 858 + GROUP(i2c1_ao_sda, 2), 859 + GROUP(rtc_clk_out, 2), 860 + 861 + /* Bank E func3 */ 862 + GROUP(clk12_24_e, 3), 863 + 864 + /* Bank Z func1 */ 865 + GROUP(eth_mdio, 1), 866 + GROUP(eth_mdc, 1), 867 + GROUP(eth_rgmii_rx_clk, 1), 868 + GROUP(eth_rx_dv, 1), 869 + GROUP(eth_rxd0, 1), 870 + GROUP(eth_rxd1, 1), 871 + GROUP(eth_rxd2_rgmii, 1), 872 + GROUP(eth_rxd3_rgmii, 1), 873 + GROUP(eth_rgmii_tx_clk, 1), 874 + GROUP(eth_txen, 1), 875 + GROUP(eth_txd0, 1), 876 + GROUP(eth_txd1, 1), 877 + GROUP(eth_txd2_rgmii, 1), 878 + GROUP(eth_txd3_rgmii, 1), 879 + 880 + /* Bank Z func2 */ 881 + GROUP(iso7816_clk_z, 2), 882 + GROUP(iso7816_data_z, 2), 883 + GROUP(tsin_b_valid, 2), 884 + GROUP(tsin_b_sop, 2), 885 + GROUP(tsin_b_din0, 2), 886 + GROUP(tsin_b_clk, 2), 887 + GROUP(tsin_b_fail, 2), 888 + GROUP(tsin_b_din1, 2), 889 + GROUP(tsin_b_din2, 2), 890 + GROUP(tsin_b_din3, 2), 891 + GROUP(tsin_b_din4, 2), 892 + GROUP(tsin_b_din5, 2), 893 + GROUP(tsin_b_din6, 2), 894 + GROUP(tsin_b_din7, 2), 895 + 896 + /* Bank Z func3 */ 897 + GROUP(tsin_c_z_valid, 3), 898 + GROUP(tsin_c_z_sop, 3), 899 + GROUP(tsin_c_z_din0, 3), 900 + GROUP(tsin_c_z_clk, 3), 901 + GROUP(tsin_d_z_valid, 3), 902 + GROUP(tsin_d_z_sop, 3), 903 + GROUP(tsin_d_z_din0, 3), 904 + GROUP(tsin_d_z_clk, 3), 905 + 906 + /* Bank Z func4 */ 907 + GROUP(spi4_mosi, 4), 908 + GROUP(spi4_miso, 4), 909 + GROUP(spi4_sclk, 4), 910 + GROUP(spi4_ss0, 4), 911 + GROUP(spi5_mosi, 4), 912 + GROUP(spi5_miso, 4), 913 + GROUP(spi5_sclk, 4), 914 + GROUP(spi5_ss0, 4), 915 + 916 + /* Bank T func1 */ 917 + GROUP(mclk1, 1), 918 + GROUP(tdm_sclk1, 1), 919 + GROUP(tdm_fs1, 1), 920 + GROUP(tdm_d2, 1), 921 + GROUP(tdm_d3, 1), 922 + GROUP(tdm_d4, 1), 923 + GROUP(tdm_d5, 1), 924 + GROUP(tdm_d6, 1), 925 + GROUP(tdm_d7, 1), 926 + GROUP(tdm_d8, 1), 927 + GROUP(tdm_d9, 1), 928 + GROUP(tdm_d10, 1), 929 + GROUP(tdm_d11, 1), 930 + GROUP(mclk2, 1), 931 + GROUP(tdm_sclk2, 1), 932 + GROUP(tdm_fs2, 1), 933 + GROUP(i2c1_sck, 1), 934 + GROUP(i2c1_sda, 1), 935 + GROUP(spi0_mosi, 1), 936 + GROUP(spi0_miso, 1), 937 + GROUP(spi0_sclk, 1), 938 + GROUP(spi0_ss0, 1), 939 + GROUP(spi0_ss1, 1), 940 + GROUP(spi0_ss2, 1), 941 + 942 + /* Bank T func2 */ 943 + GROUP(spdif_in_t, 2), 944 + GROUP(spdif_out_t, 2), 945 + GROUP(iso7816_clk_t, 2), 946 + GROUP(iso7816_data_t, 2), 947 + GROUP(tsin_a_sop_t, 2), 948 + GROUP(tsin_a_din0_t, 2), 949 + GROUP(tsin_a_clk_t, 2), 950 + GROUP(tsin_a_valid_t, 2), 951 + GROUP(i2c0_sck_t, 2), 952 + GROUP(i2c0_sda_t, 2), 953 + GROUP(i2c2_sck_t, 2), 954 + GROUP(i2c2_sda_t, 2), 955 + 956 + /* Bank T func3 */ 957 + GROUP(spi3_mosi, 3), 958 + GROUP(spi3_miso, 3), 959 + GROUP(spi3_sclk, 3), 960 + GROUP(spi3_ss0, 3), 961 + 962 + /* Bank M func1 */ 963 + GROUP(tdm_d12, 1), 964 + GROUP(tdm_d13, 1), 965 + GROUP(tdm_d14, 1), 966 + GROUP(tdm_d15, 1), 967 + GROUP(tdm_sclk3, 1), 968 + GROUP(tdm_fs3, 1), 969 + GROUP(i2c3_sda_m, 1), 970 + GROUP(i2c3_sck_m, 1), 971 + GROUP(spi1_mosi_m, 1), 972 + GROUP(spi1_miso_m, 1), 973 + GROUP(spi1_sclk_m, 1), 974 + GROUP(spi1_ss0_m, 1), 975 + GROUP(spi1_ss1_m, 1), 976 + GROUP(spi1_ss2_m, 1), 977 + 978 + /* Bank M func2 */ 979 + GROUP(pdm_din1_m0, 2), 980 + GROUP(pdm_din2, 2), 981 + GROUP(pdm_din3, 2), 982 + GROUP(pdm_dclk, 2), 983 + GROUP(pdm_din0, 2), 984 + GROUP(pdm_din1_m5, 2), 985 + GROUP(uart_d_tx_m, 2), 986 + GROUP(uart_d_rx_m, 2), 987 + GROUP(uart_d_cts_m, 2), 988 + GROUP(uart_d_rts_m, 2), 989 + GROUP(i2c2_sda_m, 2), 990 + GROUP(i2c2_sck_m, 2), 991 + 992 + /* Bank Y func1 */ 993 + GROUP(spi2_mosi, 1), 994 + GROUP(spi2_miso, 1), 995 + GROUP(spi2_sclk, 1), 996 + GROUP(spi2_ss0, 1), 997 + GROUP(spi2_ss1, 1), 998 + GROUP(spi2_ss2, 1), 999 + GROUP(uart_e_tx, 1), 1000 + GROUP(uart_e_rx, 1), 1001 + GROUP(uart_e_cts, 1), 1002 + GROUP(uart_e_rts, 1), 1003 + GROUP(uart_d_cts_y, 1), 1004 + GROUP(uart_d_rts_y, 1), 1005 + GROUP(uart_d_tx_y, 1), 1006 + GROUP(uart_d_rx_y, 1), 1007 + GROUP(i2c4_sck_y, 1), 1008 + GROUP(i2c4_sda_y, 1), 1009 + GROUP(i2c5_sck, 1), 1010 + GROUP(i2c5_sda, 1), 1011 + 1012 + /* Bank Y func2 */ 1013 + GROUP(tsin_c_y_sop, 2), 1014 + GROUP(tsin_c_y_din0, 2), 1015 + GROUP(tsin_c_y_clk, 2), 1016 + GROUP(tsin_c_y_valid, 2), 1017 + GROUP(tsin_d_y_sop, 2), 1018 + GROUP(tsin_d_y_din0, 2), 1019 + GROUP(tsin_d_y_clk, 2), 1020 + GROUP(tsin_d_y_valid, 2), 1021 + GROUP(pcieck_reqn_y, 2), 1022 + 1023 + /* Bank Y func3 */ 1024 + GROUP(pwm_e, 3), 1025 + GROUP(hsync, 3), 1026 + GROUP(vsync, 3), 1027 + GROUP(pwm_f, 3), 1028 + GROUP(sync_3d_out, 3), 1029 + GROUP(vx1_a_htpdn, 3), 1030 + GROUP(vx1_b_htpdn, 3), 1031 + GROUP(vx1_a_lockn, 3), 1032 + GROUP(vx1_b_lockn, 3), 1033 + GROUP(pwm_vs_y, 3), 1034 + 1035 + /* Bank Y func4 */ 1036 + GROUP(edp_a_hpd, 4), 1037 + GROUP(edp_b_hpd, 4), 1038 + 1039 + /* Bank H func1 */ 1040 + GROUP(mic_mute_key, 1), 1041 + GROUP(mic_mute_led, 1), 1042 + GROUP(i2c3_sck_h, 1), 1043 + GROUP(i2c3_sda_h, 1), 1044 + GROUP(i2c4_sck_h, 1), 1045 + GROUP(i2c4_sda_h, 1), 1046 + GROUP(eth_link_led, 1), 1047 + GROUP(eth_act_led, 1), 1048 + 1049 + /* Bank H func2 */ 1050 + GROUP(pwm_vs_h, 2), 1051 + GROUP(uart_f_tx, 2), 1052 + GROUP(uart_f_rx, 2), 1053 + GROUP(uart_f_cts, 2), 1054 + GROUP(uart_f_rts, 2), 1055 + GROUP(i2c0_sda_h, 2), 1056 + GROUP(i2c0_sck_h, 2), 1057 + 1058 + /* Bank H func3 */ 1059 + GROUP(pcieck_reqn_h, 3), 1060 + }; 1061 + 1062 + static const char * const gpio_periphs_groups[] = { 1063 + "GPIOB_0", "GPIOB_1", "GPIOB_2", "GPIOB_3", "GPIOB_4", "GPIOB_5", 1064 + "GPIOB_6", "GPIOB_7", "GPIOB_8", "GPIOB_9", "GPIOB_10", 1065 + "GPIOB_11", "GPIOB_12", 1066 + 1067 + "GPIOC_0", "GPIOC_1", "GPIOC_2", "GPIOC_3", "GPIOC_4", "GPIOC_5", 1068 + "GPIOC_6", 1069 + 1070 + "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", "GPIOX_5", 1071 + "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", "GPIOX_10", "GPIOX_11", 1072 + "GPIOX_12", "GPIOX_13", "GPIOX_14", "GPIOX_15", "GPIOX_16", "GPIOX_17", 1073 + "GPIOX_18", "GPIOX_19", 1074 + 1075 + "GPIOW_0", "GPIOW_1", "GPIOW_2", "GPIOW_3", "GPIOW_4", "GPIOW_5", 1076 + "GPIOW_6", "GPIOW_7", "GPIOW_8", "GPIOW_9", "GPIOW_10", "GPIOW_11", 1077 + "GPIOW_12", "GPIOW_13", "GPIOW_14", "GPIOW_15", "GPIOW_16", 1078 + 1079 + "GPIOD_0", "GPIOD_1", "GPIOD_2", "GPIOD_3", "GPIOD_4", "GPIOD_5", 1080 + "GPIOD_6", "GPIOD_7", "GPIOD_8", "GPIOD_9", "GPIOD_10", "GPIOD_11", 1081 + "GPIOD_12", 1082 + 1083 + "GPIOE_0", "GPIOE_1", "GPIOE_2", "GPIOE_3", "GPIOE_4", "GPIOE_5", 1084 + "GPIOE_6", 1085 + 1086 + "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4", "GPIOZ_5", 1087 + "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9", "GPIOZ_10", "GPIOZ_11", 1088 + "GPIOZ_12", "GPIOZ_13", 1089 + 1090 + "GPIOT_0", "GPIOT_1", "GPIOT_2", "GPIOT_3", "GPIOT_4", "GPIOT_5", 1091 + "GPIOT_6", "GPIOT_7", "GPIOT_8", "GPIOT_9", "GPIOT_10", "GPIOT_11", 1092 + "GPIOT_12", "GPIOT_13", "GPIOT_14", "GPIOT_15", "GPIOT_16", 1093 + "GPIOT_17", "GPIOT_18", "GPIOT_19", "GPIOT_20", "GPIOT_21", 1094 + "GPIOT_22", "GPIOT_23", 1095 + 1096 + "GPIOM_0", "GPIOM_1", "GPIOM_2", "GPIOM_3", "GPIOM_4", "GPIOM_5", 1097 + "GPIOM_6", "GPIOM_7", "GPIOM_8", "GPIOM_9", "GPIOM_10", "GPIOM_11", 1098 + "GPIOM_12", "GPIOM_13", 1099 + 1100 + "GPIOY_0", "GPIOY_1", "GPIOY_2", "GPIOY_3", "GPIOY_4", "GPIOY_5", 1101 + "GPIOY_6", "GPIOY_7", "GPIOY_8", "GPIOY_9", "GPIOY_10", "GPIOY_11", 1102 + "GPIOY_12", "GPIOY_13", "GPIOY_14", "GPIOY_15", "GPIOY_16", 1103 + "GPIOY_17", "GPIOY_18", 1104 + 1105 + "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4", "GPIOH_5", 1106 + "GPIOH_6", "GPIOH_7", 1107 + 1108 + "GPIO_TEST_N", 1109 + }; 1110 + 1111 + static const char * const emmc_groups[] = { 1112 + "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3", 1113 + "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7", 1114 + "emmc_clk", "emmc_cmd", "emmc_nand_ds", 1115 + }; 1116 + 1117 + static const char * const nor_groups[] = { 1118 + "nor_hold", "nor_d", "nor_q", "nor_c", "nor_wp", "nor_cs", 1119 + }; 1120 + 1121 + static const char * const sdcard_groups[] = { 1122 + "sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3", "sdcard_clk", 1123 + "sdcard_cmd", 1124 + }; 1125 + 1126 + static const char * const sdio_groups[] = { 1127 + "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", "sdio_clk", "sdio_cmd", 1128 + }; 1129 + 1130 + static const char * const gen_clk_groups[] = { 1131 + "gen_clk_out_c", "gen_clk_out_d", 1132 + }; 1133 + 1134 + static const char * const jtag_a_groups[] = { 1135 + "jtag_a_clk", "jtag_a_tms", "jtag_a_tdi", "jtag_a_tdo", 1136 + }; 1137 + 1138 + static const char * const jtag_b_groups[] = { 1139 + "jtag_b_tdo", "jtag_b_tdi", "jtag_b_clk", "jtag_b_tms", 1140 + }; 1141 + 1142 + static const char * const uart_c_groups[] = { 1143 + "uart_c_tx", "uart_c_rx", "uart_c_cts", "uart_c_rts", 1144 + }; 1145 + 1146 + static const char * const uart_d_groups[] = { 1147 + "uart_d_tx_m", "uart_d_rx_m", "uart_d_cts_m", "uart_d_rts_m", 1148 + "uart_d_rts_y", "uart_d_tx_y", "uart_d_rx_y", "uart_d_cts_y", 1149 + }; 1150 + 1151 + static const char * const uart_e_groups[] = { 1152 + "uart_e_tx", "uart_e_rx", "uart_e_cts", "uart_e_rts", 1153 + }; 1154 + 1155 + static const char * const uart_f_groups[] = { 1156 + "uart_f_tx", "uart_f_rx", "uart_f_cts", "uart_f_rts", 1157 + }; 1158 + 1159 + static const char * const uart_ao_a_groups[] = { 1160 + "uart_ao_a_rx_c", "uart_ao_a_tx_c", "uart_ao_a_tx_w2", 1161 + "uart_ao_a_rx_w3", "uart_ao_a_tx_w6", "uart_ao_a_rx_w7", 1162 + "uart_ao_a_tx_w10", "uart_ao_a_rx_w11", "uart_ao_a_tx_d0", 1163 + "uart_ao_a_rx_d1", 1164 + }; 1165 + 1166 + static const char * const uart_ao_b_groups[] = { 1167 + "uart_ao_b_tx", "uart_ao_b_rx", "uart_ao_b_cts", "uart_ao_b_rts", 1168 + }; 1169 + 1170 + static const char * const spi0_groups[] = { 1171 + "spi0_mosi", "spi0_miso", "spi0_sclk", "spi0_ss0", "spi0_ss1", 1172 + "spi0_ss2", 1173 + }; 1174 + 1175 + static const char * const spi1_groups[] = { 1176 + "spi1_mosi_c", "spi1_miso_c", "spi1_sclk_c", "spi1_ss0_c", 1177 + "spi1_mosi_m", "spi1_miso_m", "spi1_sclk_m", "spi1_ss0_m", 1178 + "spi1_ss1_m", "spi1_ss2_m", 1179 + }; 1180 + 1181 + static const char * const spi2_groups[] = { 1182 + "spi2_mosi", "spi2_miso", "spi2_sclk", "spi2_ss0", "spi2_ss1", 1183 + "spi2_ss2", 1184 + }; 1185 + 1186 + static const char * const spi3_groups[] = { 1187 + "spi3_mosi", "spi3_miso", "spi3_sclk", "spi3_ss0", 1188 + }; 1189 + 1190 + static const char * const spi4_groups[] = { 1191 + "spi4_mosi", "spi4_miso", "spi4_sclk", "spi4_ss0", 1192 + }; 1193 + 1194 + static const char * const spi5_groups[] = { 1195 + "spi5_mosi", "spi5_miso", "spi5_sclk", "spi5_ss0", 1196 + }; 1197 + 1198 + static const char * const pwm_a_groups[] = { 1199 + "pwm_a", 1200 + }; 1201 + 1202 + static const char * const pwm_b_groups[] = { 1203 + "pwm_b", 1204 + }; 1205 + 1206 + static const char * const pwm_c_groups[] = { 1207 + "pwm_c", 1208 + }; 1209 + 1210 + static const char * const pwm_d_groups[] = { 1211 + "pwm_d", 1212 + }; 1213 + 1214 + static const char * const pwm_e_groups[] = { 1215 + "pwm_e", 1216 + }; 1217 + 1218 + static const char * const pwm_f_groups[] = { 1219 + "pwm_f", 1220 + }; 1221 + 1222 + static const char * const pwm_ao_c_hiz_groups[] = { 1223 + "pwm_ao_c_hiz", 1224 + }; 1225 + 1226 + static const char * const pwm_ao_g_hiz_groups[] = { 1227 + "pwm_ao_g_hiz", 1228 + }; 1229 + 1230 + static const char * const pwm_ao_a_groups[] = { 1231 + "pwm_ao_a", 1232 + }; 1233 + 1234 + static const char * const pwm_ao_b_groups[] = { 1235 + "pwm_ao_b", 1236 + }; 1237 + 1238 + static const char * const pwm_ao_c_groups[] = { 1239 + "pwm_ao_c_d", "pwm_ao_c_e", 1240 + }; 1241 + 1242 + static const char * const pwm_ao_d_groups[] = { 1243 + "pwm_ao_d", 1244 + }; 1245 + 1246 + static const char * const pwm_ao_e_groups[] = { 1247 + "pwm_ao_e", 1248 + }; 1249 + 1250 + static const char * const pwm_ao_f_groups[] = { 1251 + "pwm_ao_f", 1252 + }; 1253 + 1254 + static const char * const pwm_ao_h_groups[] = { 1255 + "pwm_ao_h_d5", "pwm_ao_h_d10", 1256 + }; 1257 + 1258 + static const char * const pwm_ao_g_groups[] = { 1259 + "pwm_ao_g_d11", "pwm_ao_g_d7", "pwm_ao_g_e", 1260 + }; 1261 + 1262 + static const char * const pwm_vs_groups[] = { 1263 + "pwm_vs_y", "pwm_vs_h", 1264 + }; 1265 + 1266 + static const char * const tdm_groups[] = { 1267 + "tdm_d0", "tdm_d1", "tdm_fs0", "tdm_sclk0", "tdm_sclk1", "tdm_fs1", 1268 + "tdm_d2", "tdm_d3", "tdm_d4", "tdm_d5", "tdm_d6", "tdm_d7", 1269 + "tdm_d8", "tdm_d9", "tdm_d10", "tdm_d11", "tdm_sclk2", "tdm_fs2", 1270 + "tdm_d12", "tdm_d13", "tdm_d14", "tdm_d15", "tdm_sclk3", "tdm_fs3", 1271 + }; 1272 + 1273 + static const char * const i2c0_slave_ao_groups[] = { 1274 + "i2c0_slave_ao_sck", "i2c0_slave_ao_sda", 1275 + }; 1276 + 1277 + static const char * const i2c0_ao_groups[] = { 1278 + "i2c0_ao_sck_d", "i2c0_ao_sda_d", 1279 + "i2c0_ao_sck_e", "i2c0_ao_sda_e", 1280 + }; 1281 + 1282 + static const char * const i2c1_ao_groups[] = { 1283 + "i2c1_ao_sck", "i2c1_ao_sda", 1284 + }; 1285 + 1286 + static const char * const i2c0_groups[] = { 1287 + "i2c0_sck_t", "i2c0_sda_t", "i2c0_sck_h", "i2c0_sda_h", 1288 + }; 1289 + 1290 + static const char * const i2c1_groups[] = { 1291 + "i2c1_sck", "i2c1_sda", 1292 + }; 1293 + 1294 + static const char * const i2c2_groups[] = { 1295 + "i2c2_sda_x", "i2c2_sck_x", 1296 + "i2c2_sda_t", "i2c2_sck_t", 1297 + "i2c2_sda_m", "i2c2_sck_m", 1298 + }; 1299 + 1300 + static const char * const i2c3_groups[] = { 1301 + "i2c3_sda_m", "i2c3_sck_m", "i2c3_sck_h", "i2c3_sda_h", 1302 + }; 1303 + 1304 + static const char * const i2c4_groups[] = { 1305 + "i2c4_sck_y", "i2c4_sda_y", "i2c4_sck_h", "i2c4_sda_h", 1306 + }; 1307 + 1308 + static const char * const i2c5_groups[] = { 1309 + "i2c5_sck", "i2c5_sda", 1310 + }; 1311 + 1312 + static const char * const clk12_24_groups[] = { 1313 + "clk12_24_x", "clk12_24_e", 1314 + }; 1315 + 1316 + static const char * const hdmirx_a_groups[] = { 1317 + "hdmirx_a_hpd", "hdmirx_a_det", "hdmirx_a_sda", "hdmirx_a_sck", 1318 + }; 1319 + 1320 + static const char * const hdmirx_b_groups[] = { 1321 + "hdmirx_b_hpd", "hdmirx_b_det", "hdmirx_b_sda", "hdmirx_b_sck", 1322 + }; 1323 + 1324 + static const char * const hdmirx_c_groups[] = { 1325 + "hdmirx_c_hpd", "hdmirx_c_det", "hdmirx_c_sda", "hdmirx_c_sck", 1326 + }; 1327 + 1328 + static const char * const cec_a_groups[] = { 1329 + "cec_a", 1330 + }; 1331 + 1332 + static const char * const cec_b_groups[] = { 1333 + "cec_b", 1334 + }; 1335 + 1336 + static const char * const hdmitx_groups[] = { 1337 + "hdmitx_sda_w13", "hdmitx_sck_w14", "hdmitx_hpd_in", 1338 + "hdmitx_sda_w2", "hdmitx_sck_w3", 1339 + }; 1340 + 1341 + static const char * const remote_out_groups[] = { 1342 + "remote_out_d4", "remote_out_d6", 1343 + }; 1344 + 1345 + static const char * const remote_in_groups[] = { 1346 + "remote_in", 1347 + }; 1348 + 1349 + static const char * const wd_rsto_groups[] = { 1350 + "wd_rsto", 1351 + }; 1352 + 1353 + static const char * const rtc_clk_groups[] = { 1354 + "rtc_clk_in", "rtc_clk_out", 1355 + }; 1356 + 1357 + static const char * const spdif_out_groups[] = { 1358 + "spdif_out_d", "spdif_out_t", 1359 + }; 1360 + 1361 + static const char * const spdif_in_groups[] = { 1362 + "spdif_in_d", "spdif_in_t", 1363 + }; 1364 + 1365 + static const char * const clk25m_groups[] = { 1366 + "clk25m", 1367 + }; 1368 + 1369 + static const char * const eth_groups[] = { 1370 + "eth_mdio", "eth_mdc", "eth_rgmii_rx_clk", "eth_rx_dv", "eth_rxd0", 1371 + "eth_rxd1", "eth_rxd2_rgmii", "eth_rxd3_rgmii", "eth_rgmii_tx_clk", 1372 + "eth_txen", "eth_txd0", "eth_txd1", "eth_txd2_rgmii", 1373 + "eth_txd3_rgmii", "eth_link_led", "eth_act_led", 1374 + }; 1375 + 1376 + static const char * const iso7816_groups[] = { 1377 + "iso7816_clk_z", "iso7816_data_z", 1378 + "iso7816_clk_t", "iso7816_data_t", 1379 + }; 1380 + 1381 + static const char * const tsin_a_groups[] = { 1382 + "tsin_a_sop_t", "tsin_a_din0_t", "tsin_a_clk_t", "tsin_a_valid_t", 1383 + }; 1384 + 1385 + static const char * const tsin_b_groups[] = { 1386 + "tsin_b_valid", "tsin_b_sop", "tsin_b_din0", "tsin_b_clk", 1387 + "tsin_b_fail", "tsin_b_din1", "tsin_b_din2", "tsin_b_din3", 1388 + "tsin_b_din4", "tsin_b_din5", "tsin_b_din6", "tsin_b_din7", 1389 + }; 1390 + 1391 + static const char * const tsin_c_groups[] = { 1392 + "tsin_c_z_valid", "tsin_c_z_sop", "tsin_c_z_din0", "tsin_c_z_clk", 1393 + "tsin_c_y_sop", "tsin_c_y_din0", "tsin_c_y_clk", "tsin_c_y_valid", 1394 + }; 1395 + 1396 + static const char * const tsin_d_groups[] = { 1397 + "tsin_d_z_valid", "tsin_d_z_sop", "tsin_d_z_din0", "tsin_d_z_clk", 1398 + "tsin_d_y_sop", "tsin_d_y_din0", "tsin_d_y_clk", "tsin_d_y_valid", 1399 + }; 1400 + 1401 + static const char * const mclk_groups[] = { 1402 + "mclk1", "mclk2", 1403 + }; 1404 + 1405 + static const char * const pdm_groups[] = { 1406 + "pdm_din1_m0", "pdm_din2", "pdm_din3", "pdm_dclk", "pdm_din0", 1407 + "pdm_din1_m5", 1408 + }; 1409 + 1410 + static const char * const pcieck_groups[] = { 1411 + "pcieck_reqn_y", "pcieck_reqn_h", 1412 + }; 1413 + 1414 + static const char * const hsync_groups[] = { 1415 + "hsync", 1416 + }; 1417 + 1418 + static const char * const vsync_groups[] = { 1419 + "vsync", 1420 + }; 1421 + 1422 + static const char * const sync_3d_groups[] = { 1423 + "sync_3d_out", 1424 + }; 1425 + 1426 + static const char * const vx1_a_groups[] = { 1427 + "vx1_a_htpdn", "vx1_a_lockn", 1428 + }; 1429 + 1430 + static const char * const vx1_b_groups[] = { 1431 + "vx1_b_htpdn", "vx1_b_lockn", 1432 + }; 1433 + 1434 + static const char * const edp_a_groups[] = { 1435 + "edp_a_hpd", 1436 + }; 1437 + 1438 + static const char * const edp_b_groups[] = { 1439 + "edp_b_hpd", 1440 + }; 1441 + 1442 + static const char * const mic_mute_groups[] = { 1443 + "mic_mute_key", "mic_mute_led", 1444 + }; 1445 + 1446 + static struct meson_pmx_func t7_periphs_functions[] = { 1447 + FUNCTION(gpio_periphs), 1448 + FUNCTION(emmc), 1449 + FUNCTION(nor), 1450 + FUNCTION(sdcard), 1451 + FUNCTION(sdio), 1452 + FUNCTION(gen_clk), 1453 + FUNCTION(jtag_a), 1454 + FUNCTION(jtag_b), 1455 + FUNCTION(uart_c), 1456 + FUNCTION(uart_d), 1457 + FUNCTION(uart_e), 1458 + FUNCTION(uart_f), 1459 + FUNCTION(uart_ao_a), 1460 + FUNCTION(uart_ao_b), 1461 + FUNCTION(spi0), 1462 + FUNCTION(spi1), 1463 + FUNCTION(spi2), 1464 + FUNCTION(spi3), 1465 + FUNCTION(spi4), 1466 + FUNCTION(spi5), 1467 + FUNCTION(pwm_a), 1468 + FUNCTION(pwm_b), 1469 + FUNCTION(pwm_c), 1470 + FUNCTION(pwm_d), 1471 + FUNCTION(pwm_e), 1472 + FUNCTION(pwm_f), 1473 + FUNCTION(pwm_ao_c_hiz), 1474 + FUNCTION(pwm_ao_g_hiz), 1475 + FUNCTION(pwm_ao_a), 1476 + FUNCTION(pwm_ao_b), 1477 + FUNCTION(pwm_ao_c), 1478 + FUNCTION(pwm_ao_d), 1479 + FUNCTION(pwm_ao_e), 1480 + FUNCTION(pwm_ao_f), 1481 + FUNCTION(pwm_ao_h), 1482 + FUNCTION(pwm_ao_g), 1483 + FUNCTION(pwm_vs), 1484 + FUNCTION(tdm), 1485 + FUNCTION(i2c0_slave_ao), 1486 + FUNCTION(i2c0_ao), 1487 + FUNCTION(i2c1_ao), 1488 + FUNCTION(i2c0), 1489 + FUNCTION(i2c1), 1490 + FUNCTION(i2c2), 1491 + FUNCTION(i2c3), 1492 + FUNCTION(i2c4), 1493 + FUNCTION(i2c5), 1494 + FUNCTION(clk12_24), 1495 + FUNCTION(hdmirx_a), 1496 + FUNCTION(hdmirx_b), 1497 + FUNCTION(hdmirx_c), 1498 + FUNCTION(cec_a), 1499 + FUNCTION(cec_b), 1500 + FUNCTION(hdmitx), 1501 + FUNCTION(remote_out), 1502 + FUNCTION(remote_in), 1503 + FUNCTION(wd_rsto), 1504 + FUNCTION(rtc_clk), 1505 + FUNCTION(spdif_out), 1506 + FUNCTION(spdif_in), 1507 + FUNCTION(clk25m), 1508 + FUNCTION(eth), 1509 + FUNCTION(iso7816), 1510 + FUNCTION(tsin_a), 1511 + FUNCTION(tsin_b), 1512 + FUNCTION(tsin_c), 1513 + FUNCTION(tsin_d), 1514 + FUNCTION(mclk), 1515 + FUNCTION(pdm), 1516 + FUNCTION(pcieck), 1517 + FUNCTION(hsync), 1518 + FUNCTION(vsync), 1519 + FUNCTION(sync_3d), 1520 + FUNCTION(vx1_a), 1521 + FUNCTION(vx1_b), 1522 + FUNCTION(edp_a), 1523 + FUNCTION(edp_b), 1524 + FUNCTION(mic_mute), 1525 + }; 1526 + 1527 + static struct meson_bank t7_periphs_banks[] = { 1528 + /* name first last irq pullen pull dir out in ds */ 1529 + BANK_DS("D", GPIOD_0, GPIOD_12, 57, 69, 1530 + 0x03, 0, 0x04, 0, 0x02, 0, 0x01, 0, 0x00, 0, 0x07, 0), 1531 + BANK_DS("E", GPIOE_0, GPIOE_6, 70, 76, 1532 + 0x0b, 0, 0x0c, 0, 0x0a, 0, 0x09, 0, 0x08, 0, 0x0f, 0), 1533 + BANK_DS("Z", GPIOZ_0, GPIOZ_13, 77, 90, 1534 + 0x13, 0, 0x14, 0, 0x12, 0, 0x11, 0, 0x10, 0, 0x17, 0), 1535 + BANK_DS("H", GPIOH_0, GPIOH_7, 148, 155, 1536 + 0x1b, 0, 0x1c, 0, 0x1a, 0, 0x19, 0, 0x18, 0, 0x1f, 0), 1537 + BANK_DS("C", GPIOC_0, GPIOC_6, 13, 19, 1538 + 0x23, 0, 0x24, 0, 0x22, 0, 0x21, 0, 0x20, 0, 0x27, 0), 1539 + BANK_DS("B", GPIOB_0, GPIOB_12, 0, 12, 1540 + 0x2b, 0, 0x2c, 0, 0x2a, 0, 0x29, 0, 0x28, 0, 0x2f, 0), 1541 + BANK_DS("X", GPIOX_0, GPIOX_19, 20, 39, 1542 + 0x33, 0, 0x34, 0, 0x32, 0, 0x31, 0, 0x30, 0, 0x37, 0), 1543 + BANK_DS("T", GPIOT_0, GPIOT_23, 91, 114, 1544 + 0x43, 0, 0x44, 0, 0x42, 0, 0x41, 0, 0x40, 0, 0x47, 0), 1545 + BANK_DS("Y", GPIOY_0, GPIOY_18, 129, 147, 1546 + 0x53, 0, 0x54, 0, 0x52, 0, 0x51, 0, 0x50, 0, 0x57, 0), 1547 + BANK_DS("W", GPIOW_0, GPIOW_16, 40, 56, 1548 + 0x63, 0, 0x64, 0, 0x62, 0, 0x61, 0, 0x60, 0, 0x67, 0), 1549 + BANK_DS("M", GPIOM_0, GPIOM_13, 115, 128, 1550 + 0x73, 0, 0x74, 0, 0x72, 0, 0x71, 0, 0x70, 0, 0x77, 0), 1551 + BANK_DS("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 156, 156, 1552 + 0x83, 0, 0x84, 0, 0x82, 0, 0x81, 0, 0x80, 0, 0x87, 0), 1553 + }; 1554 + 1555 + static struct meson_pmx_bank t7_periphs_pmx_banks[] = { 1556 + /* name first last reg offset */ 1557 + BANK_PMX("D", GPIOD_0, GPIOD_12, 0x0a, 0), 1558 + BANK_PMX("E", GPIOE_0, GPIOE_6, 0x0c, 0), 1559 + BANK_PMX("Z", GPIOZ_0, GPIOZ_13, 0x05, 0), 1560 + BANK_PMX("H", GPIOH_0, GPIOH_7, 0x08, 0), 1561 + BANK_PMX("C", GPIOC_0, GPIOC_6, 0x07, 0), 1562 + BANK_PMX("B", GPIOB_0, GPIOB_12, 0x00, 0), 1563 + BANK_PMX("X", GPIOX_0, GPIOX_19, 0x02, 0), 1564 + BANK_PMX("T", GPIOT_0, GPIOT_23, 0x0f, 0), 1565 + BANK_PMX("Y", GPIOY_0, GPIOY_18, 0x13, 0), 1566 + BANK_PMX("W", GPIOW_0, GPIOW_16, 0x16, 0), 1567 + BANK_PMX("M", GPIOM_0, GPIOM_13, 0x0d, 0), 1568 + BANK_PMX("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 0x09, 0), 1569 + }; 1570 + 1571 + static struct meson_axg_pmx_data t7_periphs_pmx_banks_data = { 1572 + .pmx_banks = t7_periphs_pmx_banks, 1573 + .num_pmx_banks = ARRAY_SIZE(t7_periphs_pmx_banks), 1574 + }; 1575 + 1576 + static struct meson_pinctrl_data t7_periphs_pinctrl_data = { 1577 + .name = "periphs-banks", 1578 + .pins = t7_periphs_pins, 1579 + .groups = t7_periphs_groups, 1580 + .funcs = t7_periphs_functions, 1581 + .banks = t7_periphs_banks, 1582 + .num_pins = ARRAY_SIZE(t7_periphs_pins), 1583 + .num_groups = ARRAY_SIZE(t7_periphs_groups), 1584 + .num_funcs = ARRAY_SIZE(t7_periphs_functions), 1585 + .num_banks = ARRAY_SIZE(t7_periphs_banks), 1586 + .pmx_ops = &meson_axg_pmx_ops, 1587 + .pmx_data = &t7_periphs_pmx_banks_data, 1588 + .parse_dt = &meson_a1_parse_dt_extra, 1589 + }; 1590 + 1591 + static const struct of_device_id t7_pinctrl_dt_match[] = { 1592 + { 1593 + .compatible = "amlogic,t7-periphs-pinctrl", 1594 + .data = &t7_periphs_pinctrl_data, 1595 + }, 1596 + { } 1597 + }; 1598 + MODULE_DEVICE_TABLE(of, t7_pinctrl_dt_match); 1599 + 1600 + static struct platform_driver t7_pinctrl_driver = { 1601 + .probe = meson_pinctrl_probe, 1602 + .driver = { 1603 + .name = "amlogic-t7-pinctrl", 1604 + .of_match_table = t7_pinctrl_dt_match, 1605 + }, 1606 + }; 1607 + module_platform_driver(t7_pinctrl_driver); 1608 + 1609 + MODULE_AUTHOR("Huqiang Qin <huqiang.qin@amlogic.com>"); 1610 + MODULE_DESCRIPTION("Pin controller and GPIO driver for Amlogic T7 SoC"); 1611 + MODULE_LICENSE("Dual BSD/GPL");
+179
include/dt-bindings/gpio/amlogic,t7-periphs-pinctrl.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ 2 + /* 3 + * Copyright (c) 2023 Amlogic, Inc. All rights reserved. 4 + * Author: Huqiang Qin <huqiang.qin@amlogic.com> 5 + */ 6 + 7 + #ifndef _DT_BINDINGS_AMLOGIC_T7_GPIO_H 8 + #define _DT_BINDINGS_AMLOGIC_T7_GPIO_H 9 + 10 + #define GPIOB_0 0 11 + #define GPIOB_1 1 12 + #define GPIOB_2 2 13 + #define GPIOB_3 3 14 + #define GPIOB_4 4 15 + #define GPIOB_5 5 16 + #define GPIOB_6 6 17 + #define GPIOB_7 7 18 + #define GPIOB_8 8 19 + #define GPIOB_9 9 20 + #define GPIOB_10 10 21 + #define GPIOB_11 11 22 + #define GPIOB_12 12 23 + 24 + #define GPIOC_0 13 25 + #define GPIOC_1 14 26 + #define GPIOC_2 15 27 + #define GPIOC_3 16 28 + #define GPIOC_4 17 29 + #define GPIOC_5 18 30 + #define GPIOC_6 19 31 + 32 + #define GPIOX_0 20 33 + #define GPIOX_1 21 34 + #define GPIOX_2 22 35 + #define GPIOX_3 23 36 + #define GPIOX_4 24 37 + #define GPIOX_5 25 38 + #define GPIOX_6 26 39 + #define GPIOX_7 27 40 + #define GPIOX_8 28 41 + #define GPIOX_9 29 42 + #define GPIOX_10 30 43 + #define GPIOX_11 31 44 + #define GPIOX_12 32 45 + #define GPIOX_13 33 46 + #define GPIOX_14 34 47 + #define GPIOX_15 35 48 + #define GPIOX_16 36 49 + #define GPIOX_17 37 50 + #define GPIOX_18 38 51 + #define GPIOX_19 39 52 + 53 + #define GPIOW_0 40 54 + #define GPIOW_1 41 55 + #define GPIOW_2 42 56 + #define GPIOW_3 43 57 + #define GPIOW_4 44 58 + #define GPIOW_5 45 59 + #define GPIOW_6 46 60 + #define GPIOW_7 47 61 + #define GPIOW_8 48 62 + #define GPIOW_9 49 63 + #define GPIOW_10 50 64 + #define GPIOW_11 51 65 + #define GPIOW_12 52 66 + #define GPIOW_13 53 67 + #define GPIOW_14 54 68 + #define GPIOW_15 55 69 + #define GPIOW_16 56 70 + 71 + #define GPIOD_0 57 72 + #define GPIOD_1 58 73 + #define GPIOD_2 59 74 + #define GPIOD_3 60 75 + #define GPIOD_4 61 76 + #define GPIOD_5 62 77 + #define GPIOD_6 63 78 + #define GPIOD_7 64 79 + #define GPIOD_8 65 80 + #define GPIOD_9 66 81 + #define GPIOD_10 67 82 + #define GPIOD_11 68 83 + #define GPIOD_12 69 84 + 85 + #define GPIOE_0 70 86 + #define GPIOE_1 71 87 + #define GPIOE_2 72 88 + #define GPIOE_3 73 89 + #define GPIOE_4 74 90 + #define GPIOE_5 75 91 + #define GPIOE_6 76 92 + 93 + #define GPIOZ_0 77 94 + #define GPIOZ_1 78 95 + #define GPIOZ_2 79 96 + #define GPIOZ_3 80 97 + #define GPIOZ_4 81 98 + #define GPIOZ_5 82 99 + #define GPIOZ_6 83 100 + #define GPIOZ_7 84 101 + #define GPIOZ_8 85 102 + #define GPIOZ_9 86 103 + #define GPIOZ_10 87 104 + #define GPIOZ_11 88 105 + #define GPIOZ_12 89 106 + #define GPIOZ_13 90 107 + 108 + #define GPIOT_0 91 109 + #define GPIOT_1 92 110 + #define GPIOT_2 93 111 + #define GPIOT_3 94 112 + #define GPIOT_4 95 113 + #define GPIOT_5 96 114 + #define GPIOT_6 97 115 + #define GPIOT_7 98 116 + #define GPIOT_8 99 117 + #define GPIOT_9 100 118 + #define GPIOT_10 101 119 + #define GPIOT_11 102 120 + #define GPIOT_12 103 121 + #define GPIOT_13 104 122 + #define GPIOT_14 105 123 + #define GPIOT_15 106 124 + #define GPIOT_16 107 125 + #define GPIOT_17 108 126 + #define GPIOT_18 109 127 + #define GPIOT_19 110 128 + #define GPIOT_20 111 129 + #define GPIOT_21 112 130 + #define GPIOT_22 113 131 + #define GPIOT_23 114 132 + 133 + #define GPIOM_0 115 134 + #define GPIOM_1 116 135 + #define GPIOM_2 117 136 + #define GPIOM_3 118 137 + #define GPIOM_4 119 138 + #define GPIOM_5 120 139 + #define GPIOM_6 121 140 + #define GPIOM_7 122 141 + #define GPIOM_8 123 142 + #define GPIOM_9 124 143 + #define GPIOM_10 125 144 + #define GPIOM_11 126 145 + #define GPIOM_12 127 146 + #define GPIOM_13 128 147 + 148 + #define GPIOY_0 129 149 + #define GPIOY_1 130 150 + #define GPIOY_2 131 151 + #define GPIOY_3 132 152 + #define GPIOY_4 133 153 + #define GPIOY_5 134 154 + #define GPIOY_6 135 155 + #define GPIOY_7 136 156 + #define GPIOY_8 137 157 + #define GPIOY_9 138 158 + #define GPIOY_10 139 159 + #define GPIOY_11 140 160 + #define GPIOY_12 141 161 + #define GPIOY_13 142 162 + #define GPIOY_14 143 163 + #define GPIOY_15 144 164 + #define GPIOY_16 145 165 + #define GPIOY_17 146 166 + #define GPIOY_18 147 167 + 168 + #define GPIOH_0 148 169 + #define GPIOH_1 149 170 + #define GPIOH_2 150 171 + #define GPIOH_3 151 172 + #define GPIOH_4 152 173 + #define GPIOH_5 153 174 + #define GPIOH_6 154 175 + #define GPIOH_7 155 176 + 177 + #define GPIO_TEST_N 156 178 + 179 + #endif /* _DT_BINDINGS_AMLOGIC_T7_GPIO_H */