pinctrl: sunxi: h616: add extra gpio banks

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

Some SoCs from the H616 family (such as the T507) have the same die but
more output pins that are used for additional peripherals. The T507 SoC
don't have a built-in multiphy like the AC200 or AC300 connected to the
bank A. With the T507 these pins can be freely used for any other application.
This patch adds the missing muxes on banks A, D and E.

Thanks to Samuel and Andre for the review.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://lore.kernel.org/r/20230916081615.4237-1-iuncuim@gmail.com
Signed-off-by: Mikhail Kalashnikov <iuncuim@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

authored by

iuncuim and committed by

Linus Walleij 2 years ago 44da5bf4 0ec8ae43

+366 -14

1 changed file

expand all

drivers

pinctrl

sunxi

pinctrl-sun50i-h616.c

+366 -14

drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c

··· 15 15 #include "pinctrl-sunxi.h" 16 16 17 17 static const struct sunxi_desc_pin h616_pins[] = { 18 - /* Internal connection to the AC200 part */ 18 + /* Internally connected to the AC200 part in the H616 SoC */ 19 19 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0), 20 - SUNXI_FUNCTION(0x2, "emac1")), /* ERXD1 */ 20 + SUNXI_FUNCTION(0x0, "gpio_in"), 21 + SUNXI_FUNCTION(0x1, "gpio_out"), 22 + SUNXI_FUNCTION(0x2, "emac1"), /* ERXD1 */ 23 + SUNXI_FUNCTION(0x4, "i2c0"), /* SCK */ 24 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */ 21 25 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1), 22 - SUNXI_FUNCTION(0x2, "emac1")), /* ERXD0 */ 26 + SUNXI_FUNCTION(0x0, "gpio_in"), 27 + SUNXI_FUNCTION(0x1, "gpio_out"), 28 + SUNXI_FUNCTION(0x2, "emac1"), /* ERXD0 */ 29 + SUNXI_FUNCTION(0x4, "i2c0"), /* SDA */ 30 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */ 23 31 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2), 24 - SUNXI_FUNCTION(0x2, "emac1")), /* ECRS_DV */ 32 + SUNXI_FUNCTION(0x0, "gpio_in"), 33 + SUNXI_FUNCTION(0x1, "gpio_out"), 34 + SUNXI_FUNCTION(0x2, "emac1"), /* ECRS_DV */ 35 + SUNXI_FUNCTION(0x4, "i2c1"), /* SCK */ 36 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */ 25 37 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3), 26 - SUNXI_FUNCTION(0x2, "emac1")), /* ERXERR */ 38 + SUNXI_FUNCTION(0x0, "gpio_in"), 39 + SUNXI_FUNCTION(0x1, "gpio_out"), 40 + SUNXI_FUNCTION(0x2, "emac1"), /* ERXERR */ 41 + SUNXI_FUNCTION(0x4, "i2c1"), /* SDA */ 42 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */ 27 43 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4), 28 - SUNXI_FUNCTION(0x2, "emac1")), /* ETXD1 */ 44 + SUNXI_FUNCTION(0x0, "gpio_in"), 45 + SUNXI_FUNCTION(0x1, "gpio_out"), 46 + SUNXI_FUNCTION(0x2, "emac1"), /* ETXD1 */ 47 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */ 29 48 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5), 30 - SUNXI_FUNCTION(0x2, "emac1")), /* ETXD0 */ 49 + SUNXI_FUNCTION(0x0, "gpio_in"), 50 + SUNXI_FUNCTION(0x1, "gpio_out"), 51 + SUNXI_FUNCTION(0x2, "emac1"), /* ETXD0 */ 52 + SUNXI_FUNCTION(0x3, "i2s0"), /* DOUT0 */ 53 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */ 31 54 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6), 32 - SUNXI_FUNCTION(0x2, "emac1")), /* ETXCK */ 55 + SUNXI_FUNCTION(0x0, "gpio_in"), 56 + SUNXI_FUNCTION(0x1, "gpio_out"), 57 + SUNXI_FUNCTION(0x2, "emac1"), /* ETXCK */ 58 + SUNXI_FUNCTION(0x3, "i2s0"), /* MCLK */ 59 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */ 33 60 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7), 34 - SUNXI_FUNCTION(0x2, "emac1")), /* ETXEN */ 61 + SUNXI_FUNCTION(0x0, "gpio_in"), 62 + SUNXI_FUNCTION(0x1, "gpio_out"), 63 + SUNXI_FUNCTION(0x2, "emac1"), /* ETXEN */ 64 + SUNXI_FUNCTION(0x3, "i2s0"), /* BCLK */ 65 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */ 35 66 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8), 36 - SUNXI_FUNCTION(0x2, "emac1")), /* EMDC */ 67 + SUNXI_FUNCTION(0x0, "gpio_in"), 68 + SUNXI_FUNCTION(0x1, "gpio_out"), 69 + SUNXI_FUNCTION(0x2, "emac1"), /* EMDC */ 70 + SUNXI_FUNCTION(0x3, "i2s0"), /* LRCK */ 71 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */ 37 72 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9), 38 - SUNXI_FUNCTION(0x2, "emac1")), /* EMDIO */ 73 + SUNXI_FUNCTION(0x0, "gpio_in"), 74 + SUNXI_FUNCTION(0x1, "gpio_out"), 75 + SUNXI_FUNCTION(0x2, "emac1"), /* EMDIO */ 76 + SUNXI_FUNCTION(0x3, "i2s0"), /* DIN0 */ 77 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */ 39 78 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10), 40 - SUNXI_FUNCTION(0x2, "i2c3")), /* SCK */ 79 + SUNXI_FUNCTION(0x0, "gpio_in"), 80 + SUNXI_FUNCTION(0x1, "gpio_out"), 81 + SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */ 82 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */ 41 83 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11), 42 - SUNXI_FUNCTION(0x2, "i2c3")), /* SDA */ 84 + SUNXI_FUNCTION(0x0, "gpio_in"), 85 + SUNXI_FUNCTION(0x1, "gpio_out"), 86 + SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */ 87 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */ 43 88 SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12), 44 - SUNXI_FUNCTION(0x2, "pwm5")), 89 + SUNXI_FUNCTION(0x0, "gpio_in"), 90 + SUNXI_FUNCTION(0x1, "gpio_out"), 91 + SUNXI_FUNCTION(0x2, "pwm5"), 92 + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */ 45 93 /* Hole */ 46 94 SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), 47 95 SUNXI_FUNCTION(0x0, "gpio_in"), ··· 195 147 SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */ 196 148 SUNXI_FUNCTION(0x4, "spi0"), /* HOLD */ 197 149 SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)), /* PC_EINT16 */ 150 + /* Hole */ 151 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), 152 + SUNXI_FUNCTION(0x0, "gpio_in"), 153 + SUNXI_FUNCTION(0x1, "gpio_out"), 154 + SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */ 155 + SUNXI_FUNCTION(0x3, "lvds0"), /* VP0 */ 156 + SUNXI_FUNCTION(0x4, "ts0"), /* CLK */ 157 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PD_EINT0 */ 158 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), 159 + SUNXI_FUNCTION(0x0, "gpio_in"), 160 + SUNXI_FUNCTION(0x1, "gpio_out"), 161 + SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */ 162 + SUNXI_FUNCTION(0x3, "lvds0"), /* VN0 */ 163 + SUNXI_FUNCTION(0x4, "ts0"), /* ERR */ 164 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PD_EINT1 */ 165 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), 166 + SUNXI_FUNCTION(0x0, "gpio_in"), 167 + SUNXI_FUNCTION(0x1, "gpio_out"), 168 + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ 169 + SUNXI_FUNCTION(0x3, "lvds0"), /* VP1 */ 170 + SUNXI_FUNCTION(0x4, "ts0"), /* SYNC */ 171 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PD_EINT2 */ 172 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), 173 + SUNXI_FUNCTION(0x0, "gpio_in"), 174 + SUNXI_FUNCTION(0x1, "gpio_out"), 175 + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ 176 + SUNXI_FUNCTION(0x3, "lvds0"), /* VN1 */ 177 + SUNXI_FUNCTION(0x4, "ts0"), /* DVLD */ 178 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PD_EINT3 */ 179 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), 180 + SUNXI_FUNCTION(0x0, "gpio_in"), 181 + SUNXI_FUNCTION(0x1, "gpio_out"), 182 + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ 183 + SUNXI_FUNCTION(0x3, "lvds0"), /* VP2 */ 184 + SUNXI_FUNCTION(0x4, "ts0"), /* D0 */ 185 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PD_EINT4 */ 186 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), 187 + SUNXI_FUNCTION(0x0, "gpio_in"), 188 + SUNXI_FUNCTION(0x1, "gpio_out"), 189 + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ 190 + SUNXI_FUNCTION(0x3, "lvds0"), /* VN2 */ 191 + SUNXI_FUNCTION(0x4, "ts0"), /* D1 */ 192 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PD_EINT5 */ 193 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), 194 + SUNXI_FUNCTION(0x0, "gpio_in"), 195 + SUNXI_FUNCTION(0x1, "gpio_out"), 196 + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ 197 + SUNXI_FUNCTION(0x3, "lvds0"), /* VPC */ 198 + SUNXI_FUNCTION(0x4, "ts0"), /* D2 */ 199 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PD_EINT6 */ 200 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), 201 + SUNXI_FUNCTION(0x0, "gpio_in"), 202 + SUNXI_FUNCTION(0x1, "gpio_out"), 203 + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ 204 + SUNXI_FUNCTION(0x3, "lvds0"), /* VNC */ 205 + SUNXI_FUNCTION(0x4, "ts0"), /* D3 */ 206 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PD_EINT7 */ 207 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), 208 + SUNXI_FUNCTION(0x0, "gpio_in"), 209 + SUNXI_FUNCTION(0x1, "gpio_out"), 210 + SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */ 211 + SUNXI_FUNCTION(0x3, "lvds0"), /* VP3 */ 212 + SUNXI_FUNCTION(0x4, "ts0"), /* D4 */ 213 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PD_EINT8 */ 214 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), 215 + SUNXI_FUNCTION(0x0, "gpio_in"), 216 + SUNXI_FUNCTION(0x1, "gpio_out"), 217 + SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */ 218 + SUNXI_FUNCTION(0x3, "lvds0"), /* VN3 */ 219 + SUNXI_FUNCTION(0x4, "ts0"), /* D5 */ 220 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PD_EINT9 */ 221 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), 222 + SUNXI_FUNCTION(0x0, "gpio_in"), 223 + SUNXI_FUNCTION(0x1, "gpio_out"), 224 + SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ 225 + SUNXI_FUNCTION(0x3, "lvds1"), /* VP0 */ 226 + SUNXI_FUNCTION(0x4, "ts0"), /* D6 */ 227 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PD_EINT10 */ 228 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), 229 + SUNXI_FUNCTION(0x0, "gpio_in"), 230 + SUNXI_FUNCTION(0x1, "gpio_out"), 231 + SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ 232 + SUNXI_FUNCTION(0x3, "lvds1"), /* VN0 */ 233 + SUNXI_FUNCTION(0x4, "ts0"), /* D7 */ 234 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PD_EINT11 */ 235 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), 236 + SUNXI_FUNCTION(0x0, "gpio_in"), 237 + SUNXI_FUNCTION(0x1, "gpio_out"), 238 + SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ 239 + SUNXI_FUNCTION(0x3, "lvds1"), /* VP1 */ 240 + SUNXI_FUNCTION(0x4, "sim"), /* VPPEN */ 241 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PD_EINT12 */ 242 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), 243 + SUNXI_FUNCTION(0x0, "gpio_in"), 244 + SUNXI_FUNCTION(0x1, "gpio_out"), 245 + SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ 246 + SUNXI_FUNCTION(0x3, "lvds1"), /* VN1 */ 247 + SUNXI_FUNCTION(0x4, "sim"), /* VPPPP */ 248 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PD_EINT13 */ 249 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), 250 + SUNXI_FUNCTION(0x0, "gpio_in"), 251 + SUNXI_FUNCTION(0x1, "gpio_out"), 252 + SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ 253 + SUNXI_FUNCTION(0x3, "lvds1"), /* VP2 */ 254 + SUNXI_FUNCTION(0x4, "sim"), /* PWREN */ 255 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PD_EINT14 */ 256 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), 257 + SUNXI_FUNCTION(0x0, "gpio_in"), 258 + SUNXI_FUNCTION(0x1, "gpio_out"), 259 + SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ 260 + SUNXI_FUNCTION(0x3, "lvds1"), /* VN2 */ 261 + SUNXI_FUNCTION(0x4, "sim"), /* CLK */ 262 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), /* PD_EINT15 */ 263 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), 264 + SUNXI_FUNCTION(0x0, "gpio_in"), 265 + SUNXI_FUNCTION(0x1, "gpio_out"), 266 + SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */ 267 + SUNXI_FUNCTION(0x3, "lvds1"), /* VPC */ 268 + SUNXI_FUNCTION(0x4, "sim"), /* DATA */ 269 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)), /* PD_EINT16 */ 270 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), 271 + SUNXI_FUNCTION(0x0, "gpio_in"), 272 + SUNXI_FUNCTION(0x1, "gpio_out"), 273 + SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */ 274 + SUNXI_FUNCTION(0x3, "lvds1"), /* VNC */ 275 + SUNXI_FUNCTION(0x4, "sim"), /* RST */ 276 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 17)), /* PD_EINT17 */ 277 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), 278 + SUNXI_FUNCTION(0x0, "gpio_in"), 279 + SUNXI_FUNCTION(0x1, "gpio_out"), 280 + SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ 281 + SUNXI_FUNCTION(0x3, "lvds1"), /* VP3 */ 282 + SUNXI_FUNCTION(0x4, "sim"), /* DET */ 283 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 18)), /* PD_EINT18 */ 284 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), 285 + SUNXI_FUNCTION(0x0, "gpio_in"), 286 + SUNXI_FUNCTION(0x1, "gpio_out"), 287 + SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ 288 + SUNXI_FUNCTION(0x3, "lvds1"), /* VN3 */ 289 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 19)), /* PD_EINT19 */ 290 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), 291 + SUNXI_FUNCTION(0x0, "gpio_in"), 292 + SUNXI_FUNCTION(0x1, "gpio_out"), 293 + SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ 294 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 20)), /* PD_EINT20 */ 295 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), 296 + SUNXI_FUNCTION(0x0, "gpio_in"), 297 + SUNXI_FUNCTION(0x1, "gpio_out"), 298 + SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ 299 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 21)), /* PD_EINT21 */ 300 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), 301 + SUNXI_FUNCTION(0x0, "gpio_in"), 302 + SUNXI_FUNCTION(0x1, "gpio_out"), 303 + SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ 304 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 22)), /* PD_EINT22 */ 305 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), 306 + SUNXI_FUNCTION(0x0, "gpio_in"), 307 + SUNXI_FUNCTION(0x1, "gpio_out"), 308 + SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ 309 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 23)), /* PD_EINT23 */ 310 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24), 311 + SUNXI_FUNCTION(0x0, "gpio_in"), 312 + SUNXI_FUNCTION(0x1, "gpio_out"), 313 + SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ 314 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 24)), /* PD_EINT24 */ 315 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25), 316 + SUNXI_FUNCTION(0x0, "gpio_in"), 317 + SUNXI_FUNCTION(0x1, "gpio_out"), 318 + SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ 319 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 25)), /* PD_EINT25 */ 320 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26), 321 + SUNXI_FUNCTION(0x0, "gpio_in"), 322 + SUNXI_FUNCTION(0x1, "gpio_out"), 323 + SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ 324 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 26)), /* PD_EINT26 */ 325 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27), 326 + SUNXI_FUNCTION(0x0, "gpio_in"), 327 + SUNXI_FUNCTION(0x1, "gpio_out"), 328 + SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ 329 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 27)), /* PD_EINT27 */ 330 + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 28), 331 + SUNXI_FUNCTION(0x0, "gpio_in"), 332 + SUNXI_FUNCTION(0x1, "gpio_out"), 333 + SUNXI_FUNCTION(0x2, "pwm0"), 334 + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 28)), /* PD_EINT28 */ 335 + /* Hole */ 336 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), 337 + SUNXI_FUNCTION(0x0, "gpio_in"), 338 + SUNXI_FUNCTION(0x1, "gpio_out"), 339 + SUNXI_FUNCTION(0x2, "csi"), /* PCLK */ 340 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PE_EINT0 */ 341 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), 342 + SUNXI_FUNCTION(0x0, "gpio_in"), 343 + SUNXI_FUNCTION(0x1, "gpio_out"), 344 + SUNXI_FUNCTION(0x2, "csi"), /* MCLK */ 345 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PE_EINT1 */ 346 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), 347 + SUNXI_FUNCTION(0x0, "gpio_in"), 348 + SUNXI_FUNCTION(0x1, "gpio_out"), 349 + SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */ 350 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PE_EINT2 */ 351 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), 352 + SUNXI_FUNCTION(0x0, "gpio_in"), 353 + SUNXI_FUNCTION(0x1, "gpio_out"), 354 + SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */ 355 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PE_EINT3 */ 356 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), 357 + SUNXI_FUNCTION(0x0, "gpio_in"), 358 + SUNXI_FUNCTION(0x1, "gpio_out"), 359 + SUNXI_FUNCTION(0x2, "csi"), /* D0 */ 360 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PE_EINT4 */ 361 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), 362 + SUNXI_FUNCTION(0x0, "gpio_in"), 363 + SUNXI_FUNCTION(0x1, "gpio_out"), 364 + SUNXI_FUNCTION(0x2, "csi"), /* D1 */ 365 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PE_EINT5 */ 366 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), 367 + SUNXI_FUNCTION(0x0, "gpio_in"), 368 + SUNXI_FUNCTION(0x1, "gpio_out"), 369 + SUNXI_FUNCTION(0x2, "csi"), /* D2 */ 370 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PE_EINT6 */ 371 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), 372 + SUNXI_FUNCTION(0x0, "gpio_in"), 373 + SUNXI_FUNCTION(0x1, "gpio_out"), 374 + SUNXI_FUNCTION(0x2, "csi"), /* D3 */ 375 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PE_EINT7 */ 376 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), 377 + SUNXI_FUNCTION(0x0, "gpio_in"), 378 + SUNXI_FUNCTION(0x1, "gpio_out"), 379 + SUNXI_FUNCTION(0x2, "csi"), /* D4 */ 380 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PE_EINT8 */ 381 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), 382 + SUNXI_FUNCTION(0x0, "gpio_in"), 383 + SUNXI_FUNCTION(0x1, "gpio_out"), 384 + SUNXI_FUNCTION(0x2, "csi"), /* D5 */ 385 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PE_EINT9 */ 386 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10), 387 + SUNXI_FUNCTION(0x0, "gpio_in"), 388 + SUNXI_FUNCTION(0x1, "gpio_out"), 389 + SUNXI_FUNCTION(0x2, "csi"), /* D6 */ 390 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PE_EINT10 */ 391 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11), 392 + SUNXI_FUNCTION(0x0, "gpio_in"), 393 + SUNXI_FUNCTION(0x1, "gpio_out"), 394 + SUNXI_FUNCTION(0x2, "csi"), /* D7 */ 395 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), /* PE_EINT11 */ 396 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12), 397 + SUNXI_FUNCTION(0x0, "gpio_in"), 398 + SUNXI_FUNCTION(0x1, "gpio_out"), 399 + SUNXI_FUNCTION(0x2, "csi"), /* D8 */ 400 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)), /* PE_EINT12 */ 401 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13), 402 + SUNXI_FUNCTION(0x0, "gpio_in"), 403 + SUNXI_FUNCTION(0x1, "gpio_out"), 404 + SUNXI_FUNCTION(0x2, "csi"), /* D9 */ 405 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)), /* PE_EINT13 */ 406 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14), 407 + SUNXI_FUNCTION(0x0, "gpio_in"), 408 + SUNXI_FUNCTION(0x1, "gpio_out"), 409 + SUNXI_FUNCTION(0x2, "csi"), /* D10 */ 410 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)), /* PE_EINT14 */ 411 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15), 412 + SUNXI_FUNCTION(0x0, "gpio_in"), 413 + SUNXI_FUNCTION(0x1, "gpio_out"), 414 + SUNXI_FUNCTION(0x2, "csi"), /* D11 */ 415 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)), /* PE_EINT15 */ 416 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16), 417 + SUNXI_FUNCTION(0x0, "gpio_in"), 418 + SUNXI_FUNCTION(0x1, "gpio_out"), 419 + SUNXI_FUNCTION(0x2, "csi"), /* D12 */ 420 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 16)), /* PE_EINT16 */ 421 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17), 422 + SUNXI_FUNCTION(0x0, "gpio_in"), 423 + SUNXI_FUNCTION(0x1, "gpio_out"), 424 + SUNXI_FUNCTION(0x2, "csi"), /* D13 */ 425 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 17)), /* PE_EINT17 */ 426 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 18), 427 + SUNXI_FUNCTION(0x0, "gpio_in"), 428 + SUNXI_FUNCTION(0x1, "gpio_out"), 429 + SUNXI_FUNCTION(0x2, "csi"), /* D14 */ 430 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 18)), /* PE_EINT18 */ 431 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 19), 432 + SUNXI_FUNCTION(0x0, "gpio_in"), 433 + SUNXI_FUNCTION(0x1, "gpio_out"), 434 + SUNXI_FUNCTION(0x2, "csi"), /* D15 */ 435 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 19)), /* PE_EINT19 */ 436 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 20), 437 + SUNXI_FUNCTION(0x0, "gpio_in"), 438 + SUNXI_FUNCTION(0x1, "gpio_out"), 439 + SUNXI_FUNCTION(0x2, "csi"), /* SCK */ 440 + SUNXI_FUNCTION(0x5, "i2c2"), /* SCK */ 441 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 20)), /* PE_EINT20 */ 442 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 21), 443 + SUNXI_FUNCTION(0x0, "gpio_in"), 444 + SUNXI_FUNCTION(0x1, "gpio_out"), 445 + SUNXI_FUNCTION(0x2, "csi"), /* SDA */ 446 + SUNXI_FUNCTION(0x5, "i2c2"), /* SDA */ 447 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 21)), /* PE_EINT21 */ 448 + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 22), 449 + SUNXI_FUNCTION(0x0, "gpio_in"), 450 + SUNXI_FUNCTION(0x1, "gpio_out"), 451 + SUNXI_FUNCTION(0x2, "csi"), /* FSIN0 */ 452 + SUNXI_FUNCTION(0x4, "tcon0"), /* TRIG0 */ 453 + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 22)), /* PE_EINT22 */ 198 454 /* Hole */ 199 455 SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), 200 456 SUNXI_FUNCTION(0x0, "gpio_in"),