tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: Add umc v8_14 ras functions
Add umc v8_14 ras functions.
Signed-off-by: Candice Li <candice.li@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Candice Li
and committed by
Alex Deucher
33f1aa21
334a8158
+229
-2
+1
-1
drivers/gpu/drm/amd/amdgpu/Makefile
+1
-1
drivers/gpu/drm/amd/amdgpu/Makefile
+17
-1
drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
+17
-1
drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
···
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#include "gfxhub_v12_0.h"
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#include "mmhub_v4_1_0.h"
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#include "athub_v4_1_0.h"
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-
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#include "umc_v8_14.h"
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static int gmc_v12_0_ecc_interrupt_state(struct amdgpu_device *adev,
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struct amdgpu_irq_src *src,
···
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static void gmc_v12_0_set_umc_funcs(struct amdgpu_device *adev)
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{
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switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) {
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case IP_VERSION(8, 14, 0):
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adev->umc.channel_inst_num = UMC_V8_14_CHANNEL_INSTANCE_NUM;
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adev->umc.umc_inst_num = UMC_V8_14_UMC_INSTANCE_NUM(adev);
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adev->umc.node_inst_num = 0;
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adev->umc.max_ras_err_cnt_per_query = UMC_V8_14_TOTAL_CHANNEL_NUM(adev);
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adev->umc.channel_offs = UMC_V8_14_PER_CHANNEL_OFFSET;
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adev->umc.ras = &umc_v8_14_ras;
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break;
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default:
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break;
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}
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}
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···
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adev->vm_manager.first_kfd_vmid = 8;
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amdgpu_vm_manager_init(adev);
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r = amdgpu_gmc_ras_sw_init(adev);
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if (r)
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return r;
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return 0;
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}
+160
drivers/gpu/drm/amd/amdgpu/umc_v8_14.c
+160
drivers/gpu/drm/amd/amdgpu/umc_v8_14.c
···
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/*
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* Copyright 2024 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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+
* to deal in the Software without restriction, including without limitation
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+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "umc_v8_14.h"
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#include "amdgpu_ras.h"
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#include "amdgpu_umc.h"
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#include "amdgpu.h"
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#include "umc/umc_8_14_0_offset.h"
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#include "umc/umc_8_14_0_sh_mask.h"
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static inline uint32_t get_umc_v8_14_reg_offset(struct amdgpu_device *adev,
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uint32_t umc_inst,
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uint32_t ch_inst)
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{
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return adev->umc.channel_offs * ch_inst + UMC_V8_14_INST_DIST * umc_inst;
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}
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static int umc_v8_14_clear_error_count_per_channel(struct amdgpu_device *adev,
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uint32_t node_inst, uint32_t umc_inst,
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uint32_t ch_inst, void *data)
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{
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uint32_t ecc_err_cnt_addr;
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uint32_t umc_reg_offset =
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get_umc_v8_14_reg_offset(adev, umc_inst, ch_inst);
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ecc_err_cnt_addr =
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SOC15_REG_OFFSET(UMC, 0, regUMCCH0_GeccErrCnt);
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/* clear error count */
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WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4,
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UMC_V8_14_CE_CNT_INIT);
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return 0;
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}
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static void umc_v8_14_clear_error_count(struct amdgpu_device *adev)
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{
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amdgpu_umc_loop_channels(adev,
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umc_v8_14_clear_error_count_per_channel, NULL);
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}
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static void umc_v8_14_query_correctable_error_count(struct amdgpu_device *adev,
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uint32_t umc_reg_offset,
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unsigned long *error_count)
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{
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uint32_t ecc_err_cnt, ecc_err_cnt_addr;
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/* UMC 8_14 registers */
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ecc_err_cnt_addr =
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SOC15_REG_OFFSET(UMC, 0, regUMCCH0_GeccErrCnt);
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ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4);
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*error_count +=
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(REG_GET_FIELD(ecc_err_cnt, UMCCH0_GeccErrCnt, GeccErrCnt) -
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UMC_V8_14_CE_CNT_INIT);
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}
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static void umc_v8_14_query_uncorrectable_error_count(struct amdgpu_device *adev,
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uint32_t umc_reg_offset,
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unsigned long *error_count)
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{
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uint32_t ecc_err_cnt, ecc_err_cnt_addr;
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/* UMC 8_14 registers */
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ecc_err_cnt_addr =
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SOC15_REG_OFFSET(UMC, 0, regUMCCH0_GeccErrCnt);
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ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4);
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*error_count +=
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(REG_GET_FIELD(ecc_err_cnt, UMCCH0_GeccErrCnt, GeccUnCorrErrCnt) -
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UMC_V8_14_CE_CNT_INIT);
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}
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static int umc_v8_14_query_error_count_per_channel(struct amdgpu_device *adev,
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uint32_t node_inst, uint32_t umc_inst,
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uint32_t ch_inst, void *data)
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{
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struct ras_err_data *err_data = (struct ras_err_data *)data;
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uint32_t umc_reg_offset =
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get_umc_v8_14_reg_offset(adev, umc_inst, ch_inst);
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umc_v8_14_query_correctable_error_count(adev,
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umc_reg_offset,
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&(err_data->ce_count));
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umc_v8_14_query_uncorrectable_error_count(adev,
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umc_reg_offset,
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&(err_data->ue_count));
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return 0;
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}
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static void umc_v8_14_query_ras_error_count(struct amdgpu_device *adev,
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void *ras_error_status)
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{
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amdgpu_umc_loop_channels(adev,
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umc_v8_14_query_error_count_per_channel, ras_error_status);
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umc_v8_14_clear_error_count(adev);
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}
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static int umc_v8_14_err_cnt_init_per_channel(struct amdgpu_device *adev,
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uint32_t node_inst, uint32_t umc_inst,
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uint32_t ch_inst, void *data)
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{
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uint32_t ecc_err_cnt_sel, ecc_err_cnt_sel_addr;
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uint32_t ecc_err_cnt_addr;
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uint32_t umc_reg_offset =
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get_umc_v8_14_reg_offset(adev, umc_inst, ch_inst);
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ecc_err_cnt_sel_addr =
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SOC15_REG_OFFSET(UMC, 0, regUMCCH0_GeccErrCntSel);
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ecc_err_cnt_addr =
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SOC15_REG_OFFSET(UMC, 0, regUMCCH0_GeccErrCnt);
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ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4);
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/* set ce error interrupt type to APIC based interrupt */
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ecc_err_cnt_sel = REG_SET_FIELD(ecc_err_cnt_sel, UMCCH0_GeccErrCntSel,
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GeccErrInt, 0x1);
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WREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4, ecc_err_cnt_sel);
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/* set error count to initial value */
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WREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4, UMC_V8_14_CE_CNT_INIT);
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return 0;
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}
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static void umc_v8_14_err_cnt_init(struct amdgpu_device *adev)
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{
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amdgpu_umc_loop_channels(adev,
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umc_v8_14_err_cnt_init_per_channel, NULL);
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}
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const struct amdgpu_ras_block_hw_ops umc_v8_14_ras_hw_ops = {
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.query_ras_error_count = umc_v8_14_query_ras_error_count,
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};
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struct amdgpu_umc_ras umc_v8_14_ras = {
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.ras_block = {
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.hw_ops = &umc_v8_14_ras_hw_ops,
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},
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.err_cnt_init = umc_v8_14_err_cnt_init,
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};
+51
drivers/gpu/drm/amd/amdgpu/umc_v8_14.h
+51
drivers/gpu/drm/amd/amdgpu/umc_v8_14.h
···
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/*
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* Copyright 2024 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
5
+
* copy of this software and associated documentation files (the "Software"),
6
+
* to deal in the Software without restriction, including without limitation
7
+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8
+
* and/or sell copies of the Software, and to permit persons to whom the
9
+
* Software is furnished to do so, subject to the following conditions:
10
+
*
11
+
* The above copyright notice and this permission notice shall be included in
12
+
* all copies or substantial portions of the Software.
13
+
*
14
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15
+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16
+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17
+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18
+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19
+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20
+
* OTHER DEALINGS IN THE SOFTWARE.
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+
*
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*/
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#ifndef __UMC_V8_14_H__
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#define __UMC_V8_14_H__
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#include "soc15_common.h"
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#include "amdgpu.h"
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/* number of umc channel instance with memory map register access */
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#define UMC_V8_14_CHANNEL_INSTANCE_NUM 2
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/* number of umc instance with memory map register access */
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#define UMC_V8_14_UMC_INSTANCE_NUM(adev) ((adev)->umc.node_inst_num)
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/* Total channel instances for all available umc nodes */
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#define UMC_V8_14_TOTAL_CHANNEL_NUM(adev) \
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(UMC_V8_14_CHANNEL_INSTANCE_NUM * (adev)->gmc.num_umc)
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/* UMC register per channel offset */
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#define UMC_V8_14_PER_CHANNEL_OFFSET 0x400
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#define UMC_V8_14_INST_DIST 0x40000
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/* EccErrCnt max value */
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#define UMC_V8_14_CE_CNT_MAX 0xffff
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/* umc ce interrupt threshold */
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#define UMC_V8_14_CE_INT_THRESHOLD 0xffff
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/* umc ce count initial value */
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#define UMC_V8_14_CE_CNT_INIT (UMC_V8_14_CE_CNT_MAX - UMC_V8_14_CE_INT_THRESHOLD)
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extern struct amdgpu_umc_ras umc_v8_14_ras;
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#endif