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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
gpu: host1x: Disassemble more instructions
The disassembler for debug dumps was missing some newer host1x opcodes.
Add disassembly support for these.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
authored by
Mikko Perttunen
and committed by
Thierry Reding
2a79c034
eb2ee1a2
+59
-7
+56
-5
drivers/gpu/host1x/hw/debug_hw.c
+56
-5
drivers/gpu/host1x/hw/debug_hw.c
···
30
30
HOST1X_OPCODE_IMM = 0x04,
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31
HOST1X_OPCODE_RESTART = 0x05,
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HOST1X_OPCODE_GATHER = 0x06,
33
+
HOST1X_OPCODE_SETSTRMID = 0x07,
34
+
HOST1X_OPCODE_SETAPPID = 0x08,
35
+
HOST1X_OPCODE_SETPYLD = 0x09,
36
+
HOST1X_OPCODE_INCR_W = 0x0a,
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+
HOST1X_OPCODE_NONINCR_W = 0x0b,
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+
HOST1X_OPCODE_GATHER_W = 0x0c,
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+
HOST1X_OPCODE_RESTART_W = 0x0d,
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40
HOST1X_OPCODE_EXTEND = 0x0e,
34
41
};
35
42
···
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38
HOST1X_OPCODE_EXTEND_RELEASE_MLOCK = 0x01,
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39
};
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40
48
-
static unsigned int show_channel_command(struct output *o, u32 val)
49
-
{
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-
unsigned int mask, subop, num;
41
+
#define INVALID_PAYLOAD 0xffffffff
51
42
52
-
switch (val >> 28) {
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+
static unsigned int show_channel_command(struct output *o, u32 val,
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+
u32 *payload)
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+
{
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+
unsigned int mask, subop, num, opcode;
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+
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+
opcode = val >> 28;
49
+
50
+
switch (opcode) {
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case HOST1X_OPCODE_SETCLASS:
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52
mask = val & 0x3f;
55
53
if (mask) {
···
109
97
val >> 14 & 0x1, val & 0x3fff);
110
98
return 1;
111
99
100
+
#if HOST1X_HW >= 6
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+
case HOST1X_OPCODE_SETSTRMID:
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+
host1x_debug_cont(o, "SETSTRMID(offset=%06x)\n",
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+
val & 0x3fffff);
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+
return 0;
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+
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+
case HOST1X_OPCODE_SETAPPID:
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+
host1x_debug_cont(o, "SETAPPID(appid=%02x)\n", val & 0xff);
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+
return 0;
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+
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+
case HOST1X_OPCODE_SETPYLD:
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+
*payload = val & 0xffff;
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+
host1x_debug_cont(o, "SETPYLD(data=%04x)\n", *payload);
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+
return 0;
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+
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+
case HOST1X_OPCODE_INCR_W:
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+
case HOST1X_OPCODE_NONINCR_W:
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+
host1x_debug_cont(o, "%s(offset=%06x, ",
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+
opcode == HOST1X_OPCODE_INCR_W ?
119
+
"INCR_W" : "NONINCR_W",
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+
val & 0x3fffff);
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+
if (*payload == 0) {
122
+
host1x_debug_cont(o, "[])\n");
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+
return 0;
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+
} else if (*payload == INVALID_PAYLOAD) {
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+
host1x_debug_cont(o, "unknown)\n");
126
+
return 0;
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+
} else {
128
+
host1x_debug_cont(o, "[");
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+
return *payload;
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+
}
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+
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+
case HOST1X_OPCODE_GATHER_W:
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+
host1x_debug_cont(o, "GATHER_W(count=%04x, addr=[",
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+
val & 0x3fff);
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+
return 2;
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+
#endif
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+
112
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case HOST1X_OPCODE_EXTEND:
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subop = val >> 24 & 0xf;
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if (subop == HOST1X_OPCODE_EXTEND_ACQUIRE_MLOCK)
···
172
122
/* Map dmaget cursor to corresponding mem handle */
173
123
u32 offset = phys_addr - pin_addr;
174
124
unsigned int data_count = 0, i;
125
+
u32 payload = INVALID_PAYLOAD;
175
126
176
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/*
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128
* Sometimes we're given different hardware address to the same
···
190
139
191
140
if (!data_count) {
192
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host1x_debug_output(o, "%08x: %08x: ", addr, val);
193
-
data_count = show_channel_command(o, val);
142
+
data_count = show_channel_command(o, val, &payload);
194
143
} else {
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host1x_debug_cont(o, "%08x%s", val,
196
145
data_count > 1 ? ", " : "])\n");
+1
-1
drivers/gpu/host1x/hw/debug_hw_1x01.c
+1
-1
drivers/gpu/host1x/hw/debug_hw_1x01.c
+2
-1
drivers/gpu/host1x/hw/debug_hw_1x06.c
+2
-1
drivers/gpu/host1x/hw/debug_hw_1x06.c
···
63
63
struct output *o)
64
64
{
65
65
u32 val, rd_ptr, wr_ptr, start, end;
66
+
u32 payload = INVALID_PAYLOAD;
66
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unsigned int data_count = 0;
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68
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69
host1x_debug_output(o, "%u: fifo:\n", ch->id);
···
108
107
if (!data_count) {
109
108
host1x_debug_output(o, "%03x 0x%08x: ",
110
109
rd_ptr - start, val);
111
-
data_count = show_channel_command(o, val);
110
+
data_count = show_channel_command(o, val, &payload);
112
111
} else {
113
112
host1x_debug_cont(o, "%08x%s", val,
114
113
data_count > 1 ? ", " : "])\n");