tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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gpu: host1x: Improve debug disassembly formatting

The host1x driver prints out "disassembly" dumps of the command FIFO
and gather contents on submission timeouts. However, the output has
been quite difficult to read with unnecessary newlines and occasional
missing parentheses.

Fix these problems by using pr_cont to remove unnecessary newlines
and by fixing other small issues.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

authored by

Mikko Perttunen and committed by
Thierry Reding eb2ee1a2 2316f29f

+61 -30
+13 -1
drivers/gpu/host1x/debug.c
··· 40 40 len = vsnprintf(o->buf, sizeof(o->buf), fmt, args); 41 41 va_end(args); 42 42 43 - o->fn(o->ctx, o->buf, len); 43 + o->fn(o->ctx, o->buf, len, false); 44 + } 45 + 46 + void host1x_debug_cont(struct output *o, const char *fmt, ...) 47 + { 48 + va_list args; 49 + int len; 50 + 51 + va_start(args, fmt); 52 + len = vsnprintf(o->buf, sizeof(o->buf), fmt, args); 53 + va_end(args); 54 + 55 + o->fn(o->ctx, o->buf, len, true); 44 56 } 45 57 46 58 static int show_channel(struct host1x_channel *ch, void *data, bool show_fifo)
+10 -4
drivers/gpu/host1x/debug.h
··· 24 24 struct host1x; 25 25 26 26 struct output { 27 - void (*fn)(void *ctx, const char *str, size_t len); 27 + void (*fn)(void *ctx, const char *str, size_t len, bool cont); 28 28 void *ctx; 29 29 char buf[256]; 30 30 }; 31 31 32 - static inline void write_to_seqfile(void *ctx, const char *str, size_t len) 32 + static inline void write_to_seqfile(void *ctx, const char *str, size_t len, 33 + bool cont) 33 34 { 34 35 seq_write((struct seq_file *)ctx, str, len); 35 36 } 36 37 37 - static inline void write_to_printk(void *ctx, const char *str, size_t len) 38 + static inline void write_to_printk(void *ctx, const char *str, size_t len, 39 + bool cont) 38 40 { 39 - pr_info("%s", str); 41 + if (cont) 42 + pr_cont("%s", str); 43 + else 44 + pr_info("%s", str); 40 45 } 41 46 42 47 void __printf(2, 3) host1x_debug_output(struct output *o, const char *fmt, ...); 48 + void __printf(2, 3) host1x_debug_cont(struct output *o, const char *fmt, ...); 43 49 44 50 extern unsigned int host1x_debug_trace_cmdbuf; 45 51
+29 -17
drivers/gpu/host1x/hw/debug_hw.c
··· 40 40 41 41 static unsigned int show_channel_command(struct output *o, u32 val) 42 42 { 43 - unsigned int mask, subop; 43 + unsigned int mask, subop, num; 44 44 45 45 switch (val >> 28) { 46 46 case HOST1X_OPCODE_SETCLASS: 47 47 mask = val & 0x3f; 48 48 if (mask) { 49 - host1x_debug_output(o, "SETCL(class=%03x, offset=%03x, mask=%02x, [", 49 + host1x_debug_cont(o, "SETCL(class=%03x, offset=%03x, mask=%02x, [", 50 50 val >> 6 & 0x3ff, 51 51 val >> 16 & 0xfff, mask); 52 52 return hweight8(mask); 53 53 } 54 54 55 - host1x_debug_output(o, "SETCL(class=%03x)\n", val >> 6 & 0x3ff); 55 + host1x_debug_cont(o, "SETCL(class=%03x)\n", val >> 6 & 0x3ff); 56 56 return 0; 57 57 58 58 case HOST1X_OPCODE_INCR: 59 - host1x_debug_output(o, "INCR(offset=%03x, [", 59 + num = val & 0xffff; 60 + host1x_debug_cont(o, "INCR(offset=%03x, [", 60 61 val >> 16 & 0xfff); 61 - return val & 0xffff; 62 + if (!num) 63 + host1x_debug_cont(o, "])\n"); 64 + 65 + return num; 62 66 63 67 case HOST1X_OPCODE_NONINCR: 64 - host1x_debug_output(o, "NONINCR(offset=%03x, [", 68 + num = val & 0xffff; 69 + host1x_debug_cont(o, "NONINCR(offset=%03x, [", 65 70 val >> 16 & 0xfff); 66 - return val & 0xffff; 71 + if (!num) 72 + host1x_debug_cont(o, "])\n"); 73 + 74 + return num; 67 75 68 76 case HOST1X_OPCODE_MASK: 69 77 mask = val & 0xffff; 70 - host1x_debug_output(o, "MASK(offset=%03x, mask=%03x, [", 78 + host1x_debug_cont(o, "MASK(offset=%03x, mask=%03x, [", 71 79 val >> 16 & 0xfff, mask); 80 + if (!mask) 81 + host1x_debug_cont(o, "])\n"); 82 + 72 83 return hweight16(mask); 73 84 74 85 case HOST1X_OPCODE_IMM: 75 - host1x_debug_output(o, "IMM(offset=%03x, data=%03x)\n", 86 + host1x_debug_cont(o, "IMM(offset=%03x, data=%03x)\n", 76 87 val >> 16 & 0xfff, val & 0xffff); 77 88 return 0; 78 89 79 90 case HOST1X_OPCODE_RESTART: 80 - host1x_debug_output(o, "RESTART(offset=%08x)\n", val << 4); 91 + host1x_debug_cont(o, "RESTART(offset=%08x)\n", val << 4); 81 92 return 0; 82 93 83 94 case HOST1X_OPCODE_GATHER: 84 - host1x_debug_output(o, "GATHER(offset=%03x, insert=%d, type=%d, count=%04x, addr=[", 95 + host1x_debug_cont(o, "GATHER(offset=%03x, insert=%d, type=%d, count=%04x, addr=[", 85 96 val >> 16 & 0xfff, val >> 15 & 0x1, 86 97 val >> 14 & 0x1, val & 0x3fff); 87 98 return 1; ··· 100 89 case HOST1X_OPCODE_EXTEND: 101 90 subop = val >> 24 & 0xf; 102 91 if (subop == HOST1X_OPCODE_EXTEND_ACQUIRE_MLOCK) 103 - host1x_debug_output(o, "ACQUIRE_MLOCK(index=%d)\n", 92 + host1x_debug_cont(o, "ACQUIRE_MLOCK(index=%d)\n", 104 93 val & 0xff); 105 94 else if (subop == HOST1X_OPCODE_EXTEND_RELEASE_MLOCK) 106 - host1x_debug_output(o, "RELEASE_MLOCK(index=%d)\n", 95 + host1x_debug_cont(o, "RELEASE_MLOCK(index=%d)\n", 107 96 val & 0xff); 108 97 else 109 - host1x_debug_output(o, "EXTEND_UNKNOWN(%08x)\n", val); 98 + host1x_debug_cont(o, "EXTEND_UNKNOWN(%08x)\n", val); 110 99 return 0; 111 100 112 101 default: 102 + host1x_debug_cont(o, "UNKNOWN\n"); 113 103 return 0; 114 104 } 115 105 } ··· 138 126 u32 val = *(map_addr + offset / 4 + i); 139 127 140 128 if (!data_count) { 141 - host1x_debug_output(o, "%08x: %08x:", addr, val); 129 + host1x_debug_output(o, "%08x: %08x: ", addr, val); 142 130 data_count = show_channel_command(o, val); 143 131 } else { 144 - host1x_debug_output(o, "%08x%s", val, 145 - data_count > 0 ? ", " : "])\n"); 132 + host1x_debug_cont(o, "%08x%s", val, 133 + data_count > 1 ? ", " : "])\n"); 146 134 data_count--; 147 135 } 148 136 }
+4 -4
drivers/gpu/host1x/hw/debug_hw_1x01.c
··· 111 111 val = host1x_sync_readl(host, HOST1X_SYNC_CFPEEK_READ); 112 112 113 113 if (!data_count) { 114 - host1x_debug_output(o, "%08x:", val); 114 + host1x_debug_output(o, "%08x: ", val); 115 115 data_count = show_channel_command(o, val); 116 116 } else { 117 - host1x_debug_output(o, "%08x%s", val, 118 - data_count > 0 ? ", " : "])\n"); 117 + host1x_debug_cont(o, "%08x%s", val, 118 + data_count > 1 ? ", " : "])\n"); 119 119 data_count--; 120 120 } 121 121 ··· 126 126 } while (rd_ptr != wr_ptr); 127 127 128 128 if (data_count) 129 - host1x_debug_output(o, ", ...])\n"); 129 + host1x_debug_cont(o, ", ...])\n"); 130 130 host1x_debug_output(o, "\n"); 131 131 132 132 host1x_sync_writel(host, 0x0, HOST1X_SYNC_CFPEEK_CTRL);
+5 -4
drivers/gpu/host1x/hw/debug_hw_1x06.c
··· 105 105 HOST1X_HV_CMDFIFO_PEEK_READ); 106 106 107 107 if (!data_count) { 108 - host1x_debug_output(o, "%08x:", val); 108 + host1x_debug_output(o, "%03x 0x%08x: ", 109 + rd_ptr - start, val); 109 110 data_count = show_channel_command(o, val); 110 111 } else { 111 - host1x_debug_output(o, "%08x%s", val, 112 - data_count > 0 ? ", " : "])\n"); 112 + host1x_debug_cont(o, "%08x%s", val, 113 + data_count > 1 ? ", " : "])\n"); 113 114 data_count--; 114 115 } 115 116 ··· 121 120 } while (rd_ptr != wr_ptr); 122 121 123 122 if (data_count) 124 - host1x_debug_output(o, ", ...])\n"); 123 + host1x_debug_cont(o, ", ...])\n"); 125 124 host1x_debug_output(o, "\n"); 126 125 127 126 host1x_hypervisor_writel(host, 0x0, HOST1X_HV_CMDFIFO_PEEK_CTRL);