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m68knommu: merge bit definitions for version 3 ColdFire cache controller
All version 3 based ColdFire CPU cores have a similar cache controller.
Merge all the exitsing definitions into a single file, and make them
similar in style and naming to the existing version 2 and version 4
cache controller definitions.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
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-27
arch/m68k/include/asm/m5307sim.h
+2
-27
arch/m68k/include/asm/m5307sim.h
···
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#define CPU_NAME "COLDFIRE(m5307)"
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#define CPU_INSTR_PER_JIFFY 3
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#include <asm/m53xxacr.h>
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/*
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* Define the 5307 SIM register set addresses.
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*/
···
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*/
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#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
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#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
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-
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/*
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* Define the Cache register flags.
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*/
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#define CACR_EC (1<<31)
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#define CACR_ESB (1<<29)
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#define CACR_DPI (1<<28)
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#define CACR_HLCK (1<<27)
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#define CACR_CINVA (1<<24)
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#define CACR_DNFB (1<<10)
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#define CACR_DCM_WTHRU (0<<8)
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#define CACR_DCM_WBACK (1<<8)
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#define CACR_DCM_OFF_PRE (2<<8)
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#define CACR_DCM_OFF_IMP (3<<8)
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#define CACR_DW (1<<5)
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#define ACR_BASE_POS 24
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#define ACR_MASK_POS 16
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#define ACR_ENABLE (1<<15)
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#define ACR_USER (0<<13)
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#define ACR_SUPER (1<<13)
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#define ACR_ANY (2<<13)
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#define ACR_CM_WTHRU (0<<5)
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#define ACR_CM_WBACK (1<<5)
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#define ACR_CM_OFF_PRE (2<<5)
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#define ACR_CM_OFF_IMP (3<<5)
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#define ACR_WPROTECT (1<<2)
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/****************************************************************************/
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#endif /* m5307sim_h */
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-27
arch/m68k/include/asm/m532xsim.h
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-27
arch/m68k/include/asm/m532xsim.h
···
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#define CPU_NAME "COLDFIRE(m532x)"
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#define CPU_INSTR_PER_JIFFY 3
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#include <asm/m53xxacr.h>
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#define MCF_REG32(x) (*(volatile unsigned long *)(x))
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#define MCF_REG16(x) (*(volatile unsigned short *)(x))
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#define MCF_REG08(x) (*(volatile unsigned char *)(x))
···
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*/
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#define MCF_IRQ_TIMER (64 + 32) /* Timer0 */
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#define MCF_IRQ_PROFILER (64 + 33) /* Timer1 */
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/*
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* Define the Cache register flags.
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*/
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#define CACR_EC (1<<31)
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#define CACR_ESB (1<<29)
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#define CACR_DPI (1<<28)
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#define CACR_HLCK (1<<27)
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#define CACR_CINVA (1<<24)
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#define CACR_DNFB (1<<10)
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#define CACR_DCM_WTHRU (0<<8)
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#define CACR_DCM_WBACK (1<<8)
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#define CACR_DCM_OFF_PRE (2<<8)
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#define CACR_DCM_OFF_IMP (3<<8)
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#define CACR_DW (1<<5)
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#define ACR_BASE_POS 24
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#define ACR_MASK_POS 16
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#define ACR_ENABLE (1<<15)
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#define ACR_USER (0<<13)
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#define ACR_SUPER (1<<13)
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#define ACR_ANY (2<<13)
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#define ACR_CM_WTHRU (0<<5)
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#define ACR_CM_WBACK (1<<5)
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#define ACR_CM_OFF_PRE (2<<5)
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#define ACR_CM_OFF_IMP (3<<5)
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#define ACR_WPROTECT (1<<2)
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/*
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* UART module.
+52
arch/m68k/include/asm/m53xxacr.h
+52
arch/m68k/include/asm/m53xxacr.h
···
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/****************************************************************************/
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/*
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* m53xxacr.h -- ColdFire version 3 core cache support
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*
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* (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com>
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*/
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/****************************************************************************/
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#ifndef m53xxacr_h
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#define m53xxacr_h
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/****************************************************************************/
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/*
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* All varients of the ColdFire using version 3 cores have a similar
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* cache setup. They have a unified instruction and data cache, with
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* configurable write-through or copy-back operation.
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*/
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/*
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* Define the Cache Control register flags.
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*/
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#define CACR_EC 0x80000000 /* Enable cache */
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#define CACR_ESB 0x20000000 /* Enable store buffer */
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#define CACR_DPI 0x10000000 /* Disable invalidation by CPUSHL */
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#define CACR_HLCK 0x08000000 /* Half cache lock mode */
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#define CACR_CINVA 0x01000000 /* Invalidate cache */
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#define CACR_DNFB 0x00000400 /* Inhibited fill buffer */
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#define CACR_DCM_WT 0x00000000 /* Cacheable write-through */
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#define CACR_DCM_CB 0x00000100 /* Cacheable copy-back */
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#define CACR_DCM_PRE 0x00000200 /* Cache inhibited, precise */
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#define CACR_DCM_IMPRE 0x00000300 /* Cache inhibited, imprecise */
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#define CACR_WPROTECT 0x00000020 /* Write protect*/
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#define CACR_EUSP 0x00000010 /* Eanble separate user a7 */
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/*
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* Define the Access Control register flags.
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*/
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#define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */
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#define ACR_MASK_POS 16 /* Address Mask (next 8 bits) */
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#define ACR_ENABLE 0x00008000 /* Enable this ACR */
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#define ACR_USER 0x00000000 /* Allow only user accesses */
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#define ACR_SUPER 0x00002000 /* Allow supervisor access only */
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#define ACR_ANY 0x00004000 /* Allow any access type */
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#define ACR_CM_WT 0x00000000 /* Cacheable, write-through */
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#define ACR_CM_CB 0x00000020 /* Cacheable, copy-back */
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#define ACR_CM_PRE 0x00000040 /* Cache inhibited, precise */
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#define ACR_CM_IMPRE 0x00000060 /* Cache inhibited, imprecise */
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#define ACR_WPROTECT 0x00000004 /* Write protect region */
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/****************************************************************************/
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#endif /* m53xxsim_h */