tjh.dev / kernel
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phy: qcom: sgmii-eth: move PCS registers to separate header

Follow the example of the rest of the QMP PHY drivers and move SGMII PCS
registers to a separate header file.

Cc: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240126-phy-qmp-merge-common-v2-8-a463d0b57836@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Dmitry Baryshkov and committed by
Vinod Koul 25ee21fc df71879b

+47 -37
+20
drivers/phy/qualcomm/phy-qcom-qmp-pcs-sgmii.h
··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * Copyright (c) 2023, Linaro Limited 4 + */ 5 + 6 + #ifndef QCOM_PHY_QMP_PCS_SGMII_H_ 7 + #define QCOM_PHY_QMP_PCS_SGMII_H_ 8 + 9 + #define QPHY_PCS_PHY_START 0x000 10 + #define QPHY_PCS_POWER_DOWN_CONTROL 0x004 11 + #define QPHY_PCS_SW_RESET 0x008 12 + #define QPHY_PCS_LINE_RESET_TIME 0x00c 13 + #define QPHY_PCS_TX_LARGE_AMP_DRV_LVL 0x020 14 + #define QPHY_PCS_TX_SMALL_AMP_DRV_LVL 0x028 15 + #define QPHY_PCS_PCS_READY_STATUS 0x094 16 + #define QPHY_PCS_TX_MID_TERM_CTRL1 0x0d8 17 + #define QPHY_PCS_TX_MID_TERM_CTRL2 0x0dc 18 + #define QPHY_PCS_SGMII_MISC_CTRL8 0x118 19 + 20 + #endif
+27 -37
drivers/phy/qualcomm/phy-qcom-sgmii-eth.c
··· 11 11 #include <linux/platform_device.h> 12 12 #include <linux/regmap.h> 13 13 14 + #include "phy-qcom-qmp-pcs-sgmii.h" 14 15 #include "phy-qcom-qmp-qserdes-com-v5.h" 15 16 #include "phy-qcom-qmp-qserdes-txrx-v5.h" 16 17 ··· 19 18 #define QSERDES_RX 0x600 20 19 #define QSERDES_TX 0x400 21 20 #define QSERDES_PCS 0xc00 22 - 23 - #define QSERDES_PCS_PHY_START (QSERDES_PCS + 0x0) 24 - #define QSERDES_PCS_POWER_DOWN_CONTROL (QSERDES_PCS + 0x4) 25 - #define QSERDES_PCS_SW_RESET (QSERDES_PCS + 0x8) 26 - #define QSERDES_PCS_LINE_RESET_TIME (QSERDES_PCS + 0xc) 27 - #define QSERDES_PCS_TX_LARGE_AMP_DRV_LVL (QSERDES_PCS + 0x20) 28 - #define QSERDES_PCS_TX_SMALL_AMP_DRV_LVL (QSERDES_PCS + 0x28) 29 - #define QSERDES_PCS_TX_MID_TERM_CTRL1 (QSERDES_PCS + 0xd8) 30 - #define QSERDES_PCS_TX_MID_TERM_CTRL2 (QSERDES_PCS + 0xdc) 31 - #define QSERDES_PCS_SGMII_MISC_CTRL8 (QSERDES_PCS + 0x118) 32 - #define QSERDES_PCS_PCS_READY_STATUS (QSERDES_PCS + 0x94) 33 21 34 22 #define QSERDES_COM_C_READY BIT(0) 35 23 #define QSERDES_PCS_READY BIT(0) ··· 33 43 34 44 static void qcom_dwmac_sgmii_phy_init_1g(struct regmap *regmap) 35 45 { 36 - regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x01); 37 - regmap_write(regmap, QSERDES_PCS_POWER_DOWN_CONTROL, 0x01); 46 + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x01); 47 + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_POWER_DOWN_CONTROL, 0x01); 38 48 39 49 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_IVCO, 0x0F); 40 50 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CP_CTRL_MODE0, 0x06); ··· 108 118 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xB7); 109 119 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_DCC_CTRL1, 0x0C); 110 120 111 - regmap_write(regmap, QSERDES_PCS_LINE_RESET_TIME, 0x0C); 112 - regmap_write(regmap, QSERDES_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F); 113 - regmap_write(regmap, QSERDES_PCS_TX_SMALL_AMP_DRV_LVL, 0x03); 114 - regmap_write(regmap, QSERDES_PCS_TX_MID_TERM_CTRL1, 0x83); 115 - regmap_write(regmap, QSERDES_PCS_TX_MID_TERM_CTRL2, 0x08); 116 - regmap_write(regmap, QSERDES_PCS_SGMII_MISC_CTRL8, 0x0C); 117 - regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x00); 121 + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_LINE_RESET_TIME, 0x0C); 122 + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F); 123 + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_SMALL_AMP_DRV_LVL, 0x03); 124 + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL1, 0x83); 125 + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL2, 0x08); 126 + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SGMII_MISC_CTRL8, 0x0C); 127 + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x00); 118 128 119 - regmap_write(regmap, QSERDES_PCS_PHY_START, 0x01); 129 + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_PHY_START, 0x01); 120 130 } 121 131 122 132 static void qcom_dwmac_sgmii_phy_init_2p5g(struct regmap *regmap) 123 133 { 124 - regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x01); 125 - regmap_write(regmap, QSERDES_PCS_POWER_DOWN_CONTROL, 0x01); 134 + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x01); 135 + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_POWER_DOWN_CONTROL, 0x01); 126 136 127 137 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_IVCO, 0x0F); 128 138 regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CP_CTRL_MODE0, 0x06); ··· 196 206 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xB7); 197 207 regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_DCC_CTRL1, 0x0C); 198 208 199 - regmap_write(regmap, QSERDES_PCS_LINE_RESET_TIME, 0x0C); 200 - regmap_write(regmap, QSERDES_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F); 201 - regmap_write(regmap, QSERDES_PCS_TX_SMALL_AMP_DRV_LVL, 0x03); 202 - regmap_write(regmap, QSERDES_PCS_TX_MID_TERM_CTRL1, 0x83); 203 - regmap_write(regmap, QSERDES_PCS_TX_MID_TERM_CTRL2, 0x08); 204 - regmap_write(regmap, QSERDES_PCS_SGMII_MISC_CTRL8, 0x8C); 205 - regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x00); 209 + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_LINE_RESET_TIME, 0x0C); 210 + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F); 211 + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_SMALL_AMP_DRV_LVL, 0x03); 212 + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL1, 0x83); 213 + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL2, 0x08); 214 + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SGMII_MISC_CTRL8, 0x8C); 215 + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x00); 206 216 207 - regmap_write(regmap, QSERDES_PCS_PHY_START, 0x01); 217 + regmap_write(regmap, QSERDES_PCS + QPHY_PCS_PHY_START, 0x01); 208 218 } 209 219 210 220 static inline int ··· 241 251 } 242 252 243 253 if (qcom_dwmac_sgmii_phy_poll_status(data->regmap, 244 - QSERDES_PCS_PCS_READY_STATUS, 254 + QSERDES_PCS + QPHY_PCS_PCS_READY_STATUS, 245 255 QSERDES_PCS_READY)) { 246 256 dev_err(dev, "PCS_READY timed-out"); 247 257 return -ETIMEDOUT; 248 258 } 249 259 250 260 if (qcom_dwmac_sgmii_phy_poll_status(data->regmap, 251 - QSERDES_PCS_PCS_READY_STATUS, 261 + QSERDES_PCS + QPHY_PCS_PCS_READY_STATUS, 252 262 QSERDES_PCS_SGMIIPHY_READY)) { 253 263 dev_err(dev, "SGMIIPHY_READY timed-out"); 254 264 return -ETIMEDOUT; ··· 275 285 { 276 286 struct qcom_dwmac_sgmii_phy_data *data = phy_get_drvdata(phy); 277 287 278 - regmap_write(data->regmap, QSERDES_PCS_TX_MID_TERM_CTRL2, 0x08); 279 - regmap_write(data->regmap, QSERDES_PCS_SW_RESET, 0x01); 288 + regmap_write(data->regmap, QSERDES_PCS + QPHY_PCS_TX_MID_TERM_CTRL2, 0x08); 289 + regmap_write(data->regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x01); 280 290 udelay(100); 281 - regmap_write(data->regmap, QSERDES_PCS_SW_RESET, 0x00); 282 - regmap_write(data->regmap, QSERDES_PCS_PHY_START, 0x01); 291 + regmap_write(data->regmap, QSERDES_PCS + QPHY_PCS_SW_RESET, 0x00); 292 + regmap_write(data->regmap, QSERDES_PCS + QPHY_PCS_PHY_START, 0x01); 283 293 284 294 clk_disable_unprepare(data->refclk); 285 295