tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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phy: qcom: sgmii-eth: use existing register definitions

The Qualcomm SGMII SerDes PHY is a QMP PHY. As such, it uses standard
registers for QSERDES COM/RX/TX regions. Use register defines from the
existing headers.

Cc: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240126-phy-qmp-merge-common-v2-7-a463d0b57836@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Dmitry Baryshkov and committed by
Vinod Koul df71879b fe3ec760

+142 -211
+142 -211
drivers/phy/qualcomm/phy-qcom-sgmii-eth.c
··· 11 11 #include <linux/platform_device.h> 12 12 #include <linux/regmap.h> 13 13 14 + #include "phy-qcom-qmp-qserdes-com-v5.h" 15 + #include "phy-qcom-qmp-qserdes-txrx-v5.h" 16 + 14 17 #define QSERDES_QMP_PLL 0x0 15 - #define QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 (QSERDES_QMP_PLL + 0x1ac) 16 - #define QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 (QSERDES_QMP_PLL + 0x1b0) 17 - #define QSERDES_COM_BIN_VCOCAL_HSCLK_SEL (QSERDES_QMP_PLL + 0x1bc) 18 - #define QSERDES_COM_CORE_CLK_EN (QSERDES_QMP_PLL + 0x174) 19 - #define QSERDES_COM_CORECLK_DIV_MODE0 (QSERDES_QMP_PLL + 0x168) 20 - #define QSERDES_COM_CP_CTRL_MODE0 (QSERDES_QMP_PLL + 0x74) 21 - #define QSERDES_COM_DEC_START_MODE0 (QSERDES_QMP_PLL + 0xbc) 22 - #define QSERDES_COM_DIV_FRAC_START1_MODE0 (QSERDES_QMP_PLL + 0xcc) 23 - #define QSERDES_COM_DIV_FRAC_START2_MODE0 (QSERDES_QMP_PLL + 0xd0) 24 - #define QSERDES_COM_DIV_FRAC_START3_MODE0 (QSERDES_QMP_PLL + 0xd4) 25 - #define QSERDES_COM_HSCLK_HS_SWITCH_SEL (QSERDES_QMP_PLL + 0x15c) 26 - #define QSERDES_COM_HSCLK_SEL (QSERDES_QMP_PLL + 0x158) 27 - #define QSERDES_COM_LOCK_CMP1_MODE0 (QSERDES_QMP_PLL + 0xac) 28 - #define QSERDES_COM_LOCK_CMP2_MODE0 (QSERDES_QMP_PLL + 0xb0) 29 - #define QSERDES_COM_PLL_CCTRL_MODE0 (QSERDES_QMP_PLL + 0x84) 30 - #define QSERDES_COM_PLL_IVCO (QSERDES_QMP_PLL + 0x58) 31 - #define QSERDES_COM_PLL_RCTRL_MODE0 (QSERDES_QMP_PLL + 0x7c) 32 - #define QSERDES_COM_SYSCLK_EN_SEL (QSERDES_QMP_PLL + 0x94) 33 - #define QSERDES_COM_VCO_TUNE1_MODE0 (QSERDES_QMP_PLL + 0x110) 34 - #define QSERDES_COM_VCO_TUNE2_MODE0 (QSERDES_QMP_PLL + 0x114) 35 - #define QSERDES_COM_VCO_TUNE_INITVAL2 (QSERDES_QMP_PLL + 0x124) 36 - #define QSERDES_COM_C_READY_STATUS (QSERDES_QMP_PLL + 0x178) 37 - #define QSERDES_COM_CMN_STATUS (QSERDES_QMP_PLL + 0x140) 38 - 39 18 #define QSERDES_RX 0x600 40 - #define QSERDES_RX_UCDR_FO_GAIN (QSERDES_RX + 0x8) 41 - #define QSERDES_RX_UCDR_SO_GAIN (QSERDES_RX + 0x14) 42 - #define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN (QSERDES_RX + 0x30) 43 - #define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE (QSERDES_RX + 0x34) 44 - #define QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW (QSERDES_RX + 0x3c) 45 - #define QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH (QSERDES_RX + 0x40) 46 - #define QSERDES_RX_UCDR_PI_CONTROLS (QSERDES_RX + 0x44) 47 - #define QSERDES_RX_UCDR_PI_CTRL2 (QSERDES_RX + 0x48) 48 - #define QSERDES_RX_RX_TERM_BW (QSERDES_RX + 0x80) 49 - #define QSERDES_RX_VGA_CAL_CNTRL2 (QSERDES_RX + 0xd8) 50 - #define QSERDES_RX_GM_CAL (QSERDES_RX + 0xdc) 51 - #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1 (QSERDES_RX + 0xe8) 52 - #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 (QSERDES_RX + 0xec) 53 - #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 (QSERDES_RX + 0xf0) 54 - #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 (QSERDES_RX + 0xf4) 55 - #define QSERDES_RX_RX_IDAC_TSETTLE_LOW (QSERDES_RX + 0xf8) 56 - #define QSERDES_RX_RX_IDAC_TSETTLE_HIGH (QSERDES_RX + 0xfc) 57 - #define QSERDES_RX_RX_IDAC_MEASURE_TIME (QSERDES_RX + 0x100) 58 - #define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 (QSERDES_RX + 0x110) 59 - #define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 (QSERDES_RX + 0x114) 60 - #define QSERDES_RX_SIGDET_CNTRL (QSERDES_RX + 0x11c) 61 - #define QSERDES_RX_SIGDET_DEGLITCH_CNTRL (QSERDES_RX + 0x124) 62 - #define QSERDES_RX_RX_BAND (QSERDES_RX + 0x128) 63 - #define QSERDES_RX_RX_MODE_00_LOW (QSERDES_RX + 0x15c) 64 - #define QSERDES_RX_RX_MODE_00_HIGH (QSERDES_RX + 0x160) 65 - #define QSERDES_RX_RX_MODE_00_HIGH2 (QSERDES_RX + 0x164) 66 - #define QSERDES_RX_RX_MODE_00_HIGH3 (QSERDES_RX + 0x168) 67 - #define QSERDES_RX_RX_MODE_00_HIGH4 (QSERDES_RX + 0x16c) 68 - #define QSERDES_RX_RX_MODE_01_LOW (QSERDES_RX + 0x170) 69 - #define QSERDES_RX_RX_MODE_01_HIGH (QSERDES_RX + 0x174) 70 - #define QSERDES_RX_RX_MODE_01_HIGH2 (QSERDES_RX + 0x178) 71 - #define QSERDES_RX_RX_MODE_01_HIGH3 (QSERDES_RX + 0x17c) 72 - #define QSERDES_RX_RX_MODE_01_HIGH4 (QSERDES_RX + 0x180) 73 - #define QSERDES_RX_RX_MODE_10_LOW (QSERDES_RX + 0x184) 74 - #define QSERDES_RX_RX_MODE_10_HIGH (QSERDES_RX + 0x188) 75 - #define QSERDES_RX_RX_MODE_10_HIGH2 (QSERDES_RX + 0x18c) 76 - #define QSERDES_RX_RX_MODE_10_HIGH3 (QSERDES_RX + 0x190) 77 - #define QSERDES_RX_RX_MODE_10_HIGH4 (QSERDES_RX + 0x194) 78 - #define QSERDES_RX_DCC_CTRL1 (QSERDES_RX + 0x1a8) 79 - 80 19 #define QSERDES_TX 0x400 81 - #define QSERDES_TX_TX_BAND (QSERDES_TX + 0x24) 82 - #define QSERDES_TX_SLEW_CNTL (QSERDES_TX + 0x28) 83 - #define QSERDES_TX_RES_CODE_LANE_OFFSET_TX (QSERDES_TX + 0x3c) 84 - #define QSERDES_TX_RES_CODE_LANE_OFFSET_RX (QSERDES_TX + 0x40) 85 - #define QSERDES_TX_LANE_MODE_1 (QSERDES_TX + 0x84) 86 - #define QSERDES_TX_LANE_MODE_3 (QSERDES_TX + 0x8c) 87 - #define QSERDES_TX_RCV_DETECT_LVL_2 (QSERDES_TX + 0xa4) 88 - #define QSERDES_TX_TRAN_DRVR_EMP_EN (QSERDES_TX + 0xc0) 20 + #define QSERDES_PCS 0xc00 89 21 90 - #define QSERDES_PCS 0xC00 91 22 #define QSERDES_PCS_PHY_START (QSERDES_PCS + 0x0) 92 23 #define QSERDES_PCS_POWER_DOWN_CONTROL (QSERDES_PCS + 0x4) 93 24 #define QSERDES_PCS_SW_RESET (QSERDES_PCS + 0x8) ··· 46 115 regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x01); 47 116 regmap_write(regmap, QSERDES_PCS_POWER_DOWN_CONTROL, 0x01); 48 117 49 - regmap_write(regmap, QSERDES_COM_PLL_IVCO, 0x0F); 50 - regmap_write(regmap, QSERDES_COM_CP_CTRL_MODE0, 0x06); 51 - regmap_write(regmap, QSERDES_COM_PLL_RCTRL_MODE0, 0x16); 52 - regmap_write(regmap, QSERDES_COM_PLL_CCTRL_MODE0, 0x36); 53 - regmap_write(regmap, QSERDES_COM_SYSCLK_EN_SEL, 0x1A); 54 - regmap_write(regmap, QSERDES_COM_LOCK_CMP1_MODE0, 0x0A); 55 - regmap_write(regmap, QSERDES_COM_LOCK_CMP2_MODE0, 0x1A); 56 - regmap_write(regmap, QSERDES_COM_DEC_START_MODE0, 0x82); 57 - regmap_write(regmap, QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55); 58 - regmap_write(regmap, QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55); 59 - regmap_write(regmap, QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03); 60 - regmap_write(regmap, QSERDES_COM_VCO_TUNE1_MODE0, 0x24); 118 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_IVCO, 0x0F); 119 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CP_CTRL_MODE0, 0x06); 120 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16); 121 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36); 122 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1A); 123 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0A); 124 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1A); 125 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DEC_START_MODE0, 0x82); 126 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55); 127 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55); 128 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03); 129 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24); 61 130 62 - regmap_write(regmap, QSERDES_COM_VCO_TUNE2_MODE0, 0x02); 63 - regmap_write(regmap, QSERDES_COM_VCO_TUNE_INITVAL2, 0x00); 64 - regmap_write(regmap, QSERDES_COM_HSCLK_SEL, 0x04); 65 - regmap_write(regmap, QSERDES_COM_HSCLK_HS_SWITCH_SEL, 0x00); 66 - regmap_write(regmap, QSERDES_COM_CORECLK_DIV_MODE0, 0x0A); 67 - regmap_write(regmap, QSERDES_COM_CORE_CLK_EN, 0x00); 68 - regmap_write(regmap, QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xB9); 69 - regmap_write(regmap, QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1E); 70 - regmap_write(regmap, QSERDES_COM_BIN_VCOCAL_HSCLK_SEL, 0x11); 131 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x02); 132 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00); 133 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_HSCLK_SEL, 0x04); 134 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00); 135 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0A); 136 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CORE_CLK_EN, 0x00); 137 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xB9); 138 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1E); 139 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11); 71 140 72 - regmap_write(regmap, QSERDES_TX_TX_BAND, 0x05); 73 - regmap_write(regmap, QSERDES_TX_SLEW_CNTL, 0x0A); 74 - regmap_write(regmap, QSERDES_TX_RES_CODE_LANE_OFFSET_TX, 0x09); 75 - regmap_write(regmap, QSERDES_TX_RES_CODE_LANE_OFFSET_RX, 0x09); 76 - regmap_write(regmap, QSERDES_TX_LANE_MODE_1, 0x05); 77 - regmap_write(regmap, QSERDES_TX_LANE_MODE_3, 0x00); 78 - regmap_write(regmap, QSERDES_TX_RCV_DETECT_LVL_2, 0x12); 79 - regmap_write(regmap, QSERDES_TX_TRAN_DRVR_EMP_EN, 0x0C); 141 + regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_TX_BAND, 0x05); 142 + regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_SLEW_CNTL, 0x0A); 143 + regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09); 144 + regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09); 145 + regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_LANE_MODE_1, 0x05); 146 + regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_LANE_MODE_3, 0x00); 147 + regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12); 148 + regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0C); 80 149 81 - regmap_write(regmap, QSERDES_RX_UCDR_FO_GAIN, 0x0A); 82 - regmap_write(regmap, QSERDES_RX_UCDR_SO_GAIN, 0x06); 83 - regmap_write(regmap, QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0A); 84 - regmap_write(regmap, QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7F); 85 - regmap_write(regmap, QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00); 86 - regmap_write(regmap, QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x01); 87 - regmap_write(regmap, QSERDES_RX_UCDR_PI_CONTROLS, 0x81); 88 - regmap_write(regmap, QSERDES_RX_UCDR_PI_CTRL2, 0x80); 89 - regmap_write(regmap, QSERDES_RX_RX_TERM_BW, 0x04); 90 - regmap_write(regmap, QSERDES_RX_VGA_CAL_CNTRL2, 0x08); 91 - regmap_write(regmap, QSERDES_RX_GM_CAL, 0x0F); 92 - regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04); 93 - regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00); 94 - regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4A); 95 - regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0A); 96 - regmap_write(regmap, QSERDES_RX_RX_IDAC_TSETTLE_LOW, 0x80); 97 - regmap_write(regmap, QSERDES_RX_RX_IDAC_TSETTLE_HIGH, 0x01); 98 - regmap_write(regmap, QSERDES_RX_RX_IDAC_MEASURE_TIME, 0x20); 99 - regmap_write(regmap, QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17); 100 - regmap_write(regmap, QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00); 101 - regmap_write(regmap, QSERDES_RX_SIGDET_CNTRL, 0x0F); 102 - regmap_write(regmap, QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E); 103 - regmap_write(regmap, QSERDES_RX_RX_BAND, 0x05); 104 - regmap_write(regmap, QSERDES_RX_RX_MODE_00_LOW, 0xE0); 105 - regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH, 0xC8); 106 - regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH2, 0xC8); 107 - regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH3, 0x09); 108 - regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH4, 0xB1); 109 - regmap_write(regmap, QSERDES_RX_RX_MODE_01_LOW, 0xE0); 110 - regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH, 0xC8); 111 - regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH2, 0xC8); 112 - regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH3, 0x09); 113 - regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH4, 0xB1); 114 - regmap_write(regmap, QSERDES_RX_RX_MODE_10_LOW, 0xE0); 115 - regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH, 0xC8); 116 - regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH2, 0xC8); 117 - regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH3, 0x3B); 118 - regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH4, 0xB7); 119 - regmap_write(regmap, QSERDES_RX_DCC_CTRL1, 0x0C); 150 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FO_GAIN, 0x0A); 151 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_SO_GAIN, 0x06); 152 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0A); 153 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7F); 154 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00); 155 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x01); 156 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x81); 157 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80); 158 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_TERM_BW, 0x04); 159 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x08); 160 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_GM_CAL, 0x0F); 161 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04); 162 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00); 163 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4A); 164 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0A); 165 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80); 166 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01); 167 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20); 168 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17); 169 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00); 170 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_SIGDET_CNTRL, 0x0F); 171 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1E); 172 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_BAND, 0x05); 173 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_LOW, 0xE0); 174 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH, 0xC8); 175 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xC8); 176 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x09); 177 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xB1); 178 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_LOW, 0xE0); 179 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH, 0xC8); 180 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xC8); 181 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x09); 182 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xB1); 183 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_LOW, 0xE0); 184 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH, 0xC8); 185 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xC8); 186 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3B); 187 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xB7); 188 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_DCC_CTRL1, 0x0C); 120 189 121 190 regmap_write(regmap, QSERDES_PCS_LINE_RESET_TIME, 0x0C); 122 191 regmap_write(regmap, QSERDES_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F); ··· 134 203 regmap_write(regmap, QSERDES_PCS_SW_RESET, 0x01); 135 204 regmap_write(regmap, QSERDES_PCS_POWER_DOWN_CONTROL, 0x01); 136 205 137 - regmap_write(regmap, QSERDES_COM_PLL_IVCO, 0x0F); 138 - regmap_write(regmap, QSERDES_COM_CP_CTRL_MODE0, 0x06); 139 - regmap_write(regmap, QSERDES_COM_PLL_RCTRL_MODE0, 0x16); 140 - regmap_write(regmap, QSERDES_COM_PLL_CCTRL_MODE0, 0x36); 141 - regmap_write(regmap, QSERDES_COM_SYSCLK_EN_SEL, 0x1A); 142 - regmap_write(regmap, QSERDES_COM_LOCK_CMP1_MODE0, 0x1A); 143 - regmap_write(regmap, QSERDES_COM_LOCK_CMP2_MODE0, 0x41); 144 - regmap_write(regmap, QSERDES_COM_DEC_START_MODE0, 0x7A); 145 - regmap_write(regmap, QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00); 146 - regmap_write(regmap, QSERDES_COM_DIV_FRAC_START2_MODE0, 0x20); 147 - regmap_write(regmap, QSERDES_COM_DIV_FRAC_START3_MODE0, 0x01); 148 - regmap_write(regmap, QSERDES_COM_VCO_TUNE1_MODE0, 0xA1); 206 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_IVCO, 0x0F); 207 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CP_CTRL_MODE0, 0x06); 208 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16); 209 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36); 210 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1A); 211 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x1A); 212 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x41); 213 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DEC_START_MODE0, 0x7A); 214 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x00); 215 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x20); 216 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x01); 217 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_VCO_TUNE1_MODE0, 0xA1); 149 218 150 - regmap_write(regmap, QSERDES_COM_VCO_TUNE2_MODE0, 0x02); 151 - regmap_write(regmap, QSERDES_COM_VCO_TUNE_INITVAL2, 0x00); 152 - regmap_write(regmap, QSERDES_COM_HSCLK_SEL, 0x03); 153 - regmap_write(regmap, QSERDES_COM_HSCLK_HS_SWITCH_SEL, 0x00); 154 - regmap_write(regmap, QSERDES_COM_CORECLK_DIV_MODE0, 0x05); 155 - regmap_write(regmap, QSERDES_COM_CORE_CLK_EN, 0x00); 156 - regmap_write(regmap, QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xCD); 157 - regmap_write(regmap, QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1C); 158 - regmap_write(regmap, QSERDES_COM_BIN_VCOCAL_HSCLK_SEL, 0x11); 219 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x02); 220 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00); 221 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_HSCLK_SEL, 0x03); 222 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00); 223 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x05); 224 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_CORE_CLK_EN, 0x00); 225 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xCD); 226 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1C); 227 + regmap_write(regmap, QSERDES_QMP_PLL + QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11); 159 228 160 - regmap_write(regmap, QSERDES_TX_TX_BAND, 0x04); 161 - regmap_write(regmap, QSERDES_TX_SLEW_CNTL, 0x0A); 162 - regmap_write(regmap, QSERDES_TX_RES_CODE_LANE_OFFSET_TX, 0x09); 163 - regmap_write(regmap, QSERDES_TX_RES_CODE_LANE_OFFSET_RX, 0x02); 164 - regmap_write(regmap, QSERDES_TX_LANE_MODE_1, 0x05); 165 - regmap_write(regmap, QSERDES_TX_LANE_MODE_3, 0x00); 166 - regmap_write(regmap, QSERDES_TX_RCV_DETECT_LVL_2, 0x12); 167 - regmap_write(regmap, QSERDES_TX_TRAN_DRVR_EMP_EN, 0x0C); 229 + regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_TX_BAND, 0x04); 230 + regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_SLEW_CNTL, 0x0A); 231 + regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09); 232 + regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x02); 233 + regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_LANE_MODE_1, 0x05); 234 + regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_LANE_MODE_3, 0x00); 235 + regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12); 236 + regmap_write(regmap, QSERDES_TX + QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0C); 168 237 169 - regmap_write(regmap, QSERDES_RX_UCDR_FO_GAIN, 0x0A); 170 - regmap_write(regmap, QSERDES_RX_UCDR_SO_GAIN, 0x06); 171 - regmap_write(regmap, QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0A); 172 - regmap_write(regmap, QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7F); 173 - regmap_write(regmap, QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00); 174 - regmap_write(regmap, QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x01); 175 - regmap_write(regmap, QSERDES_RX_UCDR_PI_CONTROLS, 0x81); 176 - regmap_write(regmap, QSERDES_RX_UCDR_PI_CTRL2, 0x80); 177 - regmap_write(regmap, QSERDES_RX_RX_TERM_BW, 0x00); 178 - regmap_write(regmap, QSERDES_RX_VGA_CAL_CNTRL2, 0x08); 179 - regmap_write(regmap, QSERDES_RX_GM_CAL, 0x0F); 180 - regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04); 181 - regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00); 182 - regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4A); 183 - regmap_write(regmap, QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0A); 184 - regmap_write(regmap, QSERDES_RX_RX_IDAC_TSETTLE_LOW, 0x80); 185 - regmap_write(regmap, QSERDES_RX_RX_IDAC_TSETTLE_HIGH, 0x01); 186 - regmap_write(regmap, QSERDES_RX_RX_IDAC_MEASURE_TIME, 0x20); 187 - regmap_write(regmap, QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17); 188 - regmap_write(regmap, QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00); 189 - regmap_write(regmap, QSERDES_RX_SIGDET_CNTRL, 0x0F); 190 - regmap_write(regmap, QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E); 191 - regmap_write(regmap, QSERDES_RX_RX_BAND, 0x18); 192 - regmap_write(regmap, QSERDES_RX_RX_MODE_00_LOW, 0x18); 193 - regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH, 0xC8); 194 - regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH2, 0xC8); 195 - regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH3, 0x0C); 196 - regmap_write(regmap, QSERDES_RX_RX_MODE_00_HIGH4, 0xB8); 197 - regmap_write(regmap, QSERDES_RX_RX_MODE_01_LOW, 0xE0); 198 - regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH, 0xC8); 199 - regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH2, 0xC8); 200 - regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH3, 0x09); 201 - regmap_write(regmap, QSERDES_RX_RX_MODE_01_HIGH4, 0xB1); 202 - regmap_write(regmap, QSERDES_RX_RX_MODE_10_LOW, 0xE0); 203 - regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH, 0xC8); 204 - regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH2, 0xC8); 205 - regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH3, 0x3B); 206 - regmap_write(regmap, QSERDES_RX_RX_MODE_10_HIGH4, 0xB7); 207 - regmap_write(regmap, QSERDES_RX_DCC_CTRL1, 0x0C); 238 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FO_GAIN, 0x0A); 239 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_SO_GAIN, 0x06); 240 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0A); 241 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7F); 242 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00); 243 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x01); 244 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x81); 245 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80); 246 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_TERM_BW, 0x00); 247 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x08); 248 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_GM_CAL, 0x0F); 249 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04); 250 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00); 251 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4A); 252 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0A); 253 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80); 254 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01); 255 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20); 256 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17); 257 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00); 258 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_SIGDET_CNTRL, 0x0F); 259 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1E); 260 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_BAND, 0x18); 261 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_LOW, 0x18); 262 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH, 0xC8); 263 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xC8); 264 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x0C); 265 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xB8); 266 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_LOW, 0xE0); 267 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH, 0xC8); 268 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xC8); 269 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x09); 270 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xB1); 271 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_LOW, 0xE0); 272 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH, 0xC8); 273 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xC8); 274 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3B); 275 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xB7); 276 + regmap_write(regmap, QSERDES_RX + QSERDES_V5_RX_DCC_CTRL1, 0x0C); 208 277 209 278 regmap_write(regmap, QSERDES_PCS_LINE_RESET_TIME, 0x0C); 210 279 regmap_write(regmap, QSERDES_PCS_TX_LARGE_AMP_DRV_LVL, 0x1F); ··· 244 313 } 245 314 246 315 if (qcom_dwmac_sgmii_phy_poll_status(data->regmap, 247 - QSERDES_COM_C_READY_STATUS, 316 + QSERDES_QMP_PLL + QSERDES_V5_COM_C_READY_STATUS, 248 317 QSERDES_COM_C_READY)) { 249 318 dev_err(dev, "QSERDES_COM_C_READY_STATUS timed-out"); 250 319 return -ETIMEDOUT; ··· 265 334 } 266 335 267 336 if (qcom_dwmac_sgmii_phy_poll_status(data->regmap, 268 - QSERDES_COM_CMN_STATUS, 337 + QSERDES_QMP_PLL + QSERDES_V5_COM_CMN_STATUS, 269 338 QSERDES_COM_C_PLL_LOCKED)) { 270 339 dev_err(dev, "PLL Lock Status timed-out"); 271 340 return -ETIMEDOUT;