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[MIPS] merge GT64111 PCI routines and GT64120 PCI_0 routines

This patch has merged GT64111 PCI routines and GT64120 PCI_0 routines.
GT64111 PCI is almost the same as GT64120's PCI_0.
This patch don't change GT64120 PCI routines.

Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

authored by

Yoichi Yuasa and committed by
Ralf Baechle 252161ec 2a9effc6

+33 -137
+8 -11
arch/mips/Kconfig
··· 165 165 select HW_HAS_PCI 166 166 select I8259 167 167 select IRQ_CPU 168 - select MIPS_GT64111 168 + select PCI_GT64XXX_PCI0 169 169 select SYS_HAS_CPU_NEVADA 170 170 select SYS_HAS_EARLY_PRINTK 171 171 select SYS_SUPPORTS_32BIT_KERNEL ··· 207 207 depends on EXPERIMENTAL 208 208 select DMA_NONCOHERENT 209 209 select HW_HAS_PCI 210 - select MIPS_GT64120 210 + select PCI_GT64XXX_PCI0 211 211 select SYS_HAS_CPU_R5000 212 212 select SYS_SUPPORTS_32BIT_KERNEL 213 213 select SYS_SUPPORTS_64BIT_KERNEL ··· 245 245 select DMA_NONCOHERENT 246 246 select SYS_HAS_EARLY_PRINTK 247 247 select HW_HAS_PCI 248 - select MIPS_GT64120 248 + select PCI_GT64XXX_PCI0 249 249 select MIPS_NILE4 250 250 select R5000_CPU_SCACHE 251 251 select SYS_HAS_CPU_R5000 ··· 263 263 select HW_HAS_PCI 264 264 select MIPS_BOARDS_GEN 265 265 select MIPS_BONITO64 266 - select MIPS_GT64120 266 + select PCI_GT64XXX_PCI0 267 267 select MIPS_MSC 268 268 select RM7000_CPU_SCACHE 269 269 select SWAP_IO_SPACE ··· 296 296 select MIPS_BOARDS_GEN 297 297 select MIPS_BONITO64 298 298 select MIPS_CPU_SCACHE 299 - select MIPS_GT64120 299 + select PCI_GT64XXX_PCI0 300 300 select MIPS_MSC 301 301 select SWAP_IO_SPACE 302 302 select SYS_HAS_CPU_MIPS32_R1 ··· 340 340 select BOOT_ELF32 341 341 select DMA_NONCOHERENT 342 342 select HW_HAS_PCI 343 - select MIPS_GT64120 343 + select PCI_GT64XXX_PCI0 344 344 select SWAP_IO_SPACE 345 345 select SYS_HAS_CPU_MIPS32_R1 346 346 select SYS_HAS_CPU_MIPS32_R2 ··· 398 398 select HW_HAS_PCI 399 399 select IRQ_CPU 400 400 select IRQ_CPU_RM7K 401 - select MIPS_GT64120 401 + select PCI_GT64XXX_PCI0 402 402 select RM7000_CPU_SCACHE 403 403 select SWAP_IO_SPACE 404 404 select SYS_HAS_CPU_RM7000 ··· 999 999 config MIPS_BOARDS_GEN 1000 1000 bool 1001 1001 1002 - config MIPS_GT64111 1003 - bool 1004 - 1005 - config MIPS_GT64120 1002 + config PCI_GT64XXX_PCI0 1006 1003 bool 1007 1004 1008 1005 config MIPS_TX3927
+2 -2
arch/mips/cobalt/pci.c
··· 14 14 15 15 #include <asm/gt64120.h> 16 16 17 - extern struct pci_ops gt64111_pci_ops; 17 + extern struct pci_ops gt64xxx_pci0_ops; 18 18 19 19 static struct resource cobalt_mem_resource = { 20 20 .start = GT_DEF_PCI0_MEM0_BASE, ··· 31 31 }; 32 32 33 33 static struct pci_controller cobalt_pci_controller = { 34 - .pci_ops = &gt64111_pci_ops, 34 + .pci_ops = &gt64xxx_pci0_ops, 35 35 .mem_resource = &cobalt_mem_resource, 36 36 .io_resource = &cobalt_io_resource, 37 37 .io_offset = 0 - GT_DEF_PCI0_IO_BASE,
+2 -2
arch/mips/gt64120/wrppmc/pci.c
··· 13 13 #include <linux/kernel.h> 14 14 #include <asm/gt64120.h> 15 15 16 - extern struct pci_ops gt64120_pci_ops; 16 + extern struct pci_ops gt64xxx_pci0_ops; 17 17 18 18 static struct resource pci0_io_resource = { 19 19 .name = "pci_0 io", ··· 30 30 }; 31 31 32 32 static struct pci_controller hose_0 = { 33 - .pci_ops = &gt64120_pci_ops, 33 + .pci_ops = &gt64xxx_pci0_ops, 34 34 .io_resource = &pci0_io_resource, 35 35 .mem_resource = &pci0_mem_resource, 36 36 };
+2 -2
arch/mips/mips-boards/generic/pci.c
··· 65 65 }; 66 66 67 67 extern struct pci_ops bonito64_pci_ops; 68 - extern struct pci_ops gt64120_pci_ops; 68 + extern struct pci_ops gt64xxx_pci0_ops; 69 69 extern struct pci_ops msc_pci_ops; 70 70 71 71 static struct pci_controller bonito64_controller = { ··· 76 76 }; 77 77 78 78 static struct pci_controller gt64120_controller = { 79 - .pci_ops = &gt64120_pci_ops, 79 + .pci_ops = &gt64xxx_pci0_ops, 80 80 .io_resource = &gt64120_io_resource, 81 81 .mem_resource = &gt64120_mem_resource, 82 82 };
+1 -2
arch/mips/pci/Makefile
··· 8 8 # PCI bus host bridge specific code 9 9 # 10 10 obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o 11 - obj-$(CONFIG_MIPS_GT64111) += ops-gt64111.o 12 - obj-$(CONFIG_MIPS_GT64120) += ops-gt64120.o 11 + obj-$(CONFIG_PCI_GT64XXX_PCI0) += ops-gt64xxx_pci0.o 13 12 obj-$(CONFIG_PCI_MARVELL) += ops-marvell.o 14 13 obj-$(CONFIG_MIPS_MSC) += ops-msc.o 15 14 obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
-100
arch/mips/pci/ops-gt64111.c
··· 1 - /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 - * Copyright (C) 1995, 1996, 1997, 2002 by Ralf Baechle 7 - * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv) 8 - */ 9 - #include <linux/types.h> 10 - #include <linux/pci.h> 11 - #include <linux/kernel.h> 12 - #include <linux/init.h> 13 - 14 - #include <asm/pci.h> 15 - #include <asm/io.h> 16 - #include <asm/gt64120.h> 17 - 18 - #include <asm/mach-cobalt/cobalt.h> 19 - 20 - /* 21 - * Device 31 on the GT64111 is used to generate PCI special 22 - * cycles, so we shouldn't expected to find a device there ... 23 - */ 24 - static inline int pci_range_ck(struct pci_bus *bus, unsigned int devfn) 25 - { 26 - if (bus->number == 0 && PCI_SLOT(devfn) < 31) 27 - return 0; 28 - 29 - return -1; 30 - } 31 - 32 - static int gt64111_pci_read_config(struct pci_bus *bus, unsigned int devfn, 33 - int where, int size, u32 * val) 34 - { 35 - if (pci_range_ck(bus, devfn)) 36 - return PCIBIOS_DEVICE_NOT_FOUND; 37 - 38 - switch (size) { 39 - case 4: 40 - PCI_CFG_SET(devfn, where); 41 - *val = GT_READ(GT_PCI0_CFGDATA_OFS); 42 - return PCIBIOS_SUCCESSFUL; 43 - 44 - case 2: 45 - PCI_CFG_SET(devfn, (where & ~0x3)); 46 - *val = GT_READ(GT_PCI0_CFGDATA_OFS) 47 - >> ((where & 3) * 8); 48 - return PCIBIOS_SUCCESSFUL; 49 - 50 - case 1: 51 - PCI_CFG_SET(devfn, (where & ~0x3)); 52 - *val = GT_READ(GT_PCI0_CFGDATA_OFS) 53 - >> ((where & 3) * 8); 54 - return PCIBIOS_SUCCESSFUL; 55 - } 56 - 57 - return PCIBIOS_BAD_REGISTER_NUMBER; 58 - } 59 - 60 - static int gt64111_pci_write_config(struct pci_bus *bus, unsigned int devfn, 61 - int where, int size, u32 val) 62 - { 63 - u32 tmp; 64 - 65 - if (pci_range_ck(bus, devfn)) 66 - return PCIBIOS_DEVICE_NOT_FOUND; 67 - 68 - switch (size) { 69 - case 4: 70 - PCI_CFG_SET(devfn, where); 71 - GT_WRITE(GT_PCI0_CFGDATA_OFS, val); 72 - 73 - return PCIBIOS_SUCCESSFUL; 74 - 75 - case 2: 76 - PCI_CFG_SET(devfn, (where & ~0x3)); 77 - tmp = GT_READ(GT_PCI0_CFGDATA_OFS); 78 - tmp &= ~(0xffff << ((where & 0x3) * 8)); 79 - tmp |= (val << ((where & 0x3) * 8)); 80 - GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp); 81 - 82 - return PCIBIOS_SUCCESSFUL; 83 - 84 - case 1: 85 - PCI_CFG_SET(devfn, (where & ~0x3)); 86 - tmp = GT_READ(GT_PCI0_CFGDATA_OFS); 87 - tmp &= ~(0xff << ((where & 0x3) * 8)); 88 - tmp |= (val << ((where & 0x3) * 8)); 89 - GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp); 90 - 91 - return PCIBIOS_SUCCESSFUL; 92 - } 93 - 94 - return PCIBIOS_BAD_REGISTER_NUMBER; 95 - } 96 - 97 - struct pci_ops gt64111_pci_ops = { 98 - .read = gt64111_pci_read_config, 99 - .write = gt64111_pci_write_config, 100 - };
+15 -15
arch/mips/pci/ops-gt64120.c arch/mips/pci/ops-gt64xxx_pci0.c
··· 39 39 #define PCI_CFG_TYPE1_DEV_SHF 11 40 40 #define PCI_CFG_TYPE1_BUS_SHF 16 41 41 42 - static int gt64120_pcibios_config_access(unsigned char access_type, 43 - struct pci_bus *bus, unsigned int devfn, int where, u32 * data) 42 + static int gt64xxx_pci0_pcibios_config_access(unsigned char access_type, 43 + struct pci_bus *bus, unsigned int devfn, int where, u32 * data) 44 44 { 45 45 unsigned char busnum = bus->number; 46 46 u32 intr; ··· 100 100 * We can't address 8 and 16 bit words directly. Instead we have to 101 101 * read/write a 32bit word and mask/modify the data we actually want. 102 102 */ 103 - static int gt64120_pcibios_read(struct pci_bus *bus, unsigned int devfn, 104 - int where, int size, u32 * val) 103 + static int gt64xxx_pci0_pcibios_read(struct pci_bus *bus, unsigned int devfn, 104 + int where, int size, u32 * val) 105 105 { 106 106 u32 data = 0; 107 107 108 - if (gt64120_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, 109 - &data)) 108 + if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, 109 + where, &data)) 110 110 return PCIBIOS_DEVICE_NOT_FOUND; 111 111 112 112 if (size == 1) ··· 119 119 return PCIBIOS_SUCCESSFUL; 120 120 } 121 121 122 - static int gt64120_pcibios_write(struct pci_bus *bus, unsigned int devfn, 123 - int where, int size, u32 val) 122 + static int gt64xxx_pci0_pcibios_write(struct pci_bus *bus, unsigned int devfn, 123 + int where, int size, u32 val) 124 124 { 125 125 u32 data = 0; 126 126 127 127 if (size == 4) 128 128 data = val; 129 129 else { 130 - if (gt64120_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, 131 - where, &data)) 130 + if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_READ, bus, 131 + devfn, where, &data)) 132 132 return PCIBIOS_DEVICE_NOT_FOUND; 133 133 134 134 if (size == 1) ··· 139 139 (val << ((where & 3) << 3)); 140 140 } 141 141 142 - if (gt64120_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where, 143 - &data)) 142 + if (gt64xxx_pci0_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, 143 + where, &data)) 144 144 return PCIBIOS_DEVICE_NOT_FOUND; 145 145 146 146 return PCIBIOS_SUCCESSFUL; 147 147 } 148 148 149 - struct pci_ops gt64120_pci_ops = { 150 - .read = gt64120_pcibios_read, 151 - .write = gt64120_pcibios_write 149 + struct pci_ops gt64xxx_pci0_ops = { 150 + .read = gt64xxx_pci0_pcibios_read, 151 + .write = gt64xxx_pci0_pcibios_write 152 152 };
+2 -2
arch/mips/pci/pci-lasat.c
··· 12 12 #include <asm/bootinfo.h> 13 13 14 14 extern struct pci_ops nile4_pci_ops; 15 - extern struct pci_ops gt64120_pci_ops; 15 + extern struct pci_ops gt64xxx_pci0_ops; 16 16 static struct resource lasat_pci_mem_resource = { 17 17 .name = "LASAT PCI MEM", 18 18 .start = 0x18000000, ··· 38 38 39 39 switch (mips_machtype) { 40 40 case MACH_LASAT_100: 41 - lasat_pci_controller.pci_ops = &gt64120_pci_ops; 41 + lasat_pci_controller.pci_ops = &gt64xxx_pci0_ops; 42 42 break; 43 43 case MACH_LASAT_200: 44 44 lasat_pci_controller.pci_ops = &nile4_pci_ops;
+1 -1
arch/mips/pci/pci-ocelot.c
··· 81 81 }; 82 82 83 83 static struct pci_controller ocelot_pci_controller = { 84 - .pci_ops = gt64120_pci_ops; 84 + .pci_ops = gt64xxx_pci0_ops; 85 85 .mem_resource = &ocelot_mem_resource; 86 86 .io_resource = &ocelot_io_resource; 87 87 };