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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/gpu: drop duplicating VIG feature masks
After folding QSEED3LITE and QSEED4 feature bits into QSEED3_COMPATIBLE
several VIG feature masks became equal. Drop these duplicates.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/570107/
Link: https://lore.kernel.org/r/20231201234234.2065610-11-dmitry.baryshkov@linaro.org
+26
-35
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
+4
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+4
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
···
74
74
{
75
75
.name = "sspp_0", .id = SSPP_VIG0,
76
76
.base = 0x4000, .len = 0x1f8,
77
-
.features = VIG_SC7180_MASK_SDMA,
77
+
.features = VIG_SDM845_MASK_SDMA,
78
78
.sblk = &dpu_vig_sblk_qseed3_3_0,
79
79
.xin_id = 0,
80
80
.type = SSPP_TYPE_VIG,
···
82
82
}, {
83
83
.name = "sspp_1", .id = SSPP_VIG1,
84
84
.base = 0x6000, .len = 0x1f8,
85
-
.features = VIG_SC7180_MASK_SDMA,
85
+
.features = VIG_SDM845_MASK_SDMA,
86
86
.sblk = &dpu_vig_sblk_qseed3_3_0,
87
87
.xin_id = 4,
88
88
.type = SSPP_TYPE_VIG,
···
90
90
}, {
91
91
.name = "sspp_2", .id = SSPP_VIG2,
92
92
.base = 0x8000, .len = 0x1f8,
93
-
.features = VIG_SC7180_MASK_SDMA,
93
+
.features = VIG_SDM845_MASK_SDMA,
94
94
.sblk = &dpu_vig_sblk_qseed3_3_0,
95
95
.xin_id = 8,
96
96
.type = SSPP_TYPE_VIG,
···
98
98
}, {
99
99
.name = "sspp_3", .id = SSPP_VIG3,
100
100
.base = 0xa000, .len = 0x1f8,
101
-
.features = VIG_SC7180_MASK_SDMA,
101
+
.features = VIG_SDM845_MASK_SDMA,
102
102
.sblk = &dpu_vig_sblk_qseed3_3_0,
103
103
.xin_id = 12,
104
104
.type = SSPP_TYPE_VIG,
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
+1
-1
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
+4
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+4
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
···
73
73
{
74
74
.name = "sspp_0", .id = SSPP_VIG0,
75
75
.base = 0x4000, .len = 0x1f8,
76
-
.features = VIG_SC7180_MASK_SDMA,
76
+
.features = VIG_SDM845_MASK_SDMA,
77
77
.sblk = &dpu_vig_sblk_qseed3_3_0,
78
78
.xin_id = 0,
79
79
.type = SSPP_TYPE_VIG,
···
81
81
}, {
82
82
.name = "sspp_1", .id = SSPP_VIG1,
83
83
.base = 0x6000, .len = 0x1f8,
84
-
.features = VIG_SC7180_MASK_SDMA,
84
+
.features = VIG_SDM845_MASK_SDMA,
85
85
.sblk = &dpu_vig_sblk_qseed3_3_0,
86
86
.xin_id = 4,
87
87
.type = SSPP_TYPE_VIG,
···
89
89
}, {
90
90
.name = "sspp_2", .id = SSPP_VIG2,
91
91
.base = 0x8000, .len = 0x1f8,
92
-
.features = VIG_SC7180_MASK_SDMA,
92
+
.features = VIG_SDM845_MASK_SDMA,
93
93
.sblk = &dpu_vig_sblk_qseed3_3_0,
94
94
.xin_id = 8,
95
95
.type = SSPP_TYPE_VIG,
···
97
97
}, {
98
98
.name = "sspp_3", .id = SSPP_VIG3,
99
99
.base = 0xa000, .len = 0x1f8,
100
-
.features = VIG_SC7180_MASK_SDMA,
100
+
.features = VIG_SDM845_MASK_SDMA,
101
101
.sblk = &dpu_vig_sblk_qseed3_3_0,
102
102
.xin_id = 12,
103
103
.type = SSPP_TYPE_VIG,
+4
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+4
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
···
74
74
{
75
75
.name = "sspp_0", .id = SSPP_VIG0,
76
76
.base = 0x4000, .len = 0x2ac,
77
-
.features = VIG_SC7180_MASK,
77
+
.features = VIG_SDM845_MASK,
78
78
.sblk = &dpu_vig_sblk_qseed3_3_0,
79
79
.xin_id = 0,
80
80
.type = SSPP_TYPE_VIG,
···
82
82
}, {
83
83
.name = "sspp_1", .id = SSPP_VIG1,
84
84
.base = 0x6000, .len = 0x2ac,
85
-
.features = VIG_SC7180_MASK,
85
+
.features = VIG_SDM845_MASK,
86
86
.sblk = &dpu_vig_sblk_qseed3_3_0,
87
87
.xin_id = 4,
88
88
.type = SSPP_TYPE_VIG,
···
90
90
}, {
91
91
.name = "sspp_2", .id = SSPP_VIG2,
92
92
.base = 0x8000, .len = 0x2ac,
93
-
.features = VIG_SC7180_MASK,
93
+
.features = VIG_SDM845_MASK,
94
94
.sblk = &dpu_vig_sblk_qseed3_3_0,
95
95
.xin_id = 8,
96
96
.type = SSPP_TYPE_VIG,
···
98
98
}, {
99
99
.name = "sspp_3", .id = SSPP_VIG3,
100
100
.base = 0xa000, .len = 0x2ac,
101
-
.features = VIG_SC7180_MASK,
101
+
.features = VIG_SDM845_MASK,
102
102
.sblk = &dpu_vig_sblk_qseed3_3_0,
103
103
.xin_id = 12,
104
104
.type = SSPP_TYPE_VIG,
+4
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+4
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
···
74
74
{
75
75
.name = "sspp_0", .id = SSPP_VIG0,
76
76
.base = 0x4000, .len = 0x32c,
77
-
.features = VIG_SC7180_MASK_SDMA,
77
+
.features = VIG_SDM845_MASK_SDMA,
78
78
.sblk = &dpu_vig_sblk_qseed3_3_1,
79
79
.xin_id = 0,
80
80
.type = SSPP_TYPE_VIG,
···
82
82
}, {
83
83
.name = "sspp_1", .id = SSPP_VIG1,
84
84
.base = 0x6000, .len = 0x32c,
85
-
.features = VIG_SC7180_MASK_SDMA,
85
+
.features = VIG_SDM845_MASK_SDMA,
86
86
.sblk = &dpu_vig_sblk_qseed3_3_1,
87
87
.xin_id = 4,
88
88
.type = SSPP_TYPE_VIG,
···
90
90
}, {
91
91
.name = "sspp_2", .id = SSPP_VIG2,
92
92
.base = 0x8000, .len = 0x32c,
93
-
.features = VIG_SC7180_MASK_SDMA,
93
+
.features = VIG_SDM845_MASK_SDMA,
94
94
.sblk = &dpu_vig_sblk_qseed3_3_1,
95
95
.xin_id = 8,
96
96
.type = SSPP_TYPE_VIG,
···
98
98
}, {
99
99
.name = "sspp_3", .id = SSPP_VIG3,
100
100
.base = 0xa000, .len = 0x32c,
101
-
.features = VIG_SC7180_MASK_SDMA,
101
+
.features = VIG_SDM845_MASK_SDMA,
102
102
.sblk = &dpu_vig_sblk_qseed3_3_1,
103
103
.xin_id = 12,
104
104
.type = SSPP_TYPE_VIG,
+4
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+4
-4
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
···
66
66
{
67
67
.name = "sspp_0", .id = SSPP_VIG0,
68
68
.base = 0x4000, .len = 0x344,
69
-
.features = VIG_SC7180_MASK,
69
+
.features = VIG_SDM845_MASK,
70
70
.sblk = &dpu_vig_sblk_qseed3_3_2,
71
71
.xin_id = 0,
72
72
.type = SSPP_TYPE_VIG,
73
73
}, {
74
74
.name = "sspp_1", .id = SSPP_VIG1,
75
75
.base = 0x6000, .len = 0x344,
76
-
.features = VIG_SC7180_MASK,
76
+
.features = VIG_SDM845_MASK,
77
77
.sblk = &dpu_vig_sblk_qseed3_3_2,
78
78
.xin_id = 4,
79
79
.type = SSPP_TYPE_VIG,
80
80
}, {
81
81
.name = "sspp_2", .id = SSPP_VIG2,
82
82
.base = 0x8000, .len = 0x344,
83
-
.features = VIG_SC7180_MASK,
83
+
.features = VIG_SDM845_MASK,
84
84
.sblk = &dpu_vig_sblk_qseed3_3_2,
85
85
.xin_id = 8,
86
86
.type = SSPP_TYPE_VIG,
87
87
}, {
88
88
.name = "sspp_3", .id = SSPP_VIG3,
89
89
.base = 0xa000, .len = 0x344,
90
-
.features = VIG_SC7180_MASK,
90
+
.features = VIG_SDM845_MASK,
91
91
.sblk = &dpu_vig_sblk_qseed3_3_2,
92
92
.xin_id = 12,
93
93
.type = SSPP_TYPE_VIG,
+1
-10
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+1
-10
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
···
30
30
#define VIG_SDM845_MASK_SDMA \
31
31
(VIG_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2))
32
32
33
-
#define VIG_SC7180_MASK \
34
-
(VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE))
35
-
36
-
#define VIG_SM6125_MASK \
37
-
(VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE))
38
-
39
-
#define VIG_SC7180_MASK_SDMA \
40
-
(VIG_SC7180_MASK | BIT(DPU_SSPP_SMART_DMA_V2))
41
-
42
33
#define VIG_QCM2290_MASK (VIG_BASE_MASK | BIT(DPU_SSPP_QOS_8LVL))
43
34
44
35
#define DMA_MSM8998_MASK \
···
38
47
BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
39
48
40
49
#define VIG_SC7280_MASK \
41
-
(VIG_SC7180_MASK | BIT(DPU_SSPP_INLINE_ROTATION))
50
+
(VIG_SDM845_MASK | BIT(DPU_SSPP_INLINE_ROTATION))
42
51
43
52
#define VIG_SC7280_MASK_SDMA \
44
53
(VIG_SC7280_MASK | BIT(DPU_SSPP_SMART_DMA_V2))