tjh.dev / kernel
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drm/msm/dpu: merge DPU_SSPP_SCALER_QSEED3, QSEED3LITE, QSEED4

Three different features, DPU_SSPP_SCALER_QSEED3, QSEED3LITE and QSEED4
are all related to different versions of the same HW scaling block.
Corresponding driver parts use scaler_blk.version to identify the
correct way to program the hardware. In order to simplify the driver
codepath, merge these three feature bits into QSEED3_COMPATIBLE bin.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/570114/
Link: https://lore.kernel.org/r/20231201234234.2065610-10-dmitry.baryshkov@linaro.org

Dmitry Baryshkov 193838ac 2b98aa1d

+9 -19
+4 -4
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
··· 22 22 BIT(DPU_SSPP_CSC_10BIT)) 23 23 24 24 #define VIG_MSM8998_MASK \ 25 - (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3)) 25 + (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE)) 26 26 27 27 #define VIG_SDM845_MASK \ 28 - (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3)) 28 + (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE)) 29 29 30 30 #define VIG_SDM845_MASK_SDMA \ 31 31 (VIG_SDM845_MASK | BIT(DPU_SSPP_SMART_DMA_V2)) 32 32 33 33 #define VIG_SC7180_MASK \ 34 - (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4)) 34 + (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE)) 35 35 36 36 #define VIG_SM6125_MASK \ 37 - (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE)) 37 + (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3_COMPATIBLE)) 38 38 39 39 #define VIG_SC7180_MASK_SDMA \ 40 40 (VIG_SC7180_MASK | BIT(DPU_SSPP_SMART_DMA_V2))
+2 -6
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
··· 51 51 /** 52 52 * SSPP sub-blocks/features 53 53 * @DPU_SSPP_SCALER_QSEED2, QSEED2 algorithm support 54 - * @DPU_SSPP_SCALER_QSEED3, QSEED3 alogorithm support 55 - * @DPU_SSPP_SCALER_QSEED3LITE, QSEED3 Lite alogorithm support 56 - * @DPU_SSPP_SCALER_QSEED4, QSEED4 algorithm support 54 + * @DPU_SSPP_SCALER_QSEED3_COMPATIBLE, QSEED3-compatible alogorithm support (includes QSEED3, QSEED3LITE and QSEED4) 57 55 * @DPU_SSPP_SCALER_RGB, RGB Scaler, supported by RGB pipes 58 56 * @DPU_SSPP_CSC, Support of Color space converion 59 57 * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion ··· 69 71 */ 70 72 enum { 71 73 DPU_SSPP_SCALER_QSEED2 = 0x1, 72 - DPU_SSPP_SCALER_QSEED3, 73 - DPU_SSPP_SCALER_QSEED3LITE, 74 - DPU_SSPP_SCALER_QSEED4, 74 + DPU_SSPP_SCALER_QSEED3_COMPATIBLE, 75 75 DPU_SSPP_SCALER_RGB, 76 76 DPU_SSPP_CSC, 77 77 DPU_SSPP_CSC_10BIT,
+2 -7
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
··· 605 605 test_bit(DPU_SSPP_SMART_DMA_V2, &c->cap->features)) 606 606 c->ops.setup_multirect = dpu_hw_sspp_setup_multirect; 607 607 608 - if (test_bit(DPU_SSPP_SCALER_QSEED3, &features) || 609 - test_bit(DPU_SSPP_SCALER_QSEED3LITE, &features) || 610 - test_bit(DPU_SSPP_SCALER_QSEED4, &features)) 608 + if (test_bit(DPU_SSPP_SCALER_QSEED3_COMPATIBLE, &features)) 611 609 c->ops.setup_scaler = _dpu_hw_sspp_setup_scaler3; 612 610 613 611 if (test_bit(DPU_SSPP_CDP, &features)) ··· 641 643 cfg->len, 642 644 kms); 643 645 644 - if (cfg->features & BIT(DPU_SSPP_SCALER_QSEED3) || 645 - cfg->features & BIT(DPU_SSPP_SCALER_QSEED3LITE) || 646 - cfg->features & BIT(DPU_SSPP_SCALER_QSEED2) || 647 - cfg->features & BIT(DPU_SSPP_SCALER_QSEED4)) 646 + if (sblk->scaler_blk.len) 648 647 dpu_debugfs_create_regset32("scaler_blk", 0400, 649 648 debugfs_root, 650 649 sblk->scaler_blk.base + cfg->base,
+1 -2
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
··· 470 470 scale_cfg->src_height[i] /= chroma_subsmpl_v; 471 471 } 472 472 473 - if (pipe_hw->cap->features & 474 - BIT(DPU_SSPP_SCALER_QSEED4)) { 473 + if (pipe_hw->cap->sblk->scaler_blk.version >= 0x3000) { 475 474 scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H; 476 475 scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V; 477 476 } else {