tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/meson: Convert existing documentation to actual kerneldoc
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
+65
-30
+3
-1
drivers/gpu/drm/meson/meson_canvas.c
+3
-1
drivers/gpu/drm/meson/meson_canvas.c
+3
-2
drivers/gpu/drm/meson/meson_drv.c
+3
-2
drivers/gpu/drm/meson/meson_drv.c
···
52
52
#define DRIVER_NAME "meson"
53
53
#define DRIVER_DESC "Amlogic Meson DRM driver"
54
54
55
-
/*
56
-
* Video Processing Unit
55
+
/**
56
+
* DOC: Video Processing Unit
57
57
*
58
58
* VPU Handles the Global Video Processing, it includes management of the
59
59
* clocks gates, blocks reset lines and power domains.
60
60
*
61
61
* What is missing :
62
+
*
62
63
* - Full reset of entire video processing HW blocks
63
64
* - Scaling and setup of the VPU clock
64
65
* - Bus clock gates
+17
-8
drivers/gpu/drm/meson/meson_dw_hdmi.c
+17
-8
drivers/gpu/drm/meson/meson_dw_hdmi.c
···
42
42
#define DRIVER_NAME "meson-dw-hdmi"
43
43
#define DRIVER_DESC "Amlogic Meson HDMI-TX DRM driver"
44
44
45
-
/*
45
+
/**
46
+
* DOC: HDMI Output
47
+
*
46
48
* HDMI Output is composed of :
49
+
*
47
50
* - A Synopsys DesignWare HDMI Controller IP
48
51
* - A TOP control block controlling the Clocks and PHY
49
52
* - A custom HDMI PHY in order convert video to TMDS signal
50
-
* ___________________________________
51
-
* | HDMI TOP |<= HPD
52
-
* |___________________________________|
53
-
* | | |
54
-
* | Synopsys HDMI | HDMI PHY |=> TMDS
55
-
* | Controller |________________|
56
-
* |___________________________________|<=> DDC
53
+
*
54
+
* .. code::
55
+
*
56
+
* ___________________________________
57
+
* | HDMI TOP |<= HPD
58
+
* |___________________________________|
59
+
* | | |
60
+
* | Synopsys HDMI | HDMI PHY |=> TMDS
61
+
* | Controller |________________|
62
+
* |___________________________________|<=> DDC
63
+
*
57
64
*
58
65
* The HDMI TOP block only supports HPD sensing.
59
66
* The Synopsys HDMI Controller interrupt is routed
···
85
78
* audio source interfaces.
86
79
*
87
80
* We handle the following features :
81
+
*
88
82
* - HPD Rise & Fall interrupt
89
83
* - HDMI Controller Interrupt
90
84
* - HDMI PHY Init for 480i to 1080p60
···
93
85
* - VENC Mode setup for 480i to 1080p60
94
86
*
95
87
* What is missing :
88
+
*
96
89
* - PHY, Clock and Mode setup for 2k && 4k modes
97
90
* - SDDC Scrambling mode for HDMI 2.0a
98
91
* - HDCP Setup
+15
-7
drivers/gpu/drm/meson/meson_vclk.c
+15
-7
drivers/gpu/drm/meson/meson_vclk.c
···
23
23
#include "meson_drv.h"
24
24
#include "meson_vclk.h"
25
25
26
-
/*
26
+
/**
27
+
* DOC: Video Clocks
28
+
*
27
29
* VCLK is the "Pixel Clock" frequency generator from a dedicated PLL.
28
30
* We handle the following encodings :
31
+
*
29
32
* - CVBS 27MHz generator via the VCLK2 to the VENCI and VDAC blocks
30
33
* - HDMI Pixel Clocks generation
34
+
*
31
35
* What is missing :
36
+
*
32
37
* - Genenate Pixel clocks for 2K/4K 10bit formats
33
38
*
34
39
* Clock generator scheme :
35
-
* __________ _________ _____
36
-
* | | | | | |--ENCI
37
-
* | HDMI PLL |-| PLL_DIV |--- VCLK--| |--ENCL
38
-
* |__________| |_________| \ | MUX |--ENCP
39
-
* --VCLK2-| |--VDAC
40
-
* |_____|--HDMI-TX
40
+
*
41
+
* .. code::
42
+
*
43
+
* __________ _________ _____
44
+
* | | | | | |--ENCI
45
+
* | HDMI PLL |-| PLL_DIV |--- VCLK--| |--ENCL
46
+
* |__________| |_________| \ | MUX |--ENCP
47
+
* --VCLK2-| |--VDAC
48
+
* |_____|--HDMI-TX
41
49
*
42
50
* Final clocks can take input for either VCLK or VCLK2, but
43
51
* VCLK is the preferred path for HDMI clocking and VCLK2 is the
+16
-9
drivers/gpu/drm/meson/meson_venc.c
+16
-9
drivers/gpu/drm/meson/meson_venc.c
···
26
26
#include "meson_vclk.h"
27
27
#include "meson_registers.h"
28
28
29
-
/*
29
+
/**
30
+
* DOC: Video Encoder
31
+
*
30
32
* VENC Handle the pixels encoding to the output formats.
31
33
* We handle the following encodings :
34
+
*
32
35
* - CVBS Encoding via the ENCI encoder and VDAC digital to analog converter
33
36
* - TMDS/HDMI Encoding via ENCI_DIV and ENCP
34
37
* - Setup of more clock rates for HDMI modes
35
38
*
36
39
* What is missing :
40
+
*
37
41
* - LCD Panel encoding via ENCL
38
42
* - TV Panel encoding via ENCT
39
43
*
40
44
* VENC paths :
41
-
* _____ _____ ____________________
42
-
* vd1---| |-| | | VENC /---------|----VDAC
43
-
* vd2---| VIU |-| VPP |-|-----ENCI/-ENCI_DVI-|\
44
-
* osd1--| |-| | | \ | X--HDMI-TX
45
-
* osd2--|_____|-|_____| | |\-ENCP--ENCP_DVI-|/
46
-
* | | |
47
-
* | \--ENCL-----------|----LVDS
48
-
* |____________________|
45
+
*
46
+
* .. code::
47
+
*
48
+
* _____ _____ ____________________
49
+
* vd1---| |-| | | VENC /---------|----VDAC
50
+
* vd2---| VIU |-| VPP |-|-----ENCI/-ENCI_DVI-|-|
51
+
* osd1--| |-| | | \ | X--HDMI-TX
52
+
* osd2--|_____|-|_____| | |\-ENCP--ENCP_DVI-|-|
53
+
* | | |
54
+
* | \--ENCL-----------|----LVDS
55
+
* |____________________|
49
56
*
50
57
* The ENCI is designed for PAl or NTSC encoding and can go through the VDAC
51
58
* directly for CVBS encoding or through the ENCI_DVI encoder for HDMI.
+5
-1
drivers/gpu/drm/meson/meson_viu.c
+5
-1
drivers/gpu/drm/meson/meson_viu.c
···
28
28
#include "meson_canvas.h"
29
29
#include "meson_registers.h"
30
30
31
-
/*
31
+
/**
32
+
* DOC: Video Input Unit
33
+
*
32
34
* VIU Handles the Pixel scanout and the basic Colorspace conversions
33
35
* We handle the following features :
36
+
*
34
37
* - OSD1 RGB565/RGB888/xRGB8888 scanout
35
38
* - RGB conversion to x/cb/cr
36
39
* - Progressive or Interlace buffer scanout
···
41
38
* - HDR OSD matrix for GXL/GXM
42
39
*
43
40
* What is missing :
41
+
*
44
42
* - BGR888/xBGR8888/BGRx8888/BGRx8888 modes
45
43
* - YUV4:2:2 Y0CbY1Cr scanout
46
44
* - Conversion to YUV 4:4:4 from 4:2:2 input
+6
-2
drivers/gpu/drm/meson/meson_vpp.c
+6
-2
drivers/gpu/drm/meson/meson_vpp.c
···
25
25
#include "meson_vpp.h"
26
26
#include "meson_registers.h"
27
27
28
-
/*
28
+
/**
29
+
* DOC: Video Post Processing
30
+
*
29
31
* VPP Handles all the Post Processing after the Scanout from the VIU
30
32
* We handle the following post processings :
31
-
* - Postblend : Blends the OSD1 only
33
+
*
34
+
* - Postblend, Blends the OSD1 only
32
35
* We exclude OSD2, VS1, VS1 and Preblend output
33
36
* - Vertical OSD Scaler for OSD1 only, we disable vertical scaler and
34
37
* use it only for interlace scanout
35
38
* - Intermediate FIFO with default Amlogic values
36
39
*
37
40
* What is missing :
41
+
*
38
42
* - Preblend for video overlay pre-scaling
39
43
* - OSD2 support for cursor framebuffer
40
44
* - Video pre-scaling before postblend