Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

dt-bindings: Add bindings for the Amlogic Meson dw-hdmi extension

This binding describes the Amlogic Meson specific extension to the
Synopsys Designware HDMI Controller.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

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Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.txt
··· 1 + Amlogic specific extensions to the Synopsys Designware HDMI Controller 2 + ====================================================================== 3 + 4 + The Amlogic Meson Synopsys Designware Integration is composed of : 5 + - A Synopsys DesignWare HDMI Controller IP 6 + - A TOP control block controlling the Clocks and PHY 7 + - A custom HDMI PHY in order to convert video to TMDS signal 8 + ___________________________________ 9 + | HDMI TOP |<= HPD 10 + |___________________________________| 11 + | | | 12 + | Synopsys HDMI | HDMI PHY |=> TMDS 13 + | Controller |________________| 14 + |___________________________________|<=> DDC 15 + 16 + The HDMI TOP block only supports HPD sensing. 17 + The Synopsys HDMI Controller interrupt is routed through the 18 + TOP Block interrupt. 19 + Communication to the TOP Block and the Synopsys HDMI Controller is done 20 + via a pair of dedicated addr+read/write registers. 21 + The HDMI PHY is configured by registers in the HHI register block. 22 + 23 + Pixel data arrives in 4:4:4 format from the VENC block and the VPU HDMI mux 24 + selects either the ENCI encoder for the 576i or 480i formats or the ENCP 25 + encoder for all the other formats including interlaced HD formats. 26 + 27 + The VENC uses a DVI encoder on top of the ENCI or ENCP encoders to generate 28 + DVI timings for the HDMI controller. 29 + 30 + Amlogic Meson GXBB, GXL and GXM SoCs families embeds the Synopsys DesignWare 31 + HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF 32 + audio source interfaces. 33 + 34 + Required properties: 35 + - compatible: value should be different for each SoC family as : 36 + - GXBB (S905) : "amlogic,meson-gxbb-dw-hdmi" 37 + - GXL (S905X, S905D) : "amlogic,meson-gxl-dw-hdmi" 38 + - GXM (S912) : "amlogic,meson-gxm-dw-hdmi" 39 + followed by the common "amlogic,meson-gx-dw-hdmi" 40 + - reg: Physical base address and length of the controller's registers. 41 + - interrupts: The HDMI interrupt number 42 + - clocks, clock-names : must have the phandles to the HDMI iahb and isfr clocks, 43 + and the Amlogic Meson venci clocks as described in 44 + Documentation/devicetree/bindings/clock/clock-bindings.txt, 45 + the clocks are soc specific, the clock-names should be "iahb", "isfr", "venci" 46 + - resets, resets-names: must have the phandles to the HDMI apb, glue and phy 47 + resets as described in : 48 + Documentation/devicetree/bindings/reset/reset.txt, 49 + the reset-names should be "hdmitx_apb", "hdmitx", "hdmitx_phy" 50 + 51 + Required nodes: 52 + 53 + The connections to the HDMI ports are modeled using the OF graph 54 + bindings specified in Documentation/devicetree/bindings/graph.txt. 55 + 56 + The following table lists for each supported model the port number 57 + corresponding to each HDMI output and input. 58 + 59 + Port 0 Port 1 60 + ----------------------------------------- 61 + S905 (GXBB) VENC Input TMDS Output 62 + S905X (GXL) VENC Input TMDS Output 63 + S905D (GXL) VENC Input TMDS Output 64 + S912 (GXM) VENC Input TMDS Output 65 + 66 + Example: 67 + 68 + hdmi-connector { 69 + compatible = "hdmi-connector"; 70 + type = "a"; 71 + 72 + port { 73 + hdmi_connector_in: endpoint { 74 + remote-endpoint = <&hdmi_tx_tmds_out>; 75 + }; 76 + }; 77 + }; 78 + 79 + hdmi_tx: hdmi-tx@c883a000 { 80 + compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; 81 + reg = <0x0 0xc883a000 0x0 0x1c>; 82 + interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 83 + resets = <&reset RESET_HDMITX_CAPB3>, 84 + <&reset RESET_HDMI_SYSTEM_RESET>, 85 + <&reset RESET_HDMI_TX>; 86 + reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 87 + clocks = <&clkc CLKID_HDMI_PCLK>, 88 + <&clkc CLKID_CLK81>, 89 + <&clkc CLKID_GCLK_VENCI_INT0>; 90 + clock-names = "isfr", "iahb", "venci"; 91 + #address-cells = <1>; 92 + #size-cells = <0>; 93 + 94 + /* VPU VENC Input */ 95 + hdmi_tx_venc_port: port@0 { 96 + reg = <0>; 97 + 98 + hdmi_tx_in: endpoint { 99 + remote-endpoint = <&hdmi_tx_out>; 100 + }; 101 + }; 102 + 103 + /* TMDS Output */ 104 + hdmi_tx_tmds_port: port@1 { 105 + reg = <1>; 106 + 107 + hdmi_tx_tmds_out: endpoint { 108 + remote-endpoint = <&hdmi_connector_in>; 109 + }; 110 + }; 111 + };