Merge tag 'staging-5.12-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging

Pull staging and IIO driver fixes from Greg KH:
"Some small staging and IIO driver fixes:

- MAINTAINERS changes for the move of the staging mailing list

- comedi driver fixes to get request_irq() to work correctly

- counter driver fixes for reported issues with iio devices

- tiny iio driver fixes for reported issues.

All of these have been in linux-next with no reported problems"

* tag 'staging-5.12-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging:
staging: vt665x: fix alignment constraints
staging: comedi: cb_pcidas64: fix request_irq() warn
staging: comedi: cb_pcidas: fix request_irq() warn
MAINTAINERS: move the staging subsystem to lists.linux.dev
MAINTAINERS: move some real subsystems off of the staging mailing list
iio: gyro: mpu3050: Fix error handling in mpu3050_trigger_handler
iio: hid-sensor-temperature: Fix issues of timestamp channel
iio: hid-sensor-humidity: Fix alignment issue of timestamp channel
counter: stm32-timer-cnt: fix ceiling miss-alignment with reload register
counter: stm32-timer-cnt: fix ceiling write max value
counter: stm32-timer-cnt: Report count function when SLAVE_MODE_DISABLED
iio: adc: ab8500-gpadc: Fix off by 10 to 3
iio:adc:stm32-adc: Add HAS_IOMEM dependency
iio: adis16400: Fix an error code in adis16400_initial_setup()
iio: adc: adi-axi-adc: add proper Kconfig dependencies
iio: adc: ad7949: fix wrong ADC result due to incorrect bit mask
iio: hid-sensor-prox: Fix scale not correct issue
iio:adc:qcom-spmi-vadc: add default scale to LR_MUX2_BAT_ID channel

+75 -48
+3 -4
MAINTAINERS
··· 1181 M: Christian Brauner <christian@brauner.io> 1182 M: Hridya Valsaraju <hridya@google.com> 1183 M: Suren Baghdasaryan <surenb@google.com> 1184 - L: devel@driverdev.osuosl.org 1185 S: Supported 1186 T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git 1187 F: drivers/android/ ··· 8116 8117 HISILICON STAGING DRIVERS FOR HIKEY 960/970 8118 M: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> 8119 - L: devel@driverdev.osuosl.org 8120 S: Maintained 8121 F: drivers/staging/hikey9xx/ 8122 ··· 17039 17040 STAGING SUBSYSTEM 17041 M: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 17042 - L: devel@driverdev.osuosl.org 17043 S: Supported 17044 T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git 17045 F: drivers/staging/ ··· 19134 M: Martyn Welch <martyn@welchs.me.uk> 19135 M: Manohar Vanga <manohar.vanga@gmail.com> 19136 M: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 19137 - L: devel@driverdev.osuosl.org 19138 S: Maintained 19139 T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git 19140 F: Documentation/driver-api/vme.rst
··· 1181 M: Christian Brauner <christian@brauner.io> 1182 M: Hridya Valsaraju <hridya@google.com> 1183 M: Suren Baghdasaryan <surenb@google.com> 1184 + L: linux-kernel@vger.kernel.org 1185 S: Supported 1186 T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git 1187 F: drivers/android/ ··· 8116 8117 HISILICON STAGING DRIVERS FOR HIKEY 960/970 8118 M: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> 8119 S: Maintained 8120 F: drivers/staging/hikey9xx/ 8121 ··· 17040 17041 STAGING SUBSYSTEM 17042 M: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 17043 + L: linux-staging@lists.linux.dev 17044 S: Supported 17045 T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git 17046 F: drivers/staging/ ··· 19135 M: Martyn Welch <martyn@welchs.me.uk> 19136 M: Manohar Vanga <manohar.vanga@gmail.com> 19137 M: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 19138 + L: linux-kernel@vger.kernel.org 19139 S: Maintained 19140 T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git 19141 F: Documentation/driver-api/vme.rst
+33 -22
drivers/counter/stm32-timer-cnt.c
··· 31 struct counter_device counter; 32 struct regmap *regmap; 33 struct clk *clk; 34 - u32 ceiling; 35 bool enabled; 36 struct stm32_timer_regs bak; 37 }; ··· 44 * @STM32_COUNT_ENCODER_MODE_3: counts on both TI1FP1 and TI2FP2 edges 45 */ 46 enum stm32_count_function { 47 - STM32_COUNT_SLAVE_MODE_DISABLED = -1, 48 STM32_COUNT_ENCODER_MODE_1, 49 STM32_COUNT_ENCODER_MODE_2, 50 STM32_COUNT_ENCODER_MODE_3, 51 }; 52 53 static enum counter_count_function stm32_count_functions[] = { 54 [STM32_COUNT_ENCODER_MODE_1] = COUNTER_COUNT_FUNCTION_QUADRATURE_X2_A, 55 [STM32_COUNT_ENCODER_MODE_2] = COUNTER_COUNT_FUNCTION_QUADRATURE_X2_B, 56 [STM32_COUNT_ENCODER_MODE_3] = COUNTER_COUNT_FUNCTION_QUADRATURE_X4, ··· 74 const unsigned long val) 75 { 76 struct stm32_timer_cnt *const priv = counter->priv; 77 78 - if (val > priv->ceiling) 79 return -EINVAL; 80 81 return regmap_write(priv->regmap, TIM_CNT, val); ··· 93 regmap_read(priv->regmap, TIM_SMCR, &smcr); 94 95 switch (smcr & TIM_SMCR_SMS) { 96 case 1: 97 *function = STM32_COUNT_ENCODER_MODE_1; 98 return 0; ··· 105 case 3: 106 *function = STM32_COUNT_ENCODER_MODE_3; 107 return 0; 108 } 109 - 110 - return -EINVAL; 111 } 112 113 static int stm32_count_function_set(struct counter_device *counter, ··· 118 u32 cr1, sms; 119 120 switch (function) { 121 case STM32_COUNT_ENCODER_MODE_1: 122 sms = 1; 123 break; ··· 131 sms = 3; 132 break; 133 default: 134 - sms = 0; 135 - break; 136 } 137 138 /* Store enable status */ 139 regmap_read(priv->regmap, TIM_CR1, &cr1); 140 141 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); 142 - 143 - /* TIMx_ARR register shouldn't be buffered (ARPE=0) */ 144 - regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0); 145 - regmap_write(priv->regmap, TIM_ARR, priv->ceiling); 146 147 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms); 148 ··· 189 if (ret) 190 return ret; 191 192 /* TIMx_ARR register shouldn't be buffered (ARPE=0) */ 193 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0); 194 regmap_write(priv->regmap, TIM_ARR, ceiling); 195 196 - priv->ceiling = ceiling; 197 return len; 198 } 199 ··· 280 size_t function; 281 int err; 282 283 - /* Default action mode (e.g. STM32_COUNT_SLAVE_MODE_DISABLED) */ 284 - *action = STM32_SYNAPSE_ACTION_NONE; 285 - 286 err = stm32_count_function_get(counter, count, &function); 287 if (err) 288 - return 0; 289 290 switch (function) { 291 case STM32_COUNT_ENCODER_MODE_1: 292 /* counts up/down on TI1FP1 edge depending on TI2FP2 level */ 293 if (synapse->signal->id == count->synapses[0].signal->id) 294 *action = STM32_SYNAPSE_ACTION_BOTH_EDGES; 295 - break; 296 case STM32_COUNT_ENCODER_MODE_2: 297 /* counts up/down on TI2FP2 edge depending on TI1FP1 level */ 298 if (synapse->signal->id == count->synapses[1].signal->id) 299 *action = STM32_SYNAPSE_ACTION_BOTH_EDGES; 300 - break; 301 case STM32_COUNT_ENCODER_MODE_3: 302 /* counts up/down on both TI1FP1 and TI2FP2 edges */ 303 *action = STM32_SYNAPSE_ACTION_BOTH_EDGES; 304 - break; 305 } 306 - 307 - return 0; 308 } 309 310 static const struct counter_ops stm32_timer_cnt_ops = { ··· 370 371 priv->regmap = ddata->regmap; 372 priv->clk = ddata->clk; 373 - priv->ceiling = ddata->max_arr; 374 375 priv->counter.name = dev_name(dev); 376 priv->counter.parent = dev;
··· 31 struct counter_device counter; 32 struct regmap *regmap; 33 struct clk *clk; 34 + u32 max_arr; 35 bool enabled; 36 struct stm32_timer_regs bak; 37 }; ··· 44 * @STM32_COUNT_ENCODER_MODE_3: counts on both TI1FP1 and TI2FP2 edges 45 */ 46 enum stm32_count_function { 47 + STM32_COUNT_SLAVE_MODE_DISABLED, 48 STM32_COUNT_ENCODER_MODE_1, 49 STM32_COUNT_ENCODER_MODE_2, 50 STM32_COUNT_ENCODER_MODE_3, 51 }; 52 53 static enum counter_count_function stm32_count_functions[] = { 54 + [STM32_COUNT_SLAVE_MODE_DISABLED] = COUNTER_COUNT_FUNCTION_INCREASE, 55 [STM32_COUNT_ENCODER_MODE_1] = COUNTER_COUNT_FUNCTION_QUADRATURE_X2_A, 56 [STM32_COUNT_ENCODER_MODE_2] = COUNTER_COUNT_FUNCTION_QUADRATURE_X2_B, 57 [STM32_COUNT_ENCODER_MODE_3] = COUNTER_COUNT_FUNCTION_QUADRATURE_X4, ··· 73 const unsigned long val) 74 { 75 struct stm32_timer_cnt *const priv = counter->priv; 76 + u32 ceiling; 77 78 + regmap_read(priv->regmap, TIM_ARR, &ceiling); 79 + if (val > ceiling) 80 return -EINVAL; 81 82 return regmap_write(priv->regmap, TIM_CNT, val); ··· 90 regmap_read(priv->regmap, TIM_SMCR, &smcr); 91 92 switch (smcr & TIM_SMCR_SMS) { 93 + case 0: 94 + *function = STM32_COUNT_SLAVE_MODE_DISABLED; 95 + return 0; 96 case 1: 97 *function = STM32_COUNT_ENCODER_MODE_1; 98 return 0; ··· 99 case 3: 100 *function = STM32_COUNT_ENCODER_MODE_3; 101 return 0; 102 + default: 103 + return -EINVAL; 104 } 105 } 106 107 static int stm32_count_function_set(struct counter_device *counter, ··· 112 u32 cr1, sms; 113 114 switch (function) { 115 + case STM32_COUNT_SLAVE_MODE_DISABLED: 116 + sms = 0; 117 + break; 118 case STM32_COUNT_ENCODER_MODE_1: 119 sms = 1; 120 break; ··· 122 sms = 3; 123 break; 124 default: 125 + return -EINVAL; 126 } 127 128 /* Store enable status */ 129 regmap_read(priv->regmap, TIM_CR1, &cr1); 130 131 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); 132 133 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms); 134 ··· 185 if (ret) 186 return ret; 187 188 + if (ceiling > priv->max_arr) 189 + return -ERANGE; 190 + 191 /* TIMx_ARR register shouldn't be buffered (ARPE=0) */ 192 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0); 193 regmap_write(priv->regmap, TIM_ARR, ceiling); 194 195 return len; 196 } 197 ··· 274 size_t function; 275 int err; 276 277 err = stm32_count_function_get(counter, count, &function); 278 if (err) 279 + return err; 280 281 switch (function) { 282 + case STM32_COUNT_SLAVE_MODE_DISABLED: 283 + /* counts on internal clock when CEN=1 */ 284 + *action = STM32_SYNAPSE_ACTION_NONE; 285 + return 0; 286 case STM32_COUNT_ENCODER_MODE_1: 287 /* counts up/down on TI1FP1 edge depending on TI2FP2 level */ 288 if (synapse->signal->id == count->synapses[0].signal->id) 289 *action = STM32_SYNAPSE_ACTION_BOTH_EDGES; 290 + else 291 + *action = STM32_SYNAPSE_ACTION_NONE; 292 + return 0; 293 case STM32_COUNT_ENCODER_MODE_2: 294 /* counts up/down on TI2FP2 edge depending on TI1FP1 level */ 295 if (synapse->signal->id == count->synapses[1].signal->id) 296 *action = STM32_SYNAPSE_ACTION_BOTH_EDGES; 297 + else 298 + *action = STM32_SYNAPSE_ACTION_NONE; 299 + return 0; 300 case STM32_COUNT_ENCODER_MODE_3: 301 /* counts up/down on both TI1FP1 and TI2FP2 edges */ 302 *action = STM32_SYNAPSE_ACTION_BOTH_EDGES; 303 + return 0; 304 + default: 305 + return -EINVAL; 306 } 307 } 308 309 static const struct counter_ops stm32_timer_cnt_ops = { ··· 359 360 priv->regmap = ddata->regmap; 361 priv->clk = ddata->clk; 362 + priv->max_arr = ddata->max_arr; 363 364 priv->counter.name = dev_name(dev); 365 priv->counter.parent = dev;
+3
drivers/iio/adc/Kconfig
··· 266 select IIO_BUFFER 267 select IIO_BUFFER_HW_CONSUMER 268 select IIO_BUFFER_DMAENGINE 269 help 270 Say yes here to build support for Analog Devices Generic 271 AXI ADC IP core. The IP core is used for interfacing with ··· 925 depends on ARCH_STM32 || COMPILE_TEST 926 depends on OF 927 depends on REGULATOR 928 select IIO_BUFFER 929 select MFD_STM32_TIMERS 930 select IIO_STM32_TIMER_TRIGGER
··· 266 select IIO_BUFFER 267 select IIO_BUFFER_HW_CONSUMER 268 select IIO_BUFFER_DMAENGINE 269 + depends on HAS_IOMEM 270 + depends on OF 271 help 272 Say yes here to build support for Analog Devices Generic 273 AXI ADC IP core. The IP core is used for interfacing with ··· 923 depends on ARCH_STM32 || COMPILE_TEST 924 depends on OF 925 depends on REGULATOR 926 + depends on HAS_IOMEM 927 select IIO_BUFFER 928 select MFD_STM32_TIMERS 929 select IIO_STM32_TIMER_TRIGGER
+1 -1
drivers/iio/adc/ab8500-gpadc.c
··· 918 return processed; 919 920 /* Return millivolt or milliamps or millicentigrades */ 921 - *val = processed * 1000; 922 return IIO_VAL_INT; 923 } 924
··· 918 return processed; 919 920 /* Return millivolt or milliamps or millicentigrades */ 921 + *val = processed; 922 return IIO_VAL_INT; 923 } 924
+1 -1
drivers/iio/adc/ad7949.c
··· 91 int ret; 92 int i; 93 int bits_per_word = ad7949_adc->resolution; 94 - int mask = GENMASK(ad7949_adc->resolution, 0); 95 struct spi_message msg; 96 struct spi_transfer tx[] = { 97 {
··· 91 int ret; 92 int i; 93 int bits_per_word = ad7949_adc->resolution; 94 + int mask = GENMASK(ad7949_adc->resolution - 1, 0); 95 struct spi_message msg; 96 struct spi_transfer tx[] = { 97 {
+1 -1
drivers/iio/adc/qcom-spmi-vadc.c
··· 597 VADC_CHAN_NO_SCALE(P_MUX16_1_3, 1) 598 599 VADC_CHAN_NO_SCALE(LR_MUX1_BAT_THERM, 0) 600 - VADC_CHAN_NO_SCALE(LR_MUX2_BAT_ID, 0) 601 VADC_CHAN_NO_SCALE(LR_MUX3_XO_THERM, 0) 602 VADC_CHAN_NO_SCALE(LR_MUX4_AMUX_THM1, 0) 603 VADC_CHAN_NO_SCALE(LR_MUX5_AMUX_THM2, 0)
··· 597 VADC_CHAN_NO_SCALE(P_MUX16_1_3, 1) 598 599 VADC_CHAN_NO_SCALE(LR_MUX1_BAT_THERM, 0) 600 + VADC_CHAN_VOLT(LR_MUX2_BAT_ID, 0, SCALE_DEFAULT) 601 VADC_CHAN_NO_SCALE(LR_MUX3_XO_THERM, 0) 602 VADC_CHAN_NO_SCALE(LR_MUX4_AMUX_THM1, 0) 603 VADC_CHAN_NO_SCALE(LR_MUX5_AMUX_THM2, 0)
+2
drivers/iio/gyro/mpu3050-core.c
··· 551 MPU3050_FIFO_R, 552 &fifo_values[offset], 553 toread); 554 555 dev_dbg(mpu3050->dev, 556 "%04x %04x %04x %04x %04x\n",
··· 551 MPU3050_FIFO_R, 552 &fifo_values[offset], 553 toread); 554 + if (ret) 555 + goto out_trigger_unlock; 556 557 dev_dbg(mpu3050->dev, 558 "%04x %04x %04x %04x %04x\n",
+7 -5
drivers/iio/humidity/hid-sensor-humidity.c
··· 15 struct hid_humidity_state { 16 struct hid_sensor_common common_attributes; 17 struct hid_sensor_hub_attribute_info humidity_attr; 18 - s32 humidity_data; 19 int scale_pre_decml; 20 int scale_post_decml; 21 int scale_precision; ··· 128 struct hid_humidity_state *humid_st = iio_priv(indio_dev); 129 130 if (atomic_read(&humid_st->common_attributes.data_ready)) 131 - iio_push_to_buffers_with_timestamp(indio_dev, 132 - &humid_st->humidity_data, 133 - iio_get_time_ns(indio_dev)); 134 135 return 0; 136 } ··· 144 145 switch (usage_id) { 146 case HID_USAGE_SENSOR_ATMOSPHERIC_HUMIDITY: 147 - humid_st->humidity_data = *(s32 *)raw_data; 148 149 return 0; 150 default:
··· 15 struct hid_humidity_state { 16 struct hid_sensor_common common_attributes; 17 struct hid_sensor_hub_attribute_info humidity_attr; 18 + struct { 19 + s32 humidity_data; 20 + u64 timestamp __aligned(8); 21 + } scan; 22 int scale_pre_decml; 23 int scale_post_decml; 24 int scale_precision; ··· 125 struct hid_humidity_state *humid_st = iio_priv(indio_dev); 126 127 if (atomic_read(&humid_st->common_attributes.data_ready)) 128 + iio_push_to_buffers_with_timestamp(indio_dev, &humid_st->scan, 129 + iio_get_time_ns(indio_dev)); 130 131 return 0; 132 } ··· 142 143 switch (usage_id) { 144 case HID_USAGE_SENSOR_ATMOSPHERIC_HUMIDITY: 145 + humid_st->scan.humidity_data = *(s32 *)raw_data; 146 147 return 0; 148 default:
+1 -2
drivers/iio/imu/adis16400.c
··· 462 if (ret) 463 goto err_ret; 464 465 - ret = sscanf(indio_dev->name, "adis%u\n", &device_id); 466 - if (ret != 1) { 467 ret = -EINVAL; 468 goto err_ret; 469 }
··· 462 if (ret) 463 goto err_ret; 464 465 + if (sscanf(indio_dev->name, "adis%u\n", &device_id) != 1) { 466 ret = -EINVAL; 467 goto err_ret; 468 }
+11 -2
drivers/iio/light/hid-sensor-prox.c
··· 23 struct hid_sensor_common common_attributes; 24 struct hid_sensor_hub_attribute_info prox_attr; 25 u32 human_presence; 26 }; 27 28 /* Channel definitions */ ··· 96 ret_type = IIO_VAL_INT; 97 break; 98 case IIO_CHAN_INFO_SCALE: 99 - *val = prox_state->prox_attr.units; 100 - ret_type = IIO_VAL_INT; 101 break; 102 case IIO_CHAN_INFO_OFFSET: 103 *val = hid_sensor_convert_exponent( ··· 237 HID_USAGE_SENSOR_DATA_MOD_CHANGE_SENSITIVITY_ABS | 238 HID_USAGE_SENSOR_HUMAN_PRESENCE, 239 &st->common_attributes.sensitivity); 240 241 return ret; 242 }
··· 23 struct hid_sensor_common common_attributes; 24 struct hid_sensor_hub_attribute_info prox_attr; 25 u32 human_presence; 26 + int scale_pre_decml; 27 + int scale_post_decml; 28 + int scale_precision; 29 }; 30 31 /* Channel definitions */ ··· 93 ret_type = IIO_VAL_INT; 94 break; 95 case IIO_CHAN_INFO_SCALE: 96 + *val = prox_state->scale_pre_decml; 97 + *val2 = prox_state->scale_post_decml; 98 + ret_type = prox_state->scale_precision; 99 break; 100 case IIO_CHAN_INFO_OFFSET: 101 *val = hid_sensor_convert_exponent( ··· 233 HID_USAGE_SENSOR_DATA_MOD_CHANGE_SENSITIVITY_ABS | 234 HID_USAGE_SENSOR_HUMAN_PRESENCE, 235 &st->common_attributes.sensitivity); 236 + 237 + st->scale_precision = hid_sensor_format_scale( 238 + hsdev->usage, 239 + &st->prox_attr, 240 + &st->scale_pre_decml, &st->scale_post_decml); 241 242 return ret; 243 }
+8 -6
drivers/iio/temperature/hid-sensor-temperature.c
··· 15 struct temperature_state { 16 struct hid_sensor_common common_attributes; 17 struct hid_sensor_hub_attribute_info temperature_attr; 18 - s32 temperature_data; 19 int scale_pre_decml; 20 int scale_post_decml; 21 int scale_precision; ··· 35 BIT(IIO_CHAN_INFO_SAMP_FREQ) | 36 BIT(IIO_CHAN_INFO_HYSTERESIS), 37 }, 38 - IIO_CHAN_SOFT_TIMESTAMP(3), 39 }; 40 41 /* Adjust channel real bits based on report descriptor */ ··· 126 struct temperature_state *temp_st = iio_priv(indio_dev); 127 128 if (atomic_read(&temp_st->common_attributes.data_ready)) 129 - iio_push_to_buffers_with_timestamp(indio_dev, 130 - &temp_st->temperature_data, 131 - iio_get_time_ns(indio_dev)); 132 133 return 0; 134 } ··· 142 143 switch (usage_id) { 144 case HID_USAGE_SENSOR_DATA_ENVIRONMENTAL_TEMPERATURE: 145 - temp_st->temperature_data = *(s32 *)raw_data; 146 return 0; 147 default: 148 return -EINVAL;
··· 15 struct temperature_state { 16 struct hid_sensor_common common_attributes; 17 struct hid_sensor_hub_attribute_info temperature_attr; 18 + struct { 19 + s32 temperature_data; 20 + u64 timestamp __aligned(8); 21 + } scan; 22 int scale_pre_decml; 23 int scale_post_decml; 24 int scale_precision; ··· 32 BIT(IIO_CHAN_INFO_SAMP_FREQ) | 33 BIT(IIO_CHAN_INFO_HYSTERESIS), 34 }, 35 + IIO_CHAN_SOFT_TIMESTAMP(1), 36 }; 37 38 /* Adjust channel real bits based on report descriptor */ ··· 123 struct temperature_state *temp_st = iio_priv(indio_dev); 124 125 if (atomic_read(&temp_st->common_attributes.data_ready)) 126 + iio_push_to_buffers_with_timestamp(indio_dev, &temp_st->scan, 127 + iio_get_time_ns(indio_dev)); 128 129 return 0; 130 } ··· 140 141 switch (usage_id) { 142 case HID_USAGE_SENSOR_DATA_ENVIRONMENTAL_TEMPERATURE: 143 + temp_st->scan.temperature_data = *(s32 *)raw_data; 144 return 0; 145 default: 146 return -EINVAL;
+1 -1
drivers/staging/comedi/drivers/cb_pcidas.c
··· 1281 devpriv->amcc + AMCC_OP_REG_INTCSR); 1282 1283 ret = request_irq(pcidev->irq, cb_pcidas_interrupt, IRQF_SHARED, 1284 - dev->board_name, dev); 1285 if (ret) { 1286 dev_dbg(dev->class_dev, "unable to allocate irq %d\n", 1287 pcidev->irq);
··· 1281 devpriv->amcc + AMCC_OP_REG_INTCSR); 1282 1283 ret = request_irq(pcidev->irq, cb_pcidas_interrupt, IRQF_SHARED, 1284 + "cb_pcidas", dev); 1285 if (ret) { 1286 dev_dbg(dev->class_dev, "unable to allocate irq %d\n", 1287 pcidev->irq);
+1 -1
drivers/staging/comedi/drivers/cb_pcidas64.c
··· 4035 init_stc_registers(dev); 4036 4037 retval = request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED, 4038 - dev->board_name, dev); 4039 if (retval) { 4040 dev_dbg(dev->class_dev, "unable to allocate irq %u\n", 4041 pcidev->irq);
··· 4035 init_stc_registers(dev); 4036 4037 retval = request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED, 4038 + "cb_pcidas64", dev); 4039 if (retval) { 4040 dev_dbg(dev->class_dev, "unable to allocate irq %u\n", 4041 pcidev->irq);
+2 -2
drivers/staging/vt6655/rxtx.h
··· 150 u16 reserved; 151 struct ieee80211_cts data; 152 u16 reserved2; 153 - } __packed; 154 155 struct vnt_cts_fb { 156 struct vnt_phy_field b; ··· 160 __le16 cts_duration_ba_f1; 161 struct ieee80211_cts data; 162 u16 reserved2; 163 - } __packed; 164 165 struct vnt_tx_fifo_head { 166 u8 tx_key[WLAN_KEY_LEN_CCMP];
··· 150 u16 reserved; 151 struct ieee80211_cts data; 152 u16 reserved2; 153 + } __packed __aligned(2); 154 155 struct vnt_cts_fb { 156 struct vnt_phy_field b; ··· 160 __le16 cts_duration_ba_f1; 161 struct ieee80211_cts data; 162 u16 reserved2; 163 + } __packed __aligned(2); 164 165 struct vnt_tx_fifo_head { 166 u8 tx_key[WLAN_KEY_LEN_CCMP];