tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'samsung-fixes-4' of git://github.com/kgene/linux-samsung

* 'samsung-fixes-4' of git://github.com/kgene/linux-samsung:
ARM: S3C24XX: Fix s3c24xx build errors if !CONFIG_PM
ARM: S5P: fix offset calculation on gpio-interrupt

Linus Torvalds 1bf1aace 5117cc25

options
unified split
Changed files
+13 -3
arch
arm
mach-s3c2410
s3c2410.c
mach-s3c2412
s3c2412.c
mach-s3c2416
s3c2416.c
mach-s3c2440
s3c2440.c
s3c2442.c
plat-s5p
irq-gpioint.c
+2
arch/arm/mach-s3c2410/s3c2410.c
··· 170 170 { 171 171 printk("S3C2410: Initialising architecture\n"); 172 172 173 + #ifdef CONFIG_PM 173 174 register_syscore_ops(&s3c2410_pm_syscore_ops); 175 + #endif 174 176 register_syscore_ops(&s3c24xx_irq_syscore_ops); 175 177 176 178 return sysdev_register(&s3c2410_sysdev);
+2
arch/arm/mach-s3c2412/s3c2412.c
··· 245 245 { 246 246 printk("S3C2412: Initialising architecture\n"); 247 247 248 + #ifdef CONFIG_PM 248 249 register_syscore_ops(&s3c2412_pm_syscore_ops); 250 + #endif 249 251 register_syscore_ops(&s3c24xx_irq_syscore_ops); 250 252 251 253 return sysdev_register(&s3c2412_sysdev);
+2
arch/arm/mach-s3c2416/s3c2416.c
··· 97 97 98 98 s3c_fb_setname("s3c2443-fb"); 99 99 100 + #ifdef CONFIG_PM 100 101 register_syscore_ops(&s3c2416_pm_syscore_ops); 102 + #endif 101 103 register_syscore_ops(&s3c24xx_irq_syscore_ops); 102 104 103 105 return sysdev_register(&s3c2416_sysdev);
+2
arch/arm/mach-s3c2440/s3c2440.c
··· 55 55 56 56 /* register suspend/resume handlers */ 57 57 58 + #ifdef CONFIG_PM 58 59 register_syscore_ops(&s3c2410_pm_syscore_ops); 60 + #endif 59 61 register_syscore_ops(&s3c244x_pm_syscore_ops); 60 62 register_syscore_ops(&s3c24xx_irq_syscore_ops); 61 63
+2
arch/arm/mach-s3c2440/s3c2442.c
··· 169 169 { 170 170 printk("S3C2442: Initialising architecture\n"); 171 171 172 + #ifdef CONFIG_PM 172 173 register_syscore_ops(&s3c2410_pm_syscore_ops); 174 + #endif 173 175 register_syscore_ops(&s3c244x_pm_syscore_ops); 174 176 register_syscore_ops(&s3c24xx_irq_syscore_ops); 175 177
+3 -3
arch/arm/plat-s5p/irq-gpioint.c
··· 163 163 ct->chip.irq_mask = irq_gc_mask_set_bit; 164 164 ct->chip.irq_unmask = irq_gc_mask_clr_bit; 165 165 ct->chip.irq_set_type = s5p_gpioint_set_type, 166 - ct->regs.ack = PEND_OFFSET + REG_OFFSET(chip->group); 167 - ct->regs.mask = MASK_OFFSET + REG_OFFSET(chip->group); 168 - ct->regs.type = CON_OFFSET + REG_OFFSET(chip->group); 166 + ct->regs.ack = PEND_OFFSET + REG_OFFSET(group - bank->start); 167 + ct->regs.mask = MASK_OFFSET + REG_OFFSET(group - bank->start); 168 + ct->regs.type = CON_OFFSET + REG_OFFSET(group - bank->start); 169 169 irq_setup_generic_chip(gc, IRQ_MSK(chip->chip.ngpio), 170 170 IRQ_GC_INIT_MASK_CACHE, 171 171 IRQ_NOREQUEST | IRQ_NOPROBE, 0);